Microprocessor Supervisory Circuits

19-4333; Rev 4; 12/05 Microprocessor Supervisory Circuits General Description The reduce the complexity and number of components required for power-supply monitoring and battery-control functions in microprocessor (µp) systems. They significantly improve system reliability and accuracy compared to separate ICs or discrete components. These parts provide four functions: 1) A reset output during power-up, power-down, and brownout conditions. 2) Battery-backup switching for CMOS RAM, CMOS µp, or other low-power logic. 3) A reset pulse if the optional watchdog timer has not been toggled within 1.6sec. 4) A 1.25 threshold detector for power-fail warning or low-battery detection, or to monitor a power supply other than. The parts differ in their reset-voltage threshold levels and reset outputs. The // generate a reset pulse when the supply voltage drops below 4.65, and the / generate a reset below 4.4. The / guarantee power-fail accuracies to ±2%. The is the same as the except that is provided instead of. All parts are available in 8-pin DIP and SO packages. The / are pin compatible with the MAX690 and MAX694. The / are pin compatible with the MAX692. Applications UNREGULATED DC REGULATED R 1 R 2 Battery-Powered Computers and Controllers Intelligent Instruments Automotive Systems Critical µp Power Monitoring Typical Operating Circuit O.1µF 3.6 LITHIUM BATTERY WDI BATT OUT µp NMI I/O LINE BUS CMOS RAM Features Precision Supply-oltage Monitor: 4.65 for // 4.4 for / Reset Time Delay 200ms Watchdog Timer 1.6sec Timeout Battery-Backup Power Switching 200µA Quiescent Supply Current 50nA Quiescent Supply Current in Battery- Backup Mode oltage Monitor for Power-Fail or Low-Battery Warning Power-Fail Accuracy Guaranteed to ±2% (/M) Guaranteed Assertion to = 1 8-Pin SO and DIP Packages Ordering Information PART TEMP. RANGE PIN-PACKAGE CPA 0 C to +70 C 8 Plastic DIP CSA 0 C to +70 C 8 SO C/D 0 C to +70 C Dice* EPA -40 C to +85 C 8 Plastic DIP ESA -40 C to +85 C 8 SO MJA -55 C to +125 C 8 CERDIP** Ordering Information continued on last page. * Dice are specified at T A = +25 C **Contact factory for availability and processing to MIL-STD-883. Devices in PDIP and SO packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. Pin Configurations TOP IEW OUT 1 2 3 4 ( ) ARE FOR ONLY. DIP/SO 8 7 6 5 BATT () WDI Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim s website at www.maxim-ic.com.

ABSOLUTE MAXIMUM RATINGS Terminal oltage (with respect to )... -0.3 to 6. BATT... -0.3 to 6. All Other Inputs (Note 1)... -0.3 to ( + 0.3) Input Current... 200mA BATT... 50mA... 20mA Output Current OUT... Short-Circuit Protected for up to 10sec All Other Outputs... 20mA Rate of Rise,, BATT... 10/µs Continuous Power Dissipation Plastic DIP (derate 9.09mW/ C above +70 C)... 727mW SO (derate 5.88mW/ C above +70 C)... 471mW CERDIP (derate 8.00mW/ C above +70 C)... 640mW Operating Temperature Ranges: MAX69_AC, MAX80 C... 0 C to +70 C MAX69_AE, MAX80 E... -40 C to +85 C MAX69_AMJA, MJA... -55 C to +125 C Storage Temperature Range... -65 C to +160 C Lead Temperature (soldering, 10sec)... +300 C Note 1: The input voltage limits on and WDI may be exceeded if the current into these pins is limited to less than 10mA. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( = 4.75 to 5.5 for //, = 4.5 to 5.5 for /, BATT = 2.8, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MAX69_AC, MAX802_C 1.0 5.5 Operating oltage Range, C 1.1 5.5, BATT (Note 2) MAX69_AE/M, MAX80 E 1.2 5.5 MAX69_AC, MAX802_C 200 350 Supply Current (Excluding I OUT ) I SUPPLY MAX69_AE/M, MAX802_E, E/M 200 500 µa I SUPPLY in Battery-Backup Mode =, T A = +25 C 0.05 1.0 (Excluding I OUT ) BATT = 2.8 T A = T MIN to T MAX 5.0 µa BATT Standby Current (Note 3) 5.5 > > T A = +25 C -0.1 0.02 BATT +0.2 T A = T MIN to T MAX -1.0 0.02 µa OUT Output I OUT = 5mA - 0.05-0.025 I OUT = 50mA - 0.5-0.25 OUT in Battery-Backup Mode I OUT = 250µA, < BATT - 0.2 BATT - 0.1 BATT - 0.02 Battery Switch Threshold, Power-up 20 to < RT BATT Power-down -20 Battery Switchover Hysteresis 40 m,, 4.50 4.65 4.75 Reset Threshold RT, 4.25 4.40 4.50, T A = +25 C, falling 4.55 4.70, T A = +25 C, falling 4.30 4.45 Reset Threshold Hysteresis 40 m Reset Pulse Width t RS 140 200 280 ms Output oltage I SOURCE = 800µA - 1.5 I SINK = 3.2mA 0.4 MAX69_AC, MAX802_C, = 1. I SINK = 50µA MAX69_AE/M, MAX802_E, = 1.2, I SINK = 100µA 0.3 0.3 m 2

ELECTRICAL CHARACTERISTICS (continued) ( = 4.75 to 5.5 for //, = 4.5 to 5.5 for /, BATT = 2.8, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output oltage C, I SOURCE = 4µA, = 1.1 0.8 E/M, I SOURCE = 4µA, = 1.2 0.9, I SOURCE = 800µA - 1.5, I SINK = 3.2mA 0.4 Watchdog Timeout t WD 1.00 1.60 2.25 sec WDI Pulse Width t WP IL = 0.4, IH = (0.8) ( ) 50 ns WDI Input Threshold (Note 4) = 5 Logic low 0.8 Logic high 3.5 WDI Input Current WDI = 50 150 WDI = -150-50 µa Input Threshold MAX69_A,, = 5 1.20 1.25 1.30 MAX802_C/E, = 5 1.225 1.250 1.275 Input Current -25 0.01 25 na Output oltage I SOURCE = 800µA - 1.5 I SINK = 3.2mA 0.4 Note 2: Either or BATT can go to, if the other is greater than 2.. Note 3: "-" = battery-charging current, "+" = battery-discharging current. Note 4: WDI is guaranteed to be in an intermediate, non-logic level state if WDI is floating and is in the operating voltage range. WDI is internally biased to 35% of with an input impedance of 50kΩ. 3

Typical Operating Characteristics OUT () 5.00 4.95 4.90 4.85 4.80 4.75 0 SLOPE = 5Ω OUTPUT OLTAGE vs. LOAD CURRENT 10 20 30 40 50 I OUT (ma) RESPONSE TIME 10k 30pF 2µs/div OUTPUT OLTAGE vs. SUPPLY OLTAGE = BATT = +2.8 T A = +25 C T A = +25 C +4 1/div BATT OUT () 10k 2.80 2.78 2.76 2.74 2.72 2.70 +1.3 330 pf 0 OUTPUT OLTAGE vs. LOAD CURRENT SLOPE = 80Ω 0.2 0.4 0.6 0.8 1.0 1/div 1/div I OUT (ma) = BATT = +2.8 T A = +25 C POWER-FAIL COMPARATOR RESPONSE TIME 30pF +1.25 1k = T A = +25 C 400ns/div RESPONSE TIME +4 10k + +1.2 330pF +1.2 OUTPUT OLTAGE vs. SUPPLY OLTAGE +4 BATT = O T A = +25 C 500ms/div 2k 330pF POWER-FAIL COMPARATOR RESPONSE TIME 30pF +1.25 400ns/div 1k = T A = +25 C 1/div 1/div +3 +1.3 500ms/div 2µs/div 4

Pin Description PIN / / NAME 1 1 OUT 2 2 Supply Input 3 3 Ground 4 4 5 5 6 6 WDI 7 7 8 8 BATT FUNCTION Supply Output for CMOS RAM. When is above the reset threshold, OUT connects to through a P-channel MOSFET switch. When is below the reset threshold, the higher of or BATT will be connected to OUT. Power-Fail Comparator Input. When is less than 1.25, goes low. Connect to or when not used. Power-Fail Output. When is less than 1.25, goes low; otherwise stays high. Watchdog Input. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and reset is triggered. If WDI is left floating or connected to a high-impedance three-state buffer, the watchdog feature is disabled. The internal watchdog timer clears whenever reset is asserted, WDI is three-stated, or WDI sees a rising or falling edge. Reset Output. Whenever is triggered, it pulses low for 200ms. It stays low when is below the reset threshold (4.65 in the / and 4.4 in the /) and remains low for 200ms after rises above the reset threshold. A watchdog timeout also triggers. Active-High Reset Output is the inverse of. When is asserted, the output voltage = or BATT, whichever is higher. Backup-Battery Input. When falls below the reset threshold, BATT will be switched to OUT if BATT is 20m greater than. When rises to 20m above BATT, OUT will be reconnected to. The 40m hysteresis prevents repeated switching if falls slowly. 5

BATT WDI BATTERY-SWITCHOER CIRCUITRY 3.5 0.8 1.25 ( ) ARE FOR ONLY. Figure 1. Block Diagram 1.25 WATCHDOG TIMER GENERATOR OUT () Detailed Description Reset Output A microprocessor s (µp s) reset input starts the µp in a known state. When the µp is in an unknown state, it should be held in reset. The /// assert reset during power-up and prevent code execution errors during power-down or brownout conditions. On power-up, once reaches 1, is guaranteed to be a logic low. As rises, remains low. When exceeds the reset threshold, an internal timer keeps low for a time equal to the reset pulse width; after this interval, goes high (Figure 2). If a brownout condition occurs (if dips below the reset threshold), is triggered. Each time is triggered, it stays low for the reset pulse width interval. Any time goes below the reset threshold, the internal timer restarts the pulse. If a brownout condition interrupts a previously initiated reset pulse, the reset pulse continues for another 200ms. On powerdown, once goes below the threshold, is guaranteed to be logic low until droops below 1. is also triggered by a watchdog timeout. If a high or low is continuously applied to the WDI pin for 1.6sec, pulses low. As long as is assert- OUT () 3. 3. ( ) ARE FOR ONLY. Figure 2. Timing Diagram ed, the watchdog timer remains clear. When comes high, the watchdog resumes timing and must be serviced within 1.6sec. If WDI is tied high or low, a pulse is triggered every 1.8sec (t WD plus t RS ). The active-high output is the inverse of the /// output, and is guaranteed to be valid with down to 1.1. Some µps, such as Intel s 80C51, require an active-high reset pulse. Watchdog Input The watchdog circuit monitors the µp s activity. If the µp does not toggle the watchdog input (WDI) within 1.6sec, a reset pulse is triggered. The internal 1.6sec timer is cleared by either a reset pulse or by open circuiting the WDI input. As long as reset is asserted or the WDI input is open circuited, the timer remains cleared and does not count. As soon as reset is released or WDI is driven high or low, the timer starts counting. It can detect pulses as short as 50ns. Power-Fail Comparator The input is compared to an internal 1.25 reference. If is less than 1.25, goes low. The power-fail comparator is intended for use as an undervoltage detector to signal a failing power supply; it need not be dedicated to this function though, as it is t RS BATT = = 3. I OUT = 0mA 6

BATT SW1 SW2 CONDITION D1 SUBSTRATE OUT SW1/SW2 SW3/SW4 > Reset Threshold Open Closed < Reset Threshold and > BATT Open Closed < Reset Threshold and < BATT Closed Open THRESHOLD = 4.65 IN //. THRESHOLD = 4.4 IN / D2 D3 SW3 Figure 3. Backup-Battery Switchover Block Diagram completely separate from the rest of the circuitry. The external voltage divider drives to sense the unregulated DC input to the regulator (see Typical Operating Circuit). The voltage-divider ratio can be chosen such that the voltage at falls below 1.25 just before the regulator drops out. then triggers an interrupt which signals the µp to prepare for power-down. To conserve backup-battery power, the power-fail detector comparator is turned off and is forced low when BATT connects to OUT. Backup-Battery Switchover In the event of a brownout or power failure, it may be necessary to preserve the contents of RAM. With a backup battery installed at BATT, the devices automatically switch RAM to backup power when fails. As long as exceeds the reset threshold, OUT connects to through a 5Ω PMOS power switch. Once falls below the reset threshold, or BATT (whichever is higher) switches to OUT. Unlike the MAX690/MAX692, the don t always connect BATT to OUT when BATT is greater than. BATT connects to OUT (through an 80Ω switch) only when is below the reset threshold and BATT is greater than. SW4 0.1F + BATT ( ) ARE FOR ONLY. OUT () TO STATIC RAM TO µp Figure 4. Using a SuperCap as a Backup Power Source with a // and a ±5% Supply When exceeds the reset threshold, it is connected to the substrate, regardless of the voltage applied to BATT (Figure 3). During this time, the diode (D1) between BATT and the substrate will conduct current from BATT to if BATT is 0.6 or greater than. Table 1. SIGNAL OUT BATT WDI Input and Output Status in Battery-Backup Mode STATUS Disconnected from OUT Connected to BATT through an internal 80Ω PMOS switch Connected to OUT. Current drawn from the battery is less than 1µA, as long as < BATT - 1. Power-fail comparator is disabled. Logic low Logic low Logic high ( only) Watchdog timer is disabled 7

100k 0.1F + BATT OUT TO STATIC RAM TO µp Figure 5. Using a SuperCap as a Backup Power Source with the / and a ±10% Supply When BATT connects to OUT, backup mode is activated and the internal circuitry is powered from the battery (Table 1). When is just below BATT, the current drawn from BATT is typically 30µA. When drops to more than 1 below BATT, the internal switchover comparator shuts off and the supply current falls to less than 1µA. Applications Information Using a SuperCap as a Backup Power Source SuperCaps are capacitors with extremely high capacitance values, on the order of 0.1F. Figure 4 shows a SuperCap used as a backup power source. Do not allow the SuperCap s voltage to exceed the maximum reset threshold by more than 0.6. In Figure 4 s circuit, the SuperCap rapidly charges to within a diode drop of. However, after a long time, the diode leakage current will pull the SuperCap voltage up to. When using a SuperCap with the //, may not exceed 4.75 + 0.6 = 5.35. Use the SuperCap circuit of Figure 5 with a or and a ±10% supply. This circuit ensures that the SuperCap only charges to - 0.5. At the maximum of 5.5, the SuperCap charges up to 5., only 0.5 above the maximum reset threshold well within the requisite 0.6. SuperCap is a trademark of Baknor Industries. R 1 R 2 IN C1* TO µp R 3 L TRIP IN MAX690 H *OPTIONAL Figure 6. Adding Hysteresis to the Power-Fail Comparator Allowable Backup Power-Source Batteries Lithium batteries work very well as backup batteries due to very low self-discharge rates and high energy density. Single lithium batteries with open-circuit voltages of 3. to 3.6 are ideal. Any battery with an open-circuit voltage less than the minimum reset threshold plus 0.3 can be connected directly to the BATT input of the with Table 2. R 2 TRIP = 1.25/ R 2 + R 2 R IH 1.25/ 2 R 3 = R 1 + R 2 R 3 L 1.25 5 1.25 1.25 + = R 1 R 3 R 2 Allowable Backup-Battery oltages (see Using a SuperCap as a Backup Power Source section for use with a SuperCap) PART NO. / / / MAXIMUM BACKUP-BATTERY OLTAGE () 4.80 4.55 8

no additional circuitry (see the Typical Operating Circuit). However, batteries with open-circuit voltages that are greater cannot be used for backup, as current is sourced into the substrate through the diode (D1 in Figure 3) when is close to the reset threshold. Operation Without a Backup Power Source If a backup power source is not used, ground BATT and connect OUT to. Since there is no need to switch over to any backup power source, OUT does not need to be switched. A direct connection to eliminates any voltage drops across the switch which may push OUT below. Replacing the Backup Battery The backup battery can be removed while remains valid, without danger of triggering /. As long as stays above the reset threshold, batterybackup mode cannot be entered. In other switchover ICs where battery-backup mode is entered whenever BATT gets close to, an unconnected BATT pin R 1 R 2-5 1.25 1.25 - = TRIP NOTE: R1 TRIP IS NEGATIE R2 TRIP - accumulates leakage charge and triggers / in error. Adding Hysteresis to the Power-Fail Comparator Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of when IN is close to its trip point. Figure 6 shows how to add hysteresis to the power-fail comparator. Select the ratio of R 1 and R 2 such that sees 1.25 when IN falls to its trip point ( TRIP ). R 3 adds the hysteresis. It will typically be an order of magnitude greater than R 1 or R 2 (about 10 times either R 1 or R 2 ). The current through R 1 and R 2 should be at least 1µA to ensure that the 25nA (max) input current does not shift the trip point. R 3 should be larger than 10kΩ so it does not load down the pin. Capacitor C1 adds additional noise rejection. Monitoring a Negative oltage The power-fail comparator can be used to monitor a negative supply rail using the circuit of Figure 7. When the negative rail is good (a negative voltage of large magnitude), is low. When the negative rail is degraded (a negative voltage of lesser magnitude), goes high. This circuit s accuracy is affected by the threshold tolerance, the line, and the resistors. Interfacing to µps with Bidirectional Reset Pins µps with bidirectional reset pins, such as the Motorola 68HC11 series, can contend with the /// output. If, for example, the output is driven high and the µp wants to pull it low, indeterminate logic levels may result. To correct this, connect a 4.7kΩ resistor between the output and the µp reset I/O, as in Figure 8. Buffer the output to other system components Figure 7. Monitoring a Negative oltage 9

BUFFERED TO OTHER SYSTEM COMPONENTS 4.7k Figure 8. Interfacing to µps with Bidirectional Reset I/O 10

µp Supervisory Circuits Minimum Nominal Nominal Reset Watchdog Power- Reset Pulse Timeout Backup- CE - Fail Manual- Watch- Low- Active- Battery- Part Threshold Width Period Battery Write Com- Reset dog Line High On Number () (ms) (sec) Switch Protect parator Input Output Output Reset Output /692A 4.65/4.40 140 1.6 MAX691A/693A 4.65/4.40 140/adj. 1.6/adj. /10ns MAX696 Adj. 35/adj. 1.6/adj. MAX697 Adj. 35/adj. 1.6/adj. MAX700 4.65/adj. 200 - MAX703/704 4.65/4.40 140 - MAX705/706 4.65/4.40 140 1.6 MAX706P 2.63 140 1.6 MAX706R/S/T 2.63/2.93/ 140 1.6 3.08 MAX707/708 4.65/4.40 140 - MAX708R/S/T 2.63/2.93/ 140-3.08 MAX709L/M/ 4.65/4.40/ 140 - R/S/T 2.63/2.93/3.08 MAX791 4.65 140 1 /10ns MAX792L/M/ 4.65/4.40/ 140 1 /10ns R/S/T 2.63/2.93/3.08 MAX800L/M 4.60/4.40 140 1.6/adj. /10ns /±2% /M 4.60/4.40 140 1.6 /±2% 4.65 140 1.6 MAX813L 4.65 140 1.6 MAX820L/M/ 4.65/4.40/ 140 1 /10ns /±2% R/S/T 2.63/2.93/3.08 MAX1232 4.37/4.62 250 0.15/0.60/1.2 MAX1259 - - - 11

Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE CPA 0 C to +70 C 8 Plastic DIP CSA 0 C to +70 C 8 SO C/D 0 C to +70 C Dice* EPA -40 C to +85 C 8 Plastic DIP ESA -40 C to +85 C 8 SO MJA -55 C to +125 C 8 CERDIP** CPA 0 C to +70 C 8 Plastic DIP CSA 0 C to +70 C 8 SO EPA -40 C to +85 C 8 Plastic DIP ESA -40 C to +85 C 8 SO CPA 0 C to +70 C 8 Plastic DIP CSA 0 C to +70 C 8 SO EPA -40 C to +85 C 8 Plastic DIP ESA -40 C to +85 C 8 SO CPA 0 C to +70 C 8 Plastic DIP CSA 0 C to +70 C 8 SO C/D 0 C to +70 C Dice* EPA -40 C to +85 C 8 Plastic DIP ESA -40 C to +85 C 8 SO MJA -55 C to +125 C 8 CERDIP** * Dice are specified at T A = +25 C. **Contact factory for availability and processing to MIL-STD-883. Devices in PDIP and SO packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. Chip Topography OUT BATT 0.078" (1.98mm) ( ) ARE FOR ONLY. TRANSISTOR COUNT: 573; SUBSTRATE MUST BE LEFT UNCONNECTED. () 0.061" WDI (1.55mm) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.