ENGG1203: Introduction to Electrical and Electronic Engineering Second Semester, 2014 15 Lab 1 Objective: To practice combinational logic on Logisim and Xilinx ISE tools. 1 Find your lab partner You will be working with a randomly assigned partner for this lab. To find your assigned lab partner and the assigned table, 1. Log in to Moodle. 2. Select the assignment Lab 1 Partner Please proceed to your assigned table. 2 Get the files Download the files for this lab from http://www.eee.hku.hk/~engg1203/sp15/labs/lab1.zip Save your file on the Desktop. If you save it at any other locations, make sure the folder name contains only simple english characters and numbers. Do not include space or any other symbols in the path. To unzip the file: Right click the downloaded file. Select Extract All... 3 Logisim In this part of the lab, you will get familiar with the software Logisim, which we will be using to simulate the behavior of digital logic circuits. If you would like to run Logisim on your own computer, you may download it from http://www.cburch.com/logisim/index.html. 3.1 Implement the following circuit in Logisim. A B P Q Figure 1: Y To insert a logic gate, expand the folder Gates and click on the desired logic gate. Once the gate is selected, the mouse will turn into the shape of the selected gate. Place the gate in the circuit area on the right.
To connect the gates, select the arrow icon on top ( ). Then drag from the output of one gate to the input of another gate. You can connect to any of the small blue dots on the gate symbol. To create an input to the circuit, select the Add Pin icon with an outline of a square ( ). Similarly, add an output to the circuit by using the Add Pin icon with an outline of a circle ( ). To assign a name to the input/output pin, click on the pin while the arrow icon ( You may then add the label for the pins, in this case, a, b and y for output. ) is selected. Once you have connected the circuit, you will notice the color of the wire changes. A dark green color means that the current value on the wire is a logical 0, while a light green color signifies a 1. Other wire colors: blue = unknown value, gray = unconnected, red = conflict. For more information, consult the Logisim online help file. In particular, the section on Beginner s Tutorial can be very helpful. 3.2 Select the poke tool ( ) so you can test the circuit. You can toggle the value of an input pin by clicking on it using the poke tool. Note the values of all subsequent wires change instantly. Using this tool, complete the following truth table of the given circuit. Note that we have put 3 columns on the right hand side. It is a simple short hand so we can see the internal node values (p, q) together with the final output y. a b p q y 0 0 0 1 1 0 1 1 3.3 Write down the boolean expression for p, q in terms of a, b. p = q = 3.4 Write down the boolean expression for y in terms of p and q, then substitute your answer from above to express y in terms of a and b. y = 3.5 Checkoff 1 Page 2 of 6
The given circuit performs the function of a simple gate. What is that function? Show your truth table and your boolean expression of the circuit to your TA. Before you ask for a TA to checkoff you work, log in to the Moodle account of any one of the group partners. Click on Lab 1 Checkoff 1. 4 Testing on real hardware While Logisim allows easy simulation of digital logic circuit, we will use a different software that helps us implement the digital circuit in real hardware. In this course, we will be using the Basys2 board for hardware implementation, which contains a programmable hardware integrated circuit called Field Programmable Gate Array (FPGA). An FPGA is a special hardware that is reprogrammable by a user. Once configured, the FPGA operates in the same way as if the desired hardware functions were physically implemented in hardware. Note that although it is programmable, an FPGA is not a microprocessor. This is the reason we need to configure it using a specially designed software. We will be using the Xilinx ISE tools for this purpose. Warning: As an industrial standard software, the Xilinx ISE tools can be very cumbersome and complicated at times. But once you are used to the steps, they will become much simpler. 4.1 Start ISE by double-clicking on the icon ISE Design Suite 14.2. Open the project file lab1/lab1a/lab1a.xise that you have downloaded. This will start an empty project with settings configured for the Basys2 board. 4.2 Add a Schematic We will implement the same circuit in Figure 1 using the Basys2 as an exercise. To add a schematic design into the project, do the following: 1. Select Project New Source from the menu. 2. Choose Schematic 3. Type the name lab1a in the File name field. 4. Click Next 5. Click Finish Once you have added the new source lab1a.sch, it will automatically be opened on the top right. 4.3 Adding symbols To add the necessary logic components, click on the Add Symbol button near the center of the screen. Select Logic under Categories. This is where you can find simple logic gates that we have covered in class are listed. 4.4 Finding those gates For a 2-input AND gate, select and2. For a 2-input NOR gate, select nor2. Select the gates and place them in the circuit on the right. To connect the gates with wires, select the Add Wire tool output of a gate to the input of another gate. and drag a connection from the Page 3 of 6
4.5 Input/Output To connect your schematic with the rest of the world, you need to specify the I/O ports. For that, select the button Add I/O marker. The default setting will automatically detect the I/O direction of the marker. Click on the input to a gate and you will see that an input marker is automatically created, and vise versa. Finally, name your I/O ports. Follow the name as shown in the above circuit figure: Name the input a and b respectively; Name the output y. NOTE: You must name them exactly as a, b, and y in preparation for next step. To rename an I/O marker, right click on the marker and select Rename Port. 4.6 Implement the design The FPGA is configured by a special bit file with a.bit extension. To generate the necessary bit file for your design, do the following: 1. Select the Design tab in Project Navigator; 2. double click Implement Design. 3. double click Generate Programming File, which is the step below Implement Design. If everything go smoothly, you should have your first FPGA programming bit file in about 5 minutes. 4.7 Connecting the Basys2 Connect the Basys2 to the computer using the provided USB cable. The Basys2 board is powered by the USB cable and no external power supply is needed. Once connected, turn on the Basys2 power switch. You should see the 7-segment display starts running. 4.8 Download to the real circuit The final step is to download the circuit to the Basys2 board. Double click on the Configure Target Device step in project navigator. A new software, called impact will launch. A warning will display saying no configuration for impact is found. We will create a configuration in the following steps. In impact, double click Boundary Scan on the left. Select Initialize JTAG chain or type Ctrl-I. It will detect the attached board and initialize the system. If correct, you should see two chips detected. When asked Do you want to continue and assign configuration file(s), click Cancel. We will manually set the configuration in next step. Right click on the first chip labeled xc3s100e and select Assign New Configure File.... Page 4 of 6
Select lab1a.bit as the configuration. Click NO when asked if you want to attach the SPI. Finally, right click on the xc3s100e and select Program. If things are correct, you should see that the 7-segment display is now off. Optional: If you want to skip the configuration step in future, you can save the impact configuration and use that configuration in the Configure Target Device step above. See the ISE manual for more details. 4.9 Testing your circuit The two inputs, a and b are connected to the first two switches, labeled sw0 and sw1 on the board. The output y is connected to the first LED led0. To test your circuit, try switching sw0 and sw1 between HIGH and LOW and see if led0 lights up as expected. 4.10 Checkoff 2 Demonstrate to your TA your working circuit on the Basys2. Show your schematic to your TA and explain the process to generate the FPGA configuration from the top-level schematics. Before you ask for a TA to checkoff you work, log in to the Moodle account of any one of the group partners. Click on Lab 1 Checkoff 2. 5 3-input XOR In this part of the lab, you will practice the skills you have learned so far to build a slightly more complex circuit a 3-input XOR gate. A 3-input XOR gate has three inputs a, b and c and outputs a 1 when there is an odd number of 1 among the inputs. 5.1 A 3-input XOR gate has the following Boolean expression: y = a b c. Draw in the following area the schematic of such 3-input XOR gate using two 2-input XOR gates. 5.2 Based on the above schematic, implement a 3-input XOR gate in the Xilinx ISE schematic editor. To implement the design, 1. Open the project lab1b.xise 2. Select Project New Source 3. Select Schematic and name your file lab1b Page 5 of 6
5.3 Once you have a blank schematic, complete the design of 3-input XOR gate using two 2- input XOR gates (xor2 under the Logic categories) to reproduce the schematic you have designed above. Name your inputs a, b, and c, and name your output y. 5.4 Mapping to the correct I/O You may notice that there are many switches and buttons on the Basys2 board. How did the ISE tools know that the I/O port of signal a should map to sw0 and b should map to sw1? The answer is in a user constraints file (.ucf file). In the blank project you ve downloaded, you should see a file called lab1b.ucf has already been added for you. Double click the file to open it. The content of this file determines where each I/O port in the circuit should be connected to physically in the board. Go to line 68 and 69, you will see the NET a is mapped to location (LOC) P11. It tells the software that the wire representing a should be connected physically to I/O pin P11 of the FPGA, which in turn is connected to switch 0 on the Basys2 board. Now uncomment the line that started with NET c. Compare to the line above, you see that we are now connecting the input signal c to the push button 0 on the Basys2 board. 5.5 Implement To implement your design, 1. Click on the top design module, lab1b.sch in Project Navigator 2. Implement your design by double-clicking the Process Implement Design 5.6 Download and Test Download your design to the Basys2 board following the same procedure above, except you want to download lab1b.bit this time. Test your circuit with the switches sw0, sw1 and push button btn0. 5.7 Checkoff 3 Demonstrate your working 3-input XOR gate on the Basys2 board and the schematics. While keeping a and b unchanged, explain what happens to the output by pushing btn0. What logical function does input c provide with respect to a and b? Before you ask for a TA to checkoff you work, log in to the Moodle account of any one of the group partners. Click on Lab 1 Checkoff 3. 5.8 Optional: 3-input XOR in Logisim Implement a 3-input XOR gate in Logisim without using the built-in XOR gate. You should first make the circuit in Figure 1 as a subcircuit in Logisim and reuse it in your implementation of 3-input XOR gate. To learn how to use subcircuit, select from Logisim Help User s Guide. Then select the section on Subcircuits. Verify the function of your circuit by experimenting with different input values using the Poke tool. Page 6 of 6