Features. Description. Table 1. Device summary. Quality level. Package. Engineering model SMD.5 Gold 2-55 to 150 C

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Rad-Hard N-channel 60 V, 30 A Power MOSFET Features Datasheet - production data V BDSS I D R DS(on) Q g 60 V 30 A 36 mω 43 nc SMD.5 Fast switching 100% avalanche tested Hermetic package 50 krad TID SEE radiation hardened Applications Figure 1. Internal schematic diagram Satellite High reliability Description This N-channel Power MOSFET is developed with STMicroelectronics unique STripFET process. It has specifically been designed to sustain high TID and provide immunity to heavy ion effects. This Power MOSFET is fully ESCC qualified. Table 1. Device summary Part numbers ESCC part number Quality level Package Lead finish Mass (g) Temp. range EPPL STRH40N6S1 - Engineering model SMD.5 Gold 2-55 to 150 C - STRH40N6SG 55/024/01 ESCC flight Target Note: Contact ST sales office for information about the specific conditions for tape and reel, product in die form and other packages. March 16 DocID18351 Rev 10 1/ This is information on a product in full production. www.st.com

Contents STRH40N6 Contents 1 Electrical ratings............................................ 3 2 Electrical characteristics..................................... 5 2.1 Pre-irradiation............................................... 5 3 Radiation characteristics..................................... 8 4 Electrical characteristics (curves)............................. 11 5 Test circuits............................................... 14 6 Package information........................................ 15 6.1 SMD.5 package information................................... 15 7 Order code................................................ 17 7.1 Other information........................................... 18 8 Revision history........................................... 19 2/ DocID18351 Rev 10

Electrical ratings 1 Electrical ratings (T C = 25 C unless otherwise specified) Table 2. Absolute maximum ratings (pre-irradiation) Symbol Parameter Value Unit V DS (1) V GS (2) I D (3) Drain-source voltage (V GS = 0) 60 V Gate-source voltage ± V Drain current (continuous) at T C = 25 C 30 A I D (3) Drain current (continuous) at T C = 100 C 19 A I DM (4) P TOT (5) Drain current (pulsed) 1 A Total dissipation at T C = 25 C 75 W P TOT (3) Total dissipation at T C = 25 C 66 W dv/dt (6) Peak diode recovery voltage slope 2.5 V/ns T stg Storage temperature -55 to 150 C T j Max. operating junction temperature 150 C 1. This rating is guaranteed @ T J 25 C (see Figure 10: Normalized BV DSS vs temperature). 2. This value is guaranteed over the full range of temperature. 3. Rated according to the R thj-case + R thc-sink 4. Pulse width limited by safe operating area 5. Rated according to the R thj-case 6. I SD 40 A, di/dt 1060 A/µs, V DD = 80 %V (BR)DSS Table 3. Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case 1.67 C/W R thc-sink thermal resistance case-sink 0.21 C/W R thj-amb (1) Thermal resistance junction -amb 50 C/W 1. When mounted on heat sink of 300 mm², t < 10 sec DocID18351 Rev 10 3/

Electrical ratings STRH40N6 Table 4. Avalanche characteristics Symbol Parameter Value Unit I AR (1) E AS E AS E AR Avalanche current, repetitive or not-repetitive (pulse width limited by T j max) Single pulse avalanche energy (starting T J = 25 C, Id = A, V dd = 40 V) Single pulse avalanche energy (starting T J = 110 C, Id= A, V dd = 40 V) Repetitive avalanche (V dd = 50 V, I AR = 17.5 A, f = 10 KHz, T J = 25 C, duty cycle = 50%) Repetitive avalanche (V dd = 40 V, I AR = 15 A, f = 100 KHz, T J = 25 C, duty cycle = 10%) Repetitive avalanche (V dd = 40 V, I AR = 15 A, f = 100 KHz, T J = 110 C, duty cycle = 10%) 15 A 354 mj 105 1.3 mj 0.4 1. Maximum rating value. 4/ DocID18351 Rev 10

Electrical characteristics 2 Electrical characteristics (T C = 25 C unless otherwise specified). 2.1 Pre-irradiation Table 5. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit I DSS I GSS BV DSS (1) V GS(th) R DS(on) Zero gate voltage drain current (V GS = 0) Gate body leakage current (V DS = 0) Drain-to-source breakdown voltage Gate threshold voltage Static drain-source on resistance 80% BV Dss 10 ua 80% BV Dss, T C = 125 C 100 ua V GS = V 100 na V GS = - V -100 na V GS = V, T C = 125 C 0 na V GS = - V, T C = 125 C -0 na V GS = 0, I D = 1 ma 60 V V DS = V GS, I D = 1 ma 2 4.5 V V DS = V GS, I D = 1 ma, T C = 125 C 1.5 3.7 V DS = V GS, I D = 1 ma, T C = -55 C 2.1 5.5 V V GS = 12 V, I D = 15 A 0.036 0.045 V GS = 12 V, I D = 15 A, T C = 125 C 0.076 Ω 1. This rating is guaranteed @ T J 25 C (see Figure 10: Normalized BV DSS vs temperature). DocID18351 Rev 10 5/

Electrical characteristics STRH40N6 Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance 1312 1640 1968 pf C (1) oss Output capacitance V GS = 0, V DS = 25 V, 281 351 421 pf C rss f = 1MHz Reverse transfer capacitance 111 139 167 pf Q g Total gate charge 35 43 52 nc Q gs Gate-to-source charge V DD = 30 V, I D = 40 A, 9 11 13 nc Q gd V GS = 12 V Gate-to-drain ( Miller ) charge 12 15 18 nc R G (2) Gate input resistance 1. This value is guaranteed over the full range of temperature. 2. Not tested, guaranteed by process. f = 1MHz Gate DC bias=0 test signal level= mv open drain 1.04 1.3 1.56 Ω Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time 13 17 21 ns t r Rise time V DD = 30 V, I D = A, 26 59 92 ns t d(off) Turn-off-delay time R G = 4.7 Ω, V GS = 12 V 18 33 48 ns t f Fall time 7 11.5 16 ns 6/ DocID18351 Rev 10

Electrical characteristics Table 8. Source drain diode (1) Symbol Parameter Test conditions Min. Typ. Max Unit I SD Source-drain current 30 A (2) I SDM (3) V SD t (4) rr (4) Q rr (4) I RRM t (4) rr (4) Q rr (4) I RRM Source-drain current (pulsed) Forward on voltage 1 A I SD = 30 A, V GS = 0 1.1 1.5 V I SD = 30 A, V GS = 0,T C = 125 C 1.275 V Reverse recovery time 288 360 432 ns Reverse recovery charge I SD = 40 A, di/dt = 100 A/µs V DD = 48 V, Tj = 25 C 3.3 µc Reverse recovery current 18.2 A Reverse recovery time 352 440 529 ns Reverse recovery charge I SD = 40 A, di/dt = 100 A/µs V DD = 48 V, Tj = 150 C 4.4 µc Reverse recovery current 19.8 A 1. Refer to the Figure 16: Source drain diode. 2. Pulse width limited by safe operating area. 3. Pulsed: pulse duration = 300µs, duty cycle 1.5% 4. Not tested in production, guaranteed by process. DocID18351 Rev 10 7/

Radiation characteristics STRH40N6 3 Radiation characteristics The STMicroelectronics Rad-Hard technology renders these Power MOSFETs extremely resistant to radiative environments. Every manufacturing lot is tested with the TO-3 package for total ionizing dose (according to ESCC 22900 Basic Specification, Window 1), and single event effects (according to MIL-STD-750E Method 1080), up to 3e+5 ions/cm² fluence. Both pre-irradiation and post-irradiation performance characteristics are tested and specified using the same circuitry and test conditions for direct comparison. (T amb = 22 ± 3 C unless otherwise specified). Total dose radiation (TID) testing One bias conditions using the TO-3 package: V GS bias: + 15 V applied and V DS = 0 V during irradiation The following parameters are measured (see Table 9, Table 10 and Table 11): before irradiation after irradiation after 24 hrs @ room temperature after 168 hrs @ 100 C anneal Table 9. Post-irradiation on/off states @ T J = 25 C, (Co60 γ rays 50 K Rad(Si) Symbol Parameter Test conditions Drift values Δ Unit I DSS I GSS Zero gate voltage drain current (V GS = 0) Gate body leakage current (V DS = 0) 80% BV Dss + µa V GS = V V GS = - V 1.5-1.5 BV DSS Drain-to-source breakdown voltage V GS = 0, I D = 1 ma -% V V GS(th) Gate threshold voltage V DS = V GS, I D = 1 ma -60% / +% V R DS(on) Static drain-source on-resistance V GS = 10 V; I D = A ±10% Ω na Table 10. Dynamic post-irradiation @ T J = 25 C, (Co60 γ rays 50 K Rad(Si)) Symbol Parameter Test conditions Drift values Δ Unit Q g Total gate charge -5% / +50% Q gs Gate-source charge I G = 1 ma, V GS = 12 V, V DS = 30 V, I DS = A ±35% Q gd Gate-drain charge -5% / +110% nc 8/ DocID18351 Rev 10

Radiation characteristics Table 11. Source drain diode post-irradiation @ T J = 25 C, (Co60 γ rays 50 K Rad(Si)) (1) Symbol Parameter Test conditions Drift values Δ. Unit V SD (2) Forward on voltage I SD = 40 A, V GS = 0 ±5% V 1. Refer to Figure 16. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Single event effect, SOA The STMicroelectronics Rad-Hard technology renders these Power MOSFETs extremely resistant to heavy ion environments for single event effects (irradiation as per MIL-STD- 750E, method 1080 bias circuit in Figure 3.: Single event effect, bias circuit: SEB and SEGR tests were performed with a fluence of 3e+5 ions/cm². The accept/reject criteria are: Single-event burnout (SEB) test: drain voltage checked, trigger level is set to V ds = - 5 V. Stop condition: as soon as a SEB occurs or if the fluence reaches 3e+5 ions/cm². Single-event gate rupture (SEGR) test: the gate current is monitored every 100 ms. A gate test is performed before and after irradiation. Stop condition: as soon as the gate current reaches 100 na (during irradiation or during PIGS test) or if the fluence reaches 3e+5 ions/cm². The results are: SEB immune at 60 MeV/mg/cm2 SEGR immune at 60 MeV/mg/cm 2 within the safe operating area (SOA) given in Table 12: Single event effect (SEE), safe operating area (SOA) and Figure 2: Single event effect, SOA Table 12. Single event effect (SEE), safe operating area (SOA) Ion Let (Mev/(mg/cm 2 ) Energy (MeV) Range (µm) V DS (V) V GS =0 V GS = -2 V V GS = -5 V V GS = -10 V V GS = -15 V V GS = - V Kr 32 768 94 60 48 39 27 15 Br 38 300 38 45 25 15 15 I 61 330 31 25 15 DocID18351 Rev 10 9/

Radiation characteristics STRH40N6 Figure 2. Single event effect, SOA Figure 3. Single event effect, bias circuit (a) a. Bias condition during radiation refer to Table 12: Single event effect (SEE), safe operating area (SOA). 10/ DocID18351 Rev 10

Electrical characteristics (curves) 4 Electrical characteristics (curves) Figure 4. Safe operating area Figure 5. Thermal impedance Figure 6. Output characteristics Figure 7. Transfer characteristics ID (A) 1 VGS=10V HV33010 ID (A) AM07252v1 100 VGS=8V VGS=7V 100 80 Tj= +25 C 60 40 VGS=6V VGS=5V 10 Tj= +150 C Tj= -55 C 0 0 5 10 15 VDS(V) 1 3.5 4.5 5.5 6.5 VGS(V) DocID18351 Rev 10 11/

Electrical characteristics (curves) STRH40N6 Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations VGS (V) 12 10 8 VDD=30 V Ig=1.3 ma HV330 C (pf) 1000 Ciss Coss HV33030 6 4 2 ID=40 A ID= A ID=10 A 0 0 10 30 40 50 Qg(nC) Figure 10. Normalized BV DSS vs temperature 100 Crss 10 0.1 1 10 VDS(V) Figure 11. Static drain-source on-resistance Figure 12. Normalized gate threshold voltage vs temperature Figure 13. Normalized on-resistance vs temperature 12/ DocID18351 Rev 10

Electrical characteristics (curves) Figure 14. Source drain-diode forward characteristics DocID18351 Rev 10 13/

Test circuits STRH40N6 5 Test circuits Figure 15. Switching times test circuit for resistive load (1) VGS VD RG RL D.U.T. 20 µf 3.3 µf VDD PW AM01468v1 1. Max driver V GS slope = 1V/ns (no DUT) Figure 16. Source drain diode Figure 17. Unclamped inductive load test circuit (single pulse and repetitive) L VD 20 µf 3.3 µf VDD ID Vi D.U.T. Pw AM01471v1 14/ DocID18351 Rev 10

Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 SMD.5 package information Figure 18. SMD.5 package outline Pin n 1 identification (7386434 rev.5) DocID18351 Rev 10 15/

Package information STRH40N6 Table 13. SMD.5 mechanical data Dim. mm Inch Min. Typ. Max. Min. Typ. Max. A 2.84 3.00 3.15 0.112 0.118 0.124 A1 0.25 0.38 0.51 0.010 0.015 0.0 b 7.13 7.26 7.39 0.281 0.286 0.291 b1 5.58 5.72 5.84 0.2 0.225 0.230 b2 2.28 2.41 2.54 0.090 0.095 0.100 b3 2.92 3.05 3.18 0.115 0.1 0.125 D 10.03 10.16 10.28 0.935 0.400 0.405 D1 0.76 0.030 E 7.39 7.52 7.64 0.291 0.296 0.301 e 1.91 0.075 16/ DocID18351 Rev 10

Order code 7 Order code Table 14. Ordering information Order code ESCC part number Quality level EPPL Package Lead finish Marking Packing STRH40N6S1 - Eng model - STRH40N6S1 SMD.5 Gold +BeO STRH40N6SG 55/024/01 ESCC flight Target 5502401F Strip pack For specific marking only the complete structure is: ST Logo ESA Logo Date code (date of sealing of the package) : YYWWA YY: year WW: week number A: week index ESCC part number (as mentioned in the table) Warning signs (e.g. BeO) Country of origin: FR (France) Serial number of the part within the assembly lot Contact ST sales office for information about the specific conditions for products in die form and for other packages. DocID18351 Rev 10 17/

Order code STRH40N6 7.1 Other information Date code The date code for ESCC flight is structured as follows: yywwz where: yy: last two digits of year ww: week digits z: lot index in the week Documentation The table below provide a summary of the documentation provided with each type of products. Table 15. Summary of the documentation provided Quality level Radiation level Documentation Engineering model - - ESCC flight 50 Krad Certificate of conformance radiation verification test report 18/ DocID18351 Rev 10

Revision history 8 Revision history Table 16. Document revision history Date Revision Changes 03-Jan-11 1 First release. 25-Aug-11 2 Updated order codes in Table 1: Device summary and Table 14: Ordering information. Minor text changes. 09-Nov-11 3 28-Mar-12 4 Updated title in cover page. Updated dynamic values on Table 7: Pre-irradiation switching times. Document status changed from preliminary data to datasheet. 03-Oct-12 5 Figure 4: Safe operating area has been modified. 01-Jul-13 6 Updated order codes in Table 1: Device summary, Table 12: Single event effect (SEE), safe operating area (SOA), Figure 2: Single event effect, SOA and Table 14: Ordering information. Added Section 7.1: Other information. Minor text changes. 09-Sep-13 7 Updated features in cover page. 14-May-14 8 Updated Table 5: Pre-irradiation on/off states. 19-May-14 9 04-Mar-16 10 Updated Table 9: Post-irradiation on/off states @ TJ= 25 C, (Co60 g rays 50 K Rad(Si)). Updated: Features, Table 5, Table 8,Table 9,Table 10, Table 11 and Table 15. Updated Section 6: Package information. Minor text changes. DocID18351 Rev 10 19/

IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 16 STMicroelectronics All rights reserved / DocID18351 Rev 10