Digital Integrated Circuits A Design Perspective The Inverter
Introduction The inverter is the simplest of all digital logic gates However, building an understanding of its properties and operation is crucial for the design and analysis of larger/ more complex logic gates. We will discuss: General properties of an inverter (and logic gates), and inverter implementation issues in CMOS technology.
General Properties Small area is a desirable property for a digital logic gate Larger packing density Small parasitic capacitances Shorter interconnects Smaller chip area, hence higher number of devices per wafer (lower cost) Fewer transistors for a logic gate usually results into smaller area. Hence, minimum possible number of transistors for a given gate is important.
The CMOS Inverter: A First Glance V DD C L
CMOS Inverter - First-Order DC Analysis V DD V DD R p Properties 1) High and low outputs = V DD and Ground. Voltage swing= V DD. High Noise Margins. 2) Logic Levels are independent of device sizes (ratioless logic) 3) In steady state, a path exists from O/P to V DD or GND. Thus, low output impedance. Less sensitive to noise. 4) Input resistance is extremly high, since MOS gate draws no dc input current. Steady-state input current ~ zero. An inverter can theoretically drive infinite number of gates and be functionally operational. This degrades the transient response. 5) In steady-state, no direct path exists between supply and ground rails. No static power (ignoring leakage) R n = V DD = 0 V OL = 0 V OH = V DD V M = f(r n, R p )
Voltage Transfer Characteristic
PMOS Load Lines I V V DSp GSn DSn = I = V = V in out DSn ; V ; V GSp DSp = V in = V V out DD V DD I Dp =0 I Dn I Dn =0 =1.5 =1.5 V GSp =-1 V DSp V DSp V GSp =-2.5 = V DD +V GSp I Dn = - I Dp = V DD +V DSp
CMOS Inverter Load Characteristics I Dn = 0 = 2.5 PMOS = 0.5 = 2 NMOS = 1 = 1.5 = 1.5 = 1 = 2 = 1.5 = 1 = 0.5 = 2.5 = 0 For a dc operating point to be valid, the currents through NMOS and PMOS devices must be equal (intersections) { = 0, 0.5, 1, 1.5, 2, 2.5} Operating points are located either at the high or low output levels. The Voltage Transfer Characteristics (VTC) exhibit a very narrow transition zone (high gain during switching transient a small change in the input voltage results in a large output variation)
CMOS Inverter VTC (V DD =2.5V) (V DD NMOS off PMOS res = 0.5 1 1.5 2 2.5 NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat V M = switching threshold NMOS res PMOS off 0.5 1 1.5 2 2.5
Switching Threshold as a function of Transistor Ratio = PMOS and NMOS are saturated since V DS =V GS. Equate current through NMOS and PMOS. V (V) M 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 V M rv 1 + r DD 0.8 10 0 10 1 W p /W n V M =V DD /2 for comparable high and low noise margins. Thus, r=1. ( W / L) = ( W / L) p n ( V DSATn k ' n ) /( V DSATp k ' p ) Increasing strength of NMOS (sizing it up), moves V M closer to GND. Vice versa for PMOS case. Note: When designing CMOS circuits, it is advisable to balance the strengths of the transistors by making PMOS wider than NMOS, to obtain large noise margins + symmetrical characteristics.
Switching Threshold as a function of Transistor Ratio Points V M is relatively insensitive to variations in the device ratio. Small variations of the ratio do not disturb the VTC that much. Setting ratio of W p /W n to {3, 2.5, 2} yields switching thresholds of {1.22V, 1.18V, 1.13V} V M shifts towards V DD or GND depending on strength of NMOS and PMOS. Asymmetrical VTC is sometimes desirable in some designs. Example in Page 187.
Noise Margin - Determining V IH and V IL In real life applications, output voltage of a gate may not have the nominal value, owing to load, high switching speed..etc. Hence, it is desirable to define an acceptable voltage range for logic 1 and logic 0 V OH V M V OL A simplified approach V IL V IH These expressions make it clear that a high gain in the transition region is very desirable. For infinite gain: NM H =V DD -V M, NM L =V M Logic gates have the property to restore the proper output logic values despite of non-ideal input levels.
Inverter Gain 0-2 -4-6 gain -8-10 -12-14 NMOS and PMOS are in saturation. Equate currents. Differentiate and solve for d /d The gain is almost purely determined by technology parameters, especially the channel-length modulation. -16-18 0 0.5 1 1.5 2 2.5 V in (V)
Gain as a function of V DD 2.5 0.2 2 0.15 (V) 1.5 1 (V) 0.1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in 0.05 Gain=-1 0 0 0.05 0.1 0.15 0.2 V (V) in The gain of the inverter actually increases with a reduction of V DD. At a V DD =0.5V, which is just 100mV above V T of the transistors. So why can t we operate all digital circuits at low V DD values? Yes, you get lower power consumption. But the delay of the gate drastically increases. DC characteristics become very sensitive to variations in device parameters such at V T once V DD and intrinsic voltages become comparable. The signal swing is reduced. Although this is good for internal noise (crosstalk), this is bad for external noise sources that do not scale.
Impact of Process Variations 2.5 A CMOS inverter remains functional under a wide range of operating conditions. We showed that variations in device sizes have minor impact on switching threshold. This robust behavior, which ensures functionality of the gate over a wide range of conditions, has contributed in a big way to the popularity of the static CMOS gate. (V) 2 1.5 1 Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS 0.5 0 0 0.5 1 1.5 2 2.5 (V)
Propagation Delay
CMOS Inverter: Transient Response V DD V DD R p t phl = f(r on.c L ) = 0.69 R on C L C L C L R n = 0 (a) Low-to-high = V DD (b) High-to-low