1.[14 pts]) a) Convert the following numbers to IEEE single precision floating-point format. Give the results as eight hexadecimal digits. (Note: You should fill in the table s elements for partial credit.) (7 pts.) Value -13 1/4 91 Sign bit 1 0 Binary w/ fraction 1101.01 1011011. Exponent 3 = 0000 0011 6 = 0000 0110 Shifted Binary 1.10101 1.011 011 Excess 127 Exp 130 = 1000 0010 133 = 1000 0101 Binary IEEE 1 1000 0010 1010 100 0 1000 0101 011 011 Hex IEEE C154 0000 42B6 0000 b) Convert the following IEEE single-precision floating-point numbers from hex to decimal: (for the final value provide the sign, an integer, and the power of 2). (7 pts.) IEEE Value C2C8 0000 1234 0000 Sign bit 1 0 Excess 127 Exp 100 0010 1 = 133 001 0010 0 = 36 Exponent 6-91 Fraction 1. 100 1000 1. 011 0100 Format Value -2^6 x 1.100 1 2^-91 x 1.01101 Magnitude Binary -2^2 x 1 1001.. 2^-96 x 10 1101. Value - 2^2 x 25 = -100 2^-96 x 45 Page - 2 -
2. [8 pts.](1) Convert the following infix formula to reverse Polish notation and (2) generate IJVM code to evaluate it. (2 * 3 + 4) - (4 / 2 ) Assume that the IJVM instruction set on p. 250 has additional instructions for multiplication (IMUL) and division (IDIV) Revere Polish: 2 3 * 4 + 4 2 / - BIPUSH 2 BIPUSH 3 IMUL BIPUSH 4 IADD BIPUSH 4 BIPUSH 2 IDIV ISUB 3. [16 pts]) Describe, define, and/or respond to each of the following: a. [2 pts]) What is the Program Status Word (PSW) or Flag Register in a CPU and why is it important? The PSW is a CPU control register that provides information on the instruction by instruction execution of the CPU. The PSW includes the condition code bits that reflect the most recent status of the ALU (execution units) operation that are used for branching operations. b. [3 pts]) What are the major differences and similarities between a trap and an interrupt? A trap is a synchronous event that is executed based on a software or system condition occurring. Traps occur but are not typically a part of the desired execution of a program, they are an automatic procedure call based on a normal processing action. An interrupt is a real-time or asynchronous event that occurs based on influences external to the system. Interrupts can both be desired or unexpected based on their application in a system. Both events stop the running program and transfer control to distinct software routines executed to handle the event. After completion, the handlers often return control to the stopped program. Page - 3 -
c. [2 pts]) Define the cache policies: (1) Write-Allocate and (2) Non-Write Allocate Write-Allocate is a cache policy that that loads a cache whenever there is a write miss. In a Non- Write Allocate policy, the cache line is not loaded on a cache miss, so the data must be written to memory. d. [3 pts]) Stalling, include two unique examples when stalling would occur. When a processor must hold the instruction pipeline and wait for needed values in a pipeline to be generated. Two types of stalls are for branching and data dependencies. In branching, the next instruction may be determined by the result of a computation. To fetch and initiate the next instruction, the processor must stall and wait for the result of whether to take a branch or not. In data dependency, an instruction must wait until the data input operands that are being calculated in previous instructions are available for execution. e. [6 pts]) Cache Architecture: Assume that we have a 32-bit processor with a 32-bit byte addressable address space. The processor has a 256-kByte cache. In this system, a cache line (or block) consists of 32-bytes. 1.) How many cache lines (or cache blocks) can be stored in the cache? 2.) For a direct mapping cache, how many bits are in the TAG? 3.) For a 32-way set associative cache, how many bits are in the TAG? Cache Size: 256 kb = 2^18, Cache Line: 32 B = 2^5: (1) 2^18/2^5 = 2^13 = 8192 cache lines (2) Direct Mapping: TAG Bits = 32-5 - 13 = 14 Associative: TAG Bits = 32-5 - 00 = 27 (3) 32-way Set Assoc: TAG Bits = 32-5 - 13 + 5= 19 Page - 4 -
4. [16 pts]) Addressing Modes: (Note: all addresses and data are in hexadecimal!) Assume that a processor memory is loaded with numerical values that are all 0x20 higher than their addresses. In addition, assume each register is loaded with values that are 0x10 higher than the register number. For example: Mem Word 0x10 contains 0x30 Register 0x00 contains 0x10 Mem Word 0x11 contains 0x31 Register 0x01 contains 0x11 Mem Word 0x6E contains 0x8E Register 0x2E contains 0x3E Mem Word 0x6F contains 0x8F Register 0x2F contains 0x3F What values do the following addressing modes return as input operand? Note: 0xAB means the hexadecimal value 00AB. You should enter in the boxes to the right both a symbolic representation of the addressing mode (e.g., M[0xbb], or R(0xcc)) and the operand. Addressing Mode Numerical Value Returned (in hex notation) a) LOAD IMMEDIATE 0x0123 ### 0x0123 b) LOAD DIRECT 0x12B M[0x12B] 0x14B c) LOAD INDIRECT 0x3C M[ M[0x3C] ] 0x7C M[ 0x5C ] d) LOAD REGISTER 0x23 R(0x23) 0x33 e) LOAD REG 0x0A INDIRECT f) LOAD INDEXED 0x1A, REGISTER 0x1E g) LOAD BASE REG 0x06, INDEX REG 0x09 h) LOAD INDIRECT 0x48 M[ R(0x0A) ] 0x3A M[ 0x1A ] M[ R(0x1E) + 0x1A ] M[ 0x48 ] M[ 0x2E + 0x1A] 0x68 M[ R(0x06) + R(0x09)] M[ 0x2F ] M[ 0x16 + 0x19] 0x4F M[ M[0x48] ] 0x88 M[ 0x68 ] Page - 5 -
5. [16 pts]) There is an additional JVM instruction that could be added to the Mic-1 architecture (Fig. 4-6) of the IJVM, goto_w, branch always using a 32-bit index. From The Java TM Virtual Machine Specificatio 2nd Edition, T. Lindholm and F. Yellin : Format: goto_w branchbyte1 branchbyte2 branchbyte3 branchbyte4 The unsigned bytes branchbyte1, branchbyte2, branchbyte3, and branchbyte4 are used to construct a signed 32-bit branchoffset, where branchoffset is (branchbyte1 << 24) (branchbyte2 << 16) (branchbyte3 << 8) branchbyte4. Execution proceeds at that offset from the address of the opcode of this goto_w instruction. The target address must be that of an opcode of an instruction within the method that contains this goto_w instruction. Following the structure of Figure 4-17 (p. 262-264) in the text, determine the number of microinstructions, define the operations for each microinstruction, and provide comments on what is being done. The Main 1 instruction is shown in the desired format, use as many rows as needed for goto_w(1:n). Label Operation Comments Main1 PC=PC+1; fetch; gt (MBR) MBR holds opcode; get next byte; dispatch goto_w-1 OPC = PC - 1 Save address of opcode goto_w-2 PC = PC + 1; fetch MBR = 1st byte of offset; fetch 2nd byte goto_w-3 H = MBR << 8 Shift and save signed first byte in H H = 8-bit branch offset goto_w-4 PC = PC + 1; fetch MBR = 2st byte of offset; fetch 3rd byte goto_w-5 H = MBRU OR H << 8 H = 16-bit branch offset goto_w-6 PC = PC + 1; fetch MBR = 3rd byte of offset; fetch 4th byte goto_w-7 H = MBRU OR H << 8 H = 24-bit branch offset goto_w-8 H = MBRU OR H H = 32-bit branch offset goto_w-9 PC = OPC + H; fetch Add offset to OPC and fetch the next instruction Page - 6 -
goto_w-10 goto main1 Wait for the instruction fetch of next opcode Page - 7 -