An FPGA Implementation of a Lossless Electrocardiogram Compressor based on Prediction and Golomb-Rice Coding Moab Mariz Meira 1, José Antônio Gomes de Lima 1, Leonardo Vidal Batista 1 1 Departamento de Informática Universidade Federal da Paraíba (UFPB) Cidade Universitária 58.051-900 João Pessoa PB Brasil moab@lavid.ufpb.br, {jose,leonardo}@di.ufpb.br Abstract. This work describes an FPGA implementation of a lossless electrocardiogram compressor based on prediction and Golomb-Rice coding. The description and functionalities of the main blocks that compose the compressor architecture are presented as well as the simulation and synthesis methodology used to target it on FPGA devices. 1. Introduction The extensive use of digital electrocardiogram (ECG) produces large amounts of data. Since it is often necessary to store or transmit ECG records, efficient compression techniques are important to reduce transmission time or required storage capacity. Especially critical are long duration (24 or even 48 hours) Holter exams. The data generated in such cases can surpass 1G bytes. Holter devices must present good storage capacity, in addition to reduced dimensions and low power dissipation in order to be comfortably carried by patients [Antoniol and Tonella 1997]. These facts show the importance of using some data compression method that preserves the essential characteristics of the original signals. Several ECG compression methods have been developed in the past 30 years, and average compression ratios (CR) ranging approximately from 2:1 up to 50:1 have been reported [Cárdenas-Barreras and Lorenzo-Ginori 1999], [Koski 1997], [Jalaleddine et al. 1990]. CR is defined as the ratio between the number of bits in the original signal and the number of bits used to represent the compressed signal. Most of the reported techniques are lossy compressors, and therefore do not allow perfect reconstruction of the original signal from its compressed representation. For radiological image compression, however, lossless compression is largely preferred by health professional [Bilgin et al. 1998], due to the fear that the distortions introduced by lossy compression may induce misdiagnoses. This kind of apprehension is also present in the case of ECG compression. [Batista et al. 2003] investigated more than 30 lossless compression methods resulting from combinations of three prediction techniques, five integer-to-integer wavelet transforms, and Huffman, Golomb, LZW and LZ78 coders. A very simple compressor based on prediction and Golomb coding reached a competitive CR in comparison with the other evaluated methods [Batista et al. 2003]. Moreover, Golomb- Rice coding, which is a simplification of Golomb coding more suitable to hardware implementation, performs close to Golomb coding when used in combination with prediction techniques [Seroussi and Weinberg 1997].
This paper presents an FPGA implementation of a lossless ECG compressor based on prediction and Golomb-Rice coding. The Section 2 presents the theoretical background for this work. The Section 3 presents the architecture of the compressor and decompressor, and details of its implementation. Section 4 presents the simulation. Section 5 presents a synthesis results in terms of FPGA devices used. Finally, conclusions are presented in section 6. 2. Theoretical Background Figure 1 presents the adopted generic compression model. Initially, the original signal x o is processed by a decorrelation stage, whose objective is to reduce the statistical correlation among the x o samples. The coding stage tries to code x o using a reduced number of bits. The result of the coding is the binary sequence x c. Coders depend on a statistical model for the sequence to be coded. When samples are strongly correlated, high compression rates can be achieved if the coder is based on a contextual model that appropriately captures those correlations. However, there are practical problems associated with the use of contextual models, related to memory requirements, calculation of the estimates and transmission of the estimated conditional probabilities for the decoder [Bell et al. 1990]. If the decorrelation stage significantly reduces the statistical dependency among the samples, simple non-contextual models can lead to a good coding performance. x o Decorrelation Stage x d Coding Stage x c Figure 1. General model of compression 2.1. Prediction The decorrelation stage considered in the proposed method is based on prediction. The prediction techniques build an estimate x~ n for a given sample xn of the signal using past samples x n-1 x n-2 x n-3.... The sample x n is substituted by the prediction error, e n = x n - x~ n. The predictor used is simply: 2.2. Golomb-Rice Coding ~ P 1 : x n = x n 1 (1) Golomb-Rice coding provides a simple way to code any non-negative integer n [Seroussi and Weinberg 1997]. Given a non-negative integer parameter k, the Golomb- Rice code for n is the unary code for n shifted k bits to the right, concatenated with the k less significant bits of n. For one-sided geometric distributions (OSGD), Golomb-Rice codes generally achieve nearly optimal bit rates [Seroussi and Weinberg 1997].
A Laplacian distribution can be transformed in an approximation to an OSGD by the following mapping of values [Weinberg et al. 1996]: 2v M ( v) = 2 v -1 v 0 v < 0 (2) 2.3. k Calculation Given a sequence whose elements follow a Laplacian distribution, the optimum k to GR coding of the sequence obtained after the mapping in (2) can be estimated as k = log 2 a, where a is the average of the absolute values of the sequence before mapping [Weinberg et al. 1996]. In the proposed method, parameter k is incrementally calculated as shown in Equation 3 [Weinberg et al. 1996]. n 2 k a, (3) where n is the number of samples seen so far, and a is the sum of the absolute values of these samples. 3. Compressor Architecture Implemented in FPGA The compressor is composed by two main blocks, the PREDICTOR block and the CODER block as shown in Figure 2. A 16 bits sample is read by the PREDICTOR block, which computes the prediction error. The CODER block performs the coding stage (Golomb-Rice coding) and generates the codeword, bit by bit, on the code output. The table 1 shows the input/output signals of the compressor. Table 1. Compressor input/output signals Signal Dimension Input/Output Data/Control Function Clock 1 bit I C System clock Reset 1 bit I C System reset Sample 16 bits I D Sample input Code 1 bit O D Code output Ready 1 bit O C Ready signal sample [16 bits] clock reset PREDICTOR prediction error [16 bits] CODER code ready Figure 2. Compressor Architecture As seen in Figure 2, a 16 bits sample is read by the PREDICTOR block, calculating the prediction error between the samples according to the Equation 1. The CODER block gives the code-word, bit by bit on the code output.
input [16 bits] input [16 bits] OPTIMALK K[3 bits] mapped input [16 bits] SHIFTER shifted input [16 bits] GENERATOR code ready MAPPING Figure 3. CODER Block As seen in Figure 3, the CODER is composed by the following blocks: OPTIMALK block, MAPPING block, SHIFTER block and GENERATOR block. The OPTIMALK block calculates the optimal k value according to the Equation 3. The MAPPING block maps the read sample according to the Equation 2. The SHIFTER block perfoms the shift of the sample mapped, according to the last k value processed. This operation is part of the unary coding from Golomb-Rice method, that is, the conversion of the bit vector that represents the shifted sample in an integer value. The GENERATOR block performs a unary representation of the data provided by the SHIFTER block and, after this operation, sets the output as the k less significative bits from the mapped sample, generating the correct code-word. The GENERATOR block, synchronize the PREDICTOR block to accept a new sample data. 4. Decompressor Architecture Implemented in FPGA The decompressor is composed by two main blocks, the EPREDICTOR block and the DECODER block as shown in Figure 4. The DECODER block performs the decoding stage from an incoming input from the CODER. The EPREDICTOR block obtains the correct sample from the prediction errors calculated by the PREDICTOR block. The table 2 shows the input/output signals of the decompressor. Table 2. Decompressor input/output signals Signal Dimension Input/Output Data/Control Function Clock 1 bit I C System clock Reset 1 bit I C System reset Input 1 bit I D Code input Output 16 bits O D Sample output Ready 1 bit O C Ready signal As seen in Figure 4, an input (code-word) is read by the DECODER block, a prediction error is sent to the EPREDICTOR block, which obtains a sample as the decompressor output.
input clock reset DECODER prediction error [16 bits] ready EPREDICTOR sample [16 bits] Figure 4. Decompressor Architecture input prediction error before mapping [16 bits] mapped prediction error [16 bits] OPTIMALK GENERATOR MAPPING K[3 bits] Figure 5. DECODER Block As seen in Figure 5, the DECODER is composed by the following blocks: OPTIMALK block, MAPPING block and GENERATOR block. The OPTIMALK block calculates the optimal k according to the Equation 3. The MAPPING block maps the read sample in an inverse way as seen on the compressor. The GENERATOR block is responsible for the decoding itself of Golomb-Rice method. 5. Synthesis and Simulation Methodology The compressor and the decompressor were described in VHDL, the general architectures were divided in blocks as shown in Figure 2 and Figure 4. The blocks were divided in sub-blocks. At sub-blocks level, behavioral description were made and at blocks level, structural descriptions connecting the sub-blocks were constructed and validated using the MAX+plus II 10.0, software from Altera [Altera 1995], [Altera 1997]. Figure 6 presents a simulation of a sample coded by the compressor. First the input, after going through the prediction block (A). Since it is the first sample, there is no predecessor, thus there is no prediction there. The value of the sample is mapped (B). After, a new k is calculated as seen on simulation(c). After the mapping, the sample is shifted k bits to the right (D). Then, following the sequence, the ready signal goes up, indicating the beginning of the coding; the code is sent to the output, each bit on the rising edge of the clock (E). Finally, the coding ends and another input is read (F). The new input is processed by the predictor using the previous sample and the process goes on (G).
Figure 6. Simulation of a sample coded by the compressor Figure 7 presents a simulation of an input decoded by the decompressor. In the beginning of the decoding of the input, the bits are read one by one, on the rising edge of the clock (A). The sample is generated (B), and then it is mapped (inverse process of the compressor), the ready signal goes up indicating to the next block that the sample is ready to be processed (C). The mapped sample is processed by the predictor inverter. Since it is the first sample, there is no predecessor, so there is no prediction there. Also, the mapped sample is used to calculate a new k (D). After, a second sample is processed by the predictor inverter using the previous sample and the process goes on (E). Figure 7. Simulation of a sample decoded by the deeompressor
6. Synthesis Results The descriptions of the compressor and decompressor were synthesized using Alteras tools [Altera 1995], [Altera 1997]. Results in terms of number of logic cells, memory utilized, frequency of operation and device used are showed in Tables III and IV. Table 3 presents the results of the compressor. Table 3. Compressor Synthesis Results Device Number of LCs Percent of the device used Memory utilized Clock Frequency (MHz) EPF10K30ETC144-1 791 45 % - 21.45 EPF10K20TC144-3 791 68% - 10.23 EP1K30TC144-1 793 45% - 19.68 Table 4 presents the results of the decompressor. Table 4. Decompressor Synthesis Results Device Number of LCs Percent of the device used Memory utilized Clock Frequency (MHz) EPF10K30ETC144-1 681 39 % - 39.68 EPF10K20TC144-3 681 59% - 18.08 EP1K30TC144-1 681 39% - 37.03 The clock frequencies obtained in tables 3 e 4 shows that is possible an FPGA implementation of a lossless ECG compressor. 7. Conclusions and Future Works The design of an FPGA implementation of a lossless ECG compressor based on prediction and Golomb-Rice coding has been described, the results show that is possible to implement all the compressor/decompressor functions in a single FPGA chip compatible with a lossless electrocardiogram compressor based on prediction and Golomb-Rice coding. New FPGA families appearing on the market having potential for the implementation of more complex cores with significantly improved performance, encourage further researches to optimize this project design adding new functionalities for ECG equipments.
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