Microelectroics Processig Techology 6.152J / 3.155J Fall 2001 Metal Semicoductor (MOS) apacitor The MOS capacitor structure is show i Figure 1. The metal plate is a heavily doped p + - poly-silico layer which behaves as a metal. The isulatig layer is silico diide ad the other plate of the capacitor is the semicoductor layer which i our case is -type silico whose resistivity is 1-10 Ω-cm correspodig to a dopig of 10 15 cm -3. The capacitace of the MOS structure depeds o the voltage (bias) o the gate. For the purposes of this discussio, we shall refer to the cotact to the semicoductor as the body () while the poly-silico is called the gate (G). Typically a voltage is applied to the gate while the body is grouded ad the applied voltage is V G but more accurately V G. The two (V G & V G ) will be used iterchageably i this documet. Gate p + Poly- - ody Figure 1: The MOS apacitor structure. The substrate (body) is grouded ad a voltage V G is applied to the poly-silico gate. The capacitace depeds o the voltage that is applied to the gate (with respect to the body). The depedece is show i Figure 2 ad there are roughly three regimes of operatio separated by two voltages. The regimes are described by what is happeig to the semicoductor surface. These are (1) Accumulatio i which carriers of the same type as the body accumulates at the surface (2) epletio i which the surface is devoid of ay carriers leavig oly a space charge or depletio layer, ad (3) Iversio i which carriers of the opposite type from the body aggregate at the surface to ivert the coductivity type. The two voltages that demarcate the three regimes are (a) Flatbad Voltage (V F ) which separates the accumulatio regime from the depletio regimes ad (b) the Threshold Voltage (V T ) which demarcates the depletio regime from the iversio regime. Let us ow look at our particular device MOS capacitor with a -type body / substrate. MOSap01.doc MOS apacitor Page 1 of 9
QS ma MOS ma HF mi MOS (VT)mi V T V F V G Iversio epletio Accumulatio Figure 2: apacitace per uit area vs. Gate Voltage (V) diagram of a MOS apacitor. The flatbad voltage (V F ) separates the Accumulatio regio from the epletio regime. The threshold voltage (V T ) separates the depletio regime from the iversio regime. HF is high frequecy capacitace while QS is quasi-static or low frequecy capacitace. Surface Accumulatio (V G > V F ) A applied positive gate voltage larger tha the flatbad voltage (which will be defied shortly) (V G > V F ) iduces positive charge o the metal gate ad egative charge i the semicoductor. The oly egative charges available are electros ad they accumulate at the surface. The electro cocetratio at the surface is above the bulk value, thus leadig to a coditio that is called surface accumulatio. The charge distributio ad equivalet circuit is show i Figure 3. The flatbad voltage (V F ) is the voltage at which there is o charge o the plates of the capacitor ad hece there is o electric field across the ide. It s umerical value depeds o the dopig of the semicoductor ad o ay residual iterface charge that may eist at the iterface betwee the semicoductor ad the isulator. Whe the surface of the semicoductor is accumulated, a plot of the charge per uit area (Q N ) at the semicoductor / ide iterface versus the applied voltage (V G ) is liear ad the slope is the ide capacitace per uit area.,., which is give by MOS, accumulatio ma t where is the permittivity of the ide ad it is 3.9 o. o is the permittivity of free space or air. o 8.85410-14 Fcm -1. The uit for is Fcm -2. Figure 4 is a plot of the charge per uit area (Q N ) as a fuctio of the applied voltage (V G ). MOSap01.doc MOS apacitor Page 2 of 9
charge desity Poly- ρ G + + + + + - - - - - + + + + + -t lico 0 - - - - - Figure 3: harge distributio i a MOS apacitor biased ito accumulatio. The electro distributio at the /O 2 iterface could be apprimated as a δ-distributio. Figure 4: Accumulatio charge desity as a fuctio of the applied voltage. The slope of the lie is the ide capacitace per uit area,. Surface epletio (V T < V G < V F ) If the applied gate voltage is brought below the flat bad voltage (remember the flat bad voltage is the gate voltage at which there is o charge i the MOS capacitor), a egative charge is iduced at the iterface betwee the poly-silico gate ad the ide. This leads to a positive charge beig iduced at the other iterface i.e. the ide / semicoductor iterface. This could oly be accomplished by pushig all the mobile egative carriers (electros) away ad eposig the fied positive charge from the doors. Hece the surface of the semicoductor is depleted of mobile carriers leavig behid a positive space charge. Figure 5 shows the charge distributio uder these circumstaces. The space charge layer resultig behaves also like a capacitor havig a capacitace per uit area ( ), which depeds o V G ad is give by MOSap01.doc MOS apacitor Page 3 of 9
( VG ) ( V ) where is the permittivity of the silico ad it is 11.7 o. o is the permittivity of free space or air. o 8.85410-14 Fcm -2. d is the depleted silico layer thickess. The uit of is Fcm -2. From Figure 5, we observe that the ide capacitace per uit area ( ) ad depleted silico capacitace per uit area ( ) are coected i series. Thus the capacitace of the MOS structure whe it is i the surface depletio regime is give by 1 1 1 + depletio MOS, depletio d depletio G The uit for depletio is Fcm -2. The silico depletio layer thickess icreases as the gate voltage is decreased because more electros are pushed away eposig more fied positive ioized dopats leadig to thicker space charge layer. The capacitace of the depleted silico decreases ad hece the MOS capacitace decreases as the gate voltage is decreased. + charge desity Mobile electros p - - - - - + -poly + + + + + Ioized oors - G Poly- Mobile Electros - - - - - ρ Ioized oors + + + + + -t 0 d lico Figure 5: harge distributio i a MOS apacitor biased ito depletio ad the equivalet circuit diagram. d is the depleted silico layer thickess. MOSap01.doc MOS apacitor Page 4 of 9
Surface Iversio (V G < V T ) If the applied gate voltage is lowered below the threshold voltage (V T ), the semicoductor surface iverts its coductio type from -type to p-type i our particular situatio. It is atural to ask why such a thig would occur? efore aswer the questio let us defie the threshold voltage (V T ) as the gate voltage at which the coductivity type of the surface layer chages from -type to p-type because more holes have bee attracted to the surface that the umber of electros that eisted at the surface at flatbad. It demarcates the depletio regio from the iversio regio. We shall ow proceed to aswer the questio about why the surface iverts. Startig from flatbad, as the gate voltage is lowered egative mobile carriers (electros) are pushed away from the /O 2 iterface, a positive space charge is eposed. We apprimate this as a depletio layer i which we make the assumptio that the layer is devoid of all mobile carriers. However, this is oly a apprimatio. What happes i reality is that the desity of electros decreases epoetially from the surface goig ito the bulk. A importat fact pertiet to this discussio is that we assumed that system is i quasi-equilibrium, hece the law 2 of mass actio p o o i is still valid. Thus at the surface, the umber of electros decreases as the applied voltage decreases. orrespodigly, the umber of holes at the surface icreases as the applied gate voltage decreases. This is depicted i Figure 6. At a particular voltage called the threshold voltage (V T ) the cocetratio of holes at the surface eceeds the cocetratio of electros i the bulk. The coductivity type of the silico surface is iverted. Figure 7 shows the charge distributio of the MOS capacitor i iversio. There is a mobile charge delta-distributio at the silico / silico diide iterface. Additioal icreases i the applied gate voltage oly leads to a liear icrease i the charge per uit area of the iversio layer. Figure 8 shows the depedece of the charge desity o the applied gate voltage. The iversio layer charge desity is give by Q P 2 [ V V ] ( ) cm G T The above epressio for the hole desity i the iversio layer will be used whe cosiderig the p-mosfet. A importat fact we eed to state is that oce the iversio layer forms, the depletio layer thickess reaches a maimum. The total voltage drop across the semicoductor is pied at a maimum value. Icreases i the gate voltage applied to the structure is dropped mostly across the ide layer as reflected by the epressio for iversio layer charge. Thus whe the gate voltage is equal to the threshold voltage, the depleted layer capacitace per uit area reaches a miimum mi ad likewise the MOS capacitace. This capacitace is mi ad it is give by where MOS mi ( V ) T d ma mi depletio,mi + mi mi MOSap01.doc MOS apacitor Page 5 of 9
Figure 6: Semilog plots of the carrier cocetratio distributio for the MOS capacitor i (a) accumulatio, (b) flatbad, (c) depletio ad (d) iversio. MOSap01.doc MOS apacitor Page 6 of 9
Mobile electros G p + -poly - - - - - Poly- + + + + + Holes + + + + + Ioized oors - Poly- Mobile Electros - - - - - charge desity ρ + + + + + + + -t 0 dma + + + Holes at iterface lico Ioized oors mi Figure 7: harge distributio i a MOS apacitor biased ito iversio. The hole distributio at the /O2 iterface could be apprimated as a δ-distributio. Figure 8: Iversio layer hole charge desity as a fuctio of the applied voltage (low frequecy & quasi-static situatio). The slope of the lie is the ide capacitace per uit area,. Where do the holes that form the iversio layer come from? I a MOS capacitor i depletio or iversio, the holes ad electros are geerated i the depleted silico surface regio. The holes are attracted to the /O 2 iterface while the electros are pushed ito the substrate. However the holes could also come from a p-doped regio that is i close primity to the MOS capacitor such as the source/drai regio of a p-mosfet. What are the epressios for d ad dma? I will ot try to derive the equatios that give you d ad dma because they are rather ivolved, but I will have give you the epressios. If you will like to derive it, I will refer you to 6.012 Tet. Microelectroics: A Itegrated Approach, Howe ad Sodii. MOSap01.doc MOS apacitor Page 7 of 9
( V ) d where p + G ( ) m 0.55 V kt N l q i 2 2 1+ p + ( + V ) qn G 1 d ( V ) T d ma 2 2 qn The et questio to be asked is that why are there two values of capacitace at ay voltage i the iversio regime? The capacitace of the structure is usually measured by imposig a bias voltage which i our case will be V G superposed o the bias is a small sigal which is a alteratig curret (ac). This could be a high frequecy ac sigal (f1 MHz) or low frequecy sigal (f<1 khz). The frequecy of the sigal affects the capacitace versus voltage (V) curve for a MOS capacitor. The capacitace depeds o the measuremet frequecy ad what other structures are coected to the basic MOS capacitor. At very low frequecies (sometimes referred to as quasi-static coditios), the geeratio rate of holes (ad electros) i the depleted silico surface layer is fast eough ad hece holes are swept to the /O2 iterface where the thi layer holes forms a sheet of charge. Thus the iversio layer capacitace per uit area uder quasi-static coditios is give MOS, iversio, QS ma t At high frequecies, the geeratio rate is ot fast eough to allow the formatio of a hole charge desity at the /O 2 iterface. I this case the silico surface depletio layer thickess is still at it s maimum value dma ad the correspodig iversio layer capacitace per uit area at high frequecy is mi ad it is give by MOS, iversio, HF mi depletio,mi + mi mi The iversio layer capacitace of a p-mosfet eve at high frequecies has the same value as the quasi-static MOS capacitor ( ma) because there is a ready supply of holes comig from the p-type source/drai regios that are i close primity. MOSap01.doc MOS apacitor Page 8 of 9
What are the flatbad ad threshold voltages? Flatbad Voltage I theory, the flatbad voltage should be V F p + 0.55 V kt N l q ( ) ( + ) i m I real devices, there is a positive charge located at the /O 2 iterface ad it modifies the equatio thus V F Q m I t ( ) w I 2 here Q is the /O iterface charge desity (# cm -2 ) p Threshold Voltage V V T F t 2 2 qn 2 ( ) m p+ is the gate (metal) potetial is the potetial of - substrate i is the itrisic carrier cocetratio of t is ide thickess, the ide & dielectric costats N is the substrate dopig Q I is the ide charge desity at the iterface MOSap01.doc MOS apacitor Page 9 of 9