HCF40181B 4-BIT ARITHMETIC LOGIC UNIT



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4-BIT ARITHMETIC LOGIC UNIT FULL LOOK-AHEAD CARRY FOR SPEED OPERATIONS ON LONG WORDS GENERATES 16 LOGIC FUNCTIONS OF TWO BOOLEAN VARIABLES GENERATES 16 ARITHMETIC FUNCTIONS OF TWO 4-BIT BINARY WORDS A = B COMPARATOR OUTPUT AVAILABLE RIPPLE-CARRY INPUT AND OUTPUT AVAILABLE TYPICAL ADDITION TIME 200ns AT V DD = 10V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I I = 100nA (MAX) AT V DD = 18V T A = 25 C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF40181B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in SOP packages. HCF40181B is a low-power 4-bit parallel arithmetic logic unit (ALU) capable of providing 16 binary arithmetic operations on two 4-bit words ORDER CODES SOP PACKAGE TUBE T & R SOP HCF40181BM1 HCF40181M013TR and 16 logical functions of two Boolean variables. The mode control input M selects logical (M = High) or arithmetic (M = Low) operations. The four select inputs (S0, S1, S2, and S3) select the desired logical or arithmetic functions, which include AND, OR, NAND, NOR, and exclusive-or and NOR in the logical mode, and addition, subtraction, decrement, left-shift and straight transfer in the arithmetic mode, according to the truth table. HCF40181B operations may be interpreted with either active-low or active-high data at the A and B word inputs and the function outputs F, by using the appropriate truth table. HCF40181B contains logic for full look-ahead carry operations for fast carry generations using the carry-generate and carry propagate outputs G PIN CONNECTION September 2002 1/10

and P for the four bits of HCF40181B. Use of the HCF40182B look-ahead carry generator in conjunction with multiple HCF40181Bs permits high-speed arithmetic operations on long words. A ripple carry output C n+4 is available for use in systems where speed is not of primary importance. Also included in HCF40181B is a comparator output A = B, which assumes a high level whenever the two four-bit input words A and B are equal and the device is in subtract mode. In addition, relative magnitude information may be derived from the carry-in input C n and ripple carry-out output C n+4 by placing the unit in the subtract mode and externally decoding using the information in table II. HCF40181B is similar to industry types MC14581 and 74181. INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 22, 20, 18 B0 to B3 Word B 2, 23, 21, 19 A0 to A3 Word A 6, 5, 4, 3 S0 to S3 Function Select Inputs 9, 10, 11, 13 F0 to F3 Output Function 7 Cn Carry Input 8 M Mode Control 14 A = B Compare Output 15 P Look Ahead Carry Outputs 16 Cn+4 Ripple Carry Output 17 G Look Ahead Carry Outputs 12 V SS Negative Supply Voltage 24 V DD Positive Supply Voltage FUNCTIONAL DIAGRAM ACTIVE-LOW DATA ACTIVE-HIGH DATA 2/10

LOGIC DIAGRAM (ACTIVE-LOW DATA) 3/10

TRUTH TABLE 1 FUNCTION SELECT INPUTS/OUTPUTS ACTIVE LOW INPUTS/OUTPUTS ACTIVE HIGH S3 S1 S2 S0 Logic Function Arithmetic* Function Logic Function Arithmetic* Function (M = H) (M = L, Cn = L) (M = H) (M = L, Cn = H) L L L L A A minus 1 A A L L L H AB AB minus 1 A + B A + B L L H L A + B AB minus 1 AB A + B L L H H Logic 1 minus 1 Logic 0 minus 1 L H L L A + B A plus (A + B) AB A plus AB L H L H B AB plus (A + B) B (A + B) plus AB L H H L A B A minus B minus 1 A B A minus B minus 1 L H H H A + B A + B AB AB minus 1 H L L L AB A plus (A + B) A + B A plus AB H L L H A B A plus B A B A plus B H L H L B AB plus (A + B) B (A + B) plus AB H L H H A + B A + B AB AB minus 1 H H L L Logic 0 A plus A Logic 1 A plus A H H L H AB AB plus A A + B (A + B) plus A H H H L AB AB plus A A + B (A + B) plus A H H H H A A A A minus 1 : Expressed as two s complement. For arithmetic function with Cn in the opposite state, the resulting function is as show plus 1. TRUTH TABLE 2: MAGNITUDE COMPARISON ACTIVE-HIGH DATA ACTIVE-LOW DATA INPUT C n OUTPUT C n + 4 MAGNITUDE INPUT C n OUTPUT C n + 4 MAGNITUDE H H A B L L A B L H A < B H L A < B H L A > B L H A > B L L A B H H A B TRUTH TABLE 3: AC TEST SETUP REFERENCE (ACTIVE-LOW DATA) TEST DELAY TIMES AC PATHS DC DATA INPUTS MODE* INPUTS OUTPUTS TO V SS TO V DD SUM IN to SUM OUT B0 Any F ADD Mode: S0, S3 = V DD ; S1, S2 = V SS. SUBTRACT Mode: S0, S3 = V SS ; S1, S2 = V DD. B1, B2, B3, M, C n All A s ADD SUM IN to P A0 P A1, A2, A3, M, C n All B s ADD SUM IN to G B0 G All A s, M, C n B1, B2, B3 ADD SUM IN to C n + 4 B0 C n + 4 All A s, M, C n B1, B2, B3 ADD C n to SUM OUT C n Any F All A s, M All B s ADD C n to C n +4 C n C n + 4 All A s, M All B s ADD SUM IN to A = B B0 A = B All A s, B1, B2, B3, M C n SUM IN to SUM OUT (logic mode) All B,s Any F All A s, C n M SUBTRACT EXCLUSIVE OR 4/10

ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V DD Supply Voltage -0.5 to +22 V V I DC Input Voltage -0.5 to V DD + 0.5 V I I DC Input Current ± 10 ma P D Power Dissipation per Package 200 mw Power Dissipation per Output Transistor 100 mw T op Operating Temperature -55 to +125 C T stg Storage Temperature -65 to +150 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to V SS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit V DD Supply Voltage 3 to 20 V V I Input Voltage 0 to V DD V T op Operating Temperature -55 to 125 C 5/10

DC SPECIFICATIONS Test Condition Value Symbol Parameter V I (V) V O (V) I O (µa) V DD (V) T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max. Unit I L Quiescent Current 0/5 5 0.04 5 150 150 0/10 10 0.04 10 300 300 0/15 15 0.04 20 600 600 0/20 20 0.08 100 3000 3000 V OH High Level Output 0/5 <1 5 4.95 4.95 4.95 Voltage 0/10 <1 10 9.95 9.95 9.95 0/15 <1 15 14.95 14.95 14.95 V OL V IH V IL I OH I OL Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current 5/0 <1 5 0.05 0.05 0.05 10/0 <1 10 0.05 0.05 0.05 15/0 <1 15 0.05 0.05 0.05 0.5/4.5 <1 5 3.5 3.5 3.5 1/9 <1 10 7 7 7 1.5/13.5 <1 15 11 11 11 4.5/0.5 <1 5 1.5 1.5 1.5 9/1 <1 10 3 3 3 13.5/1.5 <1 15 4 4 4 0/5 2.5 <1 5-1.36-3.2-1.1-1.1 0/5 4.6 <1 5-0.44-1 -0.36-0.36 0/10 9.5 <1 10-1.1-2.6-0.9-0.9 0/15 13.5 <1 15-3.0-6.8-2.4-2.4 0/5 0.4 <1 5 0.44 1 0.36 0.36 0/10 0.5 <1 10 1.1 2.6 0.9 0.9 0/15 1.5 <1 15 3.0 6.8 2.4 2.4 I I Input Leakage Current 0/18 Any Input 18 ±10-5 ±0.1 ±1 ±1 µa I OZ 3-State Output Leakage Current 0/18 Any Input 18 ±10-4 ±0.4 ±12 ±12 µa C I Input Capacitance Any Input 5 7.5 pf The Noise Margin for both "1" and "0" level is: 1V min. with V DD =5V, 2V min. with V DD =10V, 2.5V min. with V DD =15V µa V V V V ma ma 6/10

DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25 C, C L = 50pF, R L = 200KΩ, t r = t f = 20 ns) Symbol Parameter Test Condition Value (*) Unit V DD (V) Min. Typ. Max. t PHL t PLH Propagation Delay Time A or B to F (logic mode) A or B to G or P 5 400 800 10 160 320 15 120 240 A or B to F, C n+4, or A = B 5 10 500 200 1000 400 15 140 280 C n to F 5 320 640 10 135 270 15 100 200 C n to C n+4 5 200 400 10 100 200 15 70 140 t THL t TLH Transition Time 5 100 200 10 50 100 15 40 80 ns ns ns ns ns (*) Typical temperature coefficient for all V DD value is 0.3 %/ C (1) : If more than one unit is cascaded. tr should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TEST CIRCUIT C L = 50pF or equivalent (includes jig and probe capacitance) R L = 200KΩ R T = Z OUT of pulse generator (typically 50Ω) 7/10

WAVEFORM : PROPAGATION DELAY TIMES (f=1mhz; 50% duty cycle) 8/10

SO-24 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45 (typ.) D 15.20 15.60 0.598 0.614 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 13.97 0.550 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 S 8 (max.) L C c1 a2 A b e3 e s E a1 b1 D 24 13 F 1 1 2 PO13T 9/10

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 10/10