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" PCB Layout for Switching Regulators " 2
Introduction Linear series pass regulator I L V IN V OUT GAIN REF R L Series pass device drops the necessary voltage to maintain V OUT at it s programmed value Power Loss = (V IN V OUT ) * I L e.g. 12V in, 3.3V/5A out, Power Loss = 43.5W 3
Switching regulator Introduction I L V IN FILTER V OUT PWM GAIN REF Power (V IN V OUT ) * I L When switch is closed V = 0, I = I L When switch open V = V IN, I = 0 Theoretically zero power loss with ideal switch e.g. η = 90%, Power loss = 1.83W versus 43.5W 4
Switching regulator Introduction I L V IN FILTER V OUT PWM GAIN REF But we now have high slewing currents and voltages 5
DC Resistance Copper is not a perfect conductor Efficiency Regulation Thermals Material μω-cm μω-in Silver 1.5 0.59 Copper 1.70 0.67 Silver (Plated) 1.8 0.71 Current Flow l A R = ρl A ρ = resistivity Gold 2.2 0.87 Copper (Plated) 6.0 2.36 Palladium 11 4.3 Tin (Plated) 11 4.33 Tin -Lead 15 5.91 Lead 22.0 8.66 6
DC Resistance Copper resistivity = 0.67μΩ in. at 25 C. At 279 C it doubles Count squares to estimate trace resistance Current Flow l R = ρ ( l) t ( l) t l R = ρ t 1.0mΩ R of = R of = (½ oz Cu) 0.2mΩ (2oz Cu ) 7
Estimate resistance of input trace PSU Spec: 3.3V to 1.8V/20A η = 87% I IN = 12.54A Count Squares Cu Weight Oz. Thickness mm (mils) mω/square 25 o C mω/square 100 o C 1/2 0.02 (0.7) 1.0 1.3 1 0.04 (1.4) 0.5 0.65 2 0.07 (2.8) 0.2 0.26 8
Count Squares 6.4 squares 2.8 squares 3.6 squares Using ½ oz Cu R= 6.4mΩ at 25 C P DISS = 0.98W = 18% of losses Using 2 oz Cu R = 1.28mΩ at 25 C P DISS = 0.2W = 3.7% of losses 9
Vias Have Resistance Too 1A to 3A per via 20mil via with 1 mil plating Current Flow A R = ρl A l 1.6 mm (63 mils) R ρl = π ( t d t 2 ) d 0.025 mm (1.0 mil) t 0.5 mm (20 mils) 6 2.36 10 0.063 R = = 2. 4 mω 2 π (0.001 0.02 0.001 ) 10
Vias Have Resistance Too 171 at 2.4mΩ/via R = 14μΩ Second Cu layer => total trace R = 0.64mΩ P DISS = 0.1W 11
AC Parasitics. Inductance Self inductance of PCB trace Changes in trace width has a small impact on self inductance. l w A 10x increase in width only halves the inductance t Current Flow L L = = W mm (in) 2 ln 5 ln l t + w l t + w + + t mm (in) 0.5 0.5 nh nh for cm for inches Inductance nh/cm (nh/in) 0.25 (0.01) 0.07 (0.0028) 9.7 (24.4) 2.5 (0.1) 0.07 (0.0028) 5.6 (13.9) 12.5 (0.5) 0.07 (0.0028) 2.4 (6) 12
AC Parasitics. Inductance Traces over ground planes reduces self inductance A ground plane can reduce inductance by a factor of 4 h w h mm (in) w mm (in) Current Flow L = L = Inductance nh/cm (nh/in) 1.6 (0.063) 2.5 (0.1) 1.3 (3.2) 2hl w 5hl w nh/cm nh/in Inductance No ground plane nh/cm (nh/in) 5.6 (13.9) 2.5 (0.1) 2.5 (0.1) 2.0 (5.0) 5.6 (13.9) 13
T T Current Loops and Inductance Keep loop area with high di/dt s small 2.59 2.28 Voltage (V) 0.00 Voltage (V) 0.00-2.59-2.28 2.00u 3.00u 4.00u 5.00u Time (s) 2.00u 3.00u 4.00u 5.00u Time (s) x Y y Y X Loop area A = X * Y BAD X Loop area A = (X*Y) - (x*y) GOOD 14
AC Parasitics. Capacitance Two Cu plates with PCB material dielectric Two 10 mil traces on a multi layer PCB, 10 mil between layers A = 0.25 mm x 0.25 mm Note: 10 mil = 0.25 mm. C C C = = ε R ε O t A Permittivity of FR4 4.7 ε o = 8.84 x 10-12 = ( 12 41.9 10 ) t A ( 12 ) ( 3 41.9 10 0.25 10 ) 0.25 10 3 2 C = 0. 01 pf 15
AC Parasitics. Capacitance Five 1.3 x 0.7 mm in summing junction can increase parasitic capacitance to 1pF. 1V/nsec = 1mA through 1pF. Critical components 1 2 TPS40020 ILIM/SYNC BOOT1 VDD HDRV 16 15 VIN 12V 3 OSNS SW 14 4 FB BOOT2 13 5 6 COMP SS/SD PVDD LDRV 12 7 11 7 VOUT 12nsec 7 RT PGND 10 7 8 SGND PowerPAD PWRGD 79 1mA C PARASITIC 16
Single Point Grounding Series Parallel 1 2 3 1 2 3 Simple wiring Common impedance causes different potentials High impedance at high frequency (>10 khz) Complicated wiring Low differential potentials at low frequencies High impedance at high frequency (>10 khz) 17
Multi Point Grounding 1 2 3 Ground Plane Ground plane provides low impedance between circuits to minimize potential differences Also, reduces inductance of circuit traces Goal is to contain high frequency currents in individual circuits and keep out of ground plane 18
PSU Layout Guide 1. Place power components only with regard to thermal, mech., elect. and safety reqs. 2. Place input filter symmetrical layout, immediately adjacent to input and away from FET, trafo, inductor, etc. 3. Place FET drivers star point at FET source pin 4. Place control and associated parts star point at IC GND pin star point at IC GND pin sense points = output terminals 19
Place Power Components DC Q1 B L DC A C AC C1 Q2 C2 AC D F E Typical circulating current when Q1 is ON 20
Place Power Components Q1 B L DC A C AC C1 Q2 C2 D F E Typical circulating current when Q2 is ON 21
Place Power Components DC Q1 B L DC A C AC CIN Q2 COUT AC F High di/dt in these current paths E D Circulating currents combine in some traces 22
Place Power Components Draw schematic to reflect good layout 23
Place Power Components DC High side FET ON Use short and direct paths Minimum loop area Separate dc & ac paths Separate input & output paths DC Q1 ON Current flow 24
Place Power Components Low side FET ON Use short and direct paths Minimum loop area Separate dc & ac paths Separate input & output paths DC Q2 ON Current flow 25
Place Filter Components Input Filter Filter components placed between input and power train. Place close to connector Keep AC current in small loop Output Filter 26
Measuring noise Scope Probes Use a small ground connector 27
Place Filter Components Input A Input B Input location A or B? Input ripple at C10 versus C12 28
Place Filter Components Input A Input B Input A 40mVpp ripple 16mVp spike Input B 70mVpp ripple 110mVp spike 20mV/div 50mV/div 29
Place Filter Components Output location A or B? Input ripple at C10 versus C12 Output B Output A 30
Place Filter Components Output A 12mVpp ripple 7mVp spike Output B 20mVpp ripple 17mVp spike Output B Output A 31
Place FET Drivers Q1 L CIN C1 C3 Q2 COUT FET gate charging and discharging. di/dt greater than 100A/μsec (1.5A/15nsec) dv/dt greater than 200V/μsec (3V/15nsec) 32
Place FET Drivers Place with: Short and direct paths Minimum loop area Cross other tracks at 90 reduces capacitive coupling Trace from IC to Q1 gate is 0.852, width is 0.03 on 2oz copper: L PARA = 6.23nH V IND = 0.623V Poor Driver Layout 33
Place FET Drivers Place with: Short and direct paths Minimum loop area Cross other tracks at 90 reduces capacitive coupling Trace from IC to Q1 gate is 0.852, width is 0.03 on 2oz copper: L PARA = 6.23nH V IND = 0.623V Better Driver Layout 34
Place Control and Associated Parts Connect resistors close to FB pin Remote sense at load, voltage divider at IC 35
Layout A 36
Layout A Input Ripple 40mVpp ripple 34mVp spike Output Ripple 12mVpp ripple 20mVp spike 37
Layout B 38
Layout B Input Ripple 40mVpp ripple 16mVp spike Output Ripple 12mVpp ripple 7mVp spike 39
Layout A Input Ripple 40mVpp ripple 34mVp spike Output Ripple 12mVpp ripple 20mVp spike 40
PSU Layout Guide Join components: Use short and direct paths (minimize inductance) Minimum loop area single sided PCB 1. Go and return paths immediately adjacent double sided PCB: 1. Ground planes top & bottom, no breaks, no floating areas 2. One ground plane, no breaks, no floating areas 3. Go and return paths over each other 4. Go and return paths immediately adjacent, track direction: E-W on one side, N-S on other Separate dc & ac paths Separate input & output paths Four terminal connections (Kelvin connections) Star common connections (no daisy chains) 41
Additional Resources www.ti.com www.avnet.com 42
Appendix Discussion of layout rules and differences in lab. 43
Place Control and Associated Parts Many control IC s recognize noisy/quiet circuit areas and pin out accordingly Some even provide a separate pin for power and analog ground Good practice plans layout around pin out, uses a ground plane and keeps high current out of it Signal circuits Power circuits 44
Layout A 4 layers Input GND connected directly to output GND High side FET driver return F/B node 45
Layout B 2 layer board Improved high side gate return Improved input GND and output GND decoupling Smaller F/B trace 46
PSU Layout Guide Join components: Use short and direct paths (minimize inductance) Minimum loop area single sided PCB 1. Go and return paths immediately adjacent double sided PCB: 1. Ground planes top & bottom, no breaks, no floating areas 2. One ground plane, no breaks, no floating areas 3. Go and return paths over each other 4. Go and return paths immediately adjacent, track direction: E-W on one side, N-S on other Separate dc & ac paths Separate input & output paths Four terminal connections (Kelvin connections) Star common connections (no daisy chains) 47