November 200 HI-010, HI-110 CMOS High oltage Display Driver GENERAL DESCRIPTION PIN CONFIGURATION (Top iew) The HI-010 & HI-110 high voltage display drivers are constructed of MOS P Channel and N Channel enhancement mode devices in a single monolithic structure. They are designed to drive high voltage liquid crystal displays by converting low level input signals (TTL on the HI-010 and CMOS on the HI-110) to high voltage drive signals. Both devices can drive up to 3 segments and require minimal display-to-data source interfacing. Serial data is loaded and held in internal latches until new display data is received. The HI-010 & HI-110 are available in a variety of ceramic and plastic packaging including leaded and leadless chip carriers; and J-lead and gull-wing quad flat packs. OPT DD S3 S3 S1 S2 S3 S4 S5 S6 2 3 4 5 6 10 11 12 SS S36 S35 S34 S33 S32 S31 S30 S2 S2 S2 51 50 4 4 4 46 45 44 43 42 41 40 HI-010PQI HI-110PQI HI-010PQT & HI-110PQT 52 - PIN PLASTIC QFP 14 15 16 1 1 1 20 21 22 23 24 25 26 S S S S10 S11 S12 S13 S14 EE S15 S16 S1 S1 3 3 3 36 35 34 33 32 31 30 2 2 S26 S25 S24 S23 S22 S21 S20 3 N/C N/C N/C S1 FEATURES 5 volt input translated to 30 volts or less Pin-out adaptable to drive 30, 32 or 3 LCD segments RC oscillator or high voltage () clock input TTL compatible inputs (HI-010 only) CMOS compatible inputs (HI-110 only) Low power consumption Industrial (-40 C to +5 C) & Military (-55 C to +125 C) temperature ranges Pin for pin compatible with the Micrel MIC010/011 series and the AMI S4520 series drivers Cascadable Military level processing available APPLICATIONS Dichroic Liquid Crystal Displays Standard Liquid Crystal Displays acuum Fluorescent Displays MEMS Drivers (See page 5 for additional package pin configurations) FUNCTIONAL BLOCK DIAGRAM OPT Oscillator Divider oltage Translator High oltage Buffer DATA IN 3 Stage Shift Register K LE 3 Bit Latch oltage Translators High oltage Drivers 3 32 30 (DS010, Rev. G) www.holtic.com 11/0
PIN DESCRIPTIONS SYMBOL FUNCTION DESCRIPTION SS POWER 0 olts Logic input Chip select Logic input Clocks shift register on negative edge and pins on positive edge Logic input Segment outputs equal shift register data if Load is high Logic input Shift register data input LCD0 Analog input Display clock input and is always bonded out. Can swing from EE to DD LCD0OPT OUTPUT Analog output Bonded out only if an RC oscillator is required DD POWER 5 olts EE POWER 0 olts to -30 olts OUTPUT Logic output Selected pinout can provide shift register taps at positions 30, 32, 34, or 3 OUTPUT Display drive output Low resistance drive for the backplane and swings from DD to EE Segments OUTPUT Display drive output High resistance drive for each segment and swings from DD to EE FUNCTIONAL DESCRIPTION Whenever a Logic "0" is applied to the Chip Select ( ) input, one bit of data is clocked into the shift register from the serial data input () with each negative transition of the Clock ( ) input. is internally tied to SS on some versions. A Logic "1" present at the Load () input will cause a parallel transfer of data from the shift register to the data latch. If the Load () input is held high while data is clocked into the shift register, the latch will be transparent. All four logic inputs are TTL compatible on the HI-010 and CMOS compatible on the HI-110. on the rising edge of the Clock ( ). Clock ( ), Load () and Chip Select ( ) should be tied in common with each other, respectively, between all cascaded display drivers. INTERNAL OSCILLATOR CIRCUIT To display segments, a Logic "1" is stored in the appropriate shift register bit position, and the segment output is out-ofphase with the backplane. The backplane output functions in 1 of 2 modes; externally driven or self-oscillating. When the input is externally driven with the OPT input open circuit (Figure 2), the backplane output will be in-phase with. Utilizing the self-oscillating mode, inputs and OPT are tied together and connected to an RC circuit (Figure 3). A 150K resistor with a 40pF capacitor generates an approximate backplane frequency of 100Hz. The /OPT oscillator frequency is divided by 256 to determine the backplane output frequency. The resistor value (R) must be at least 30K for proper self-oscillator operation. For displays having a number of segments greater than 3, two or more of the display drivers may be cascaded together by connecting the serial data output () from the first driver, to the serial data input () of the following driver, etc. (See Figures 2 & 3). Data out () will change state OPT Figure 1 C R 256 Q TO BACKPLANE TRANSLATOR AND DRIER 2
CASCAG - EXT. OSCILLATOR HI-010J-5 HI-010J-5 HI-010J-5 CASCAG - RC OSCILLATOR 150K HI-110PQI 40pf OPT HI-110PQI OPT HI-110PQI OPT 1-32 33-64 BACK PLANE 65-6 1-3 3-6 BACK PLANE -114 Figure 2 Figure 3 ABSOLUTE MAXIMUM RATINGS oltages referenced to SS = 0 Supply oltage DD... 0 to Power Dissipation...300 mw EE... DD-35 to 0 Operating Temperature Range - Industrial...-40 to +5 C oltage at any input, except LCD Ø..-0.3 to DD+0.3 Operating Temperature Range - Hi-Temp/Mil..-55 to +125 C oltage at input...dd-35 to DD+0.3 DC Current any input pin...10 ma Storage Temperature Range...-65 to +150 C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTI DD = 5, EE = -25, SS = 0, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Operating oltage DD 3.0.0 Supply Current (Static, No Load) @+5 C, f =0Hz 200 µa IDD @ +125 C, f =0Hz 300 µa IEE @ +125 C, f =100Hz 150 µa Input Low oltage, HI-010 (except ) ILTTL 0 0. Input High oltage, HI-010 (except ) IHTTL 2 DD Input Low oltage, HI-110 (except LCD Ø) ILCMOS 0 0.3 DD Input High oltage, HI-110 (except ) IHCMOS 0. DD DD Input Low oltage () ILX EE 3 Input High oltage () IHX 3.5 DD Input Current IIN IN =0to5 1 µa Input Capacitance (not tested) CI 5 pf Segment Output Impedance RSEG IL = 10µA 10 15 K Backplane Output Impedance R IL = 10µA @ 25 C 450 600 Data Out Current: IDOH Source Current, OH = 4.5-0.6 ma IDOL Sink Current, OL = 0.5 0.6 ma 3
AC ELECTRICAL CHARACTERISTI DD = 5, EE = -25, SS = 0, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL DD MIN TYP MAX UNITS Clock Period t 5 1200 ns Clock Pulse Width tcw 5 520 ns Data In - Setup tds 5 50 ns Data In - Hold tdh 5 400 ns Chip Select - Setup to Clock ts 5 200 ns Chip Select - Hold to Clock th 5 450 ns Load - Setup to Clock tls 5 500 ns Chip Select - Setup to Load tl 5 300 ns Load Pulse Width tlw 5 500 ns Chip Select - Hold to Load tl 5 300 ns Data Out alid, from Clock tcdo 5 00 ns TIMING DIAGRAM t ALID t DS ALID t DH t S t L t H t L t CDO t LS t LW OUTPUT ALID ALID ALID 4
ADDITIONAL HI-010/HI-110 PIN CONFIGURATIONS (See page 1 for the 52-Pin Plastic QFP) S26 S25 S24 S23 S22 S21 S20 32 S1 S1 S2 S2 S2 S30 S31 S32 N/C SS 10 11 12 13 14 15 16 1 6 5 4 3 2 1 44 43 42 41 40 HI-010J-5 & HI-110J-5 44 - PIN PLASTIC PLCC 1 1 20 21 22 23 24 25 26 2 2 3 3 3 36 35 34 33 32 31 30 2 S1 S16 S15 EE S14 S13 S12 S11 S10 S S OPT DD S1 S2 S3 S4 S5 S6 S SS S30 S2 S2 S2 S26 S36 S35 S34 S33 S32 S31 S30 S2 SS OPT DD S1 S2 S3 S4 S5 S6 S S 6 10 11 12 13 14 15 5 4 3 2 1 40 3 3 3 36 HI-010M-36 & HI-110M-36 40 - PIN CERAMIC LCC 16 1 1 1 20 21 22 23 24 25 35 34 33 32 31 30 2 2 2 26 S25 S24 S23 S22 S21 S20 30 S1 S1 OPT DD S3 S3 S1 S2 S3 S4 S5 S6 S 10 11 12 13 14 15 16 1 1 6 5 4 3 2 1 4 4 46 45 44 43 HI-010M-32 & HI-110M-32 4 - PIN CERAMIC LCC 1 20 21 22 23 24 25 26 2 2 2 30 42 41 40 3 3 3 36 35 34 33 32 S2 S2 S26 S25 S24 S23 S22 S21 S20 3 S1 S S10 S11 S12 S13 S14 EE S15 S16 S1 S S S10 S11 S12 S13 S14 S15 S16 S1 S1 EE 5
ORDERING INFORMATION HI - X10 J x - 5 (44-pin Plastic J-Lead PLCC) (44J) Blank F LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) LOGIC OF MASTER/ SLAE TEMPERATURE RANGE FLOW BURN IN 010 TTL 32 BOTH -40 C TO +5 C I NO 110 CMOS 32 BOTH -40 C TO +5 C I NO HI - X10PQ x x (52-pin Plastic Quad Flat Pack PQFP) (52P) Blank F LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) OF MASTER/ SLAE TEMPERATURE RANGE FLOW BURN IN I 3 BOTH -40 C TO +5 C I NO T 3 BOTH -55 C TO +125 C T NO 010PQ 110PQ LOGIC TTL CMOS HI - X10M -xx (Ceramic Leadless Chip Carrier LCC) (40S or 4S) MASTER/ SLAE OF OF LEADS FLOW BURN IN LEAD FINISH -32 BOTH 3 4 M YES -36 BOTH 30 40 M YES Tin / Lead (Sn / Pb) Solder Tin / Lead (Sn / Pb) Solder 010M 110M LOGIC TTL CMOS TEMPERATURE RANGE -55 C TO +125 C -55 C TO +125 C 6
SEMI-CUSTOM PACKAGING The above part numbers represent the standard configurations of the HI-010 & HI-110 products. They can also be provided with a varied number of output segments (30, 32 and 3), with either industrial or military screening and in a wide variety of packages. Listed below are currently available packages. Please contact the Holt Sales Department for your specific requirements. PACKAGE # DESCRIPTION LEADS PLASTIC DUAL-IN-LINE (PDIP) 40 PLASTIC QUAD FLAT PACK (PQFP) 52 PLASTIC J-LEAD CHIP CARRIER (PLCC) 44 CERAMIC DUAL-IN-LINE (CDIP) 40 CERAMIC LEADLESS CHIP CARRIER (LCC) 40 CERAMIC J-LEAD CHIP CARRIER 44 CERAMIC LEADED CHIP CARRIER 40 4 4 4 4 4
HI-010/HI-110 PACKAGE DIMENSIONS 44-PIN PLASTIC PLCC inches (millimeters) Package Type: 44J.045 x 45 PIN NO. 1 PIN NO. 1 IDENT.045 x 45.050 (1.2) BSC.60.005 (1.526.12) SQ..653.004 (16.56.102) SQ..031.005 (..12).01.004 (.432.102) See Detail A.13.00 (4.34.203).010 ±.001 (.254 ±.03).020 (.50) min BSC = Basic Spacing between Centers is theoretical true position dimension and has no tolerance. (JEDEC Standard 5).610.020 (15.44.50) DETAIL A R.035.010 (..254) 52-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: 52PQS.520 (13.2) BSC SQ.34 BSC SQ (10.0).0256 (.65) BSC.012 ±.003 (.30 ±.0).04 ±.013 (2.13 ±.32).063 (1.6) typ See Detail A BSC = Basic Spacing between Centers is theoretical true position dimension and has no tolerance. (JEDEC Standard 5).0 ±.00 (2.00 ±.20).00 (.20) min.005 (.13) R min.035 ±.006 (. ±.15) DETAIL A.00 ±.003 (.215 ±.05) R min 0
HI-010/HI-110 PACKAGE DIMENSIONS 40-PIN CERAMIC LEADLESS CHIP CARRIER inches (millimeters) Package Type: 40S PIN 1 IDENT..05 max (2.15).044.011 (1.11.20) PIN 1 IDENT..44 ±.00 (12.24.22) SQ. BSC = Basic Spacing between Centers is theoretical true position dimension and has no tolerance. (JEDEC Standard 5).020.003 (.50.06).040 (1.016) BSC 4-PIN CERAMIC LEADLESS CHIP CARRIER inches (millimeters) Package Type: 4S PIN 1 IDENT..00 max (2.26).040.00 (1.016.1) PIN 1 IDENT..563.00 (14.300.22) SQ..020 (.50) typ BSC = Basic Spacing between Centers is theoretical true position dimension and has no tolerance. (JEDEC Standard 5).020 (.50) typ.040 (1.016) BSC