OptiMOS 3 Power-Transistor

Type IPD6N3L G OptiMOS 3 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for DC/DC converters Qualified according to JEDEC 1) for target applications Product Summary V DS 3 V R DS(on),max 6 mω I D 5 A N-channel, logic level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Avalanche rated Pb-free plating Halogen-free according to IEC61249-2-21 * Type IPD6N3L G Avalanche rated Pb-free plating; RoHS compliant Package PG-TO252-3 PG-TO252-3-23 PG-TO251-3-11 PG-TO251-3 Marking 6N3L 6N3L 6N3L 6N3L Maximum ratings, at T j =25 C, unless otherwise specified Parameter Symbol Conditions Value Unit Continuous drain current I D V GS =1 V, T C =25 C 5 A V GS =1 V, T C =1 C 5 V GS =4.5 V, T C =25 C 5 V GS =4.5 V, T C =1 C 43 Pulsed drain current 2) I D,pulse T C =25 C 35 Avalanche current, single pulse 3) I AS T C =25 C 5 Avalanche energy, single pulse E AS I D =2 A, R GS =25 Ω 6 mj Reverse diode dv /dt dv /dt I D =5 A, V DS =24 V, di /dt =2 A/µs, T j,max =175 C 6 kv/µs Gate source voltage V GS ±2 V 1) J-STD2 and JESD22 * IPD6N3L G HF available with SP68632 only in Malacca, Malaysia available in HF Rev. 2.1 page 1 21-4-7

IPD6N3L G Maximum ratings, at T j =25 C, unless otherwise specified Parameter Symbol Conditions Value Unit Power dissipation P tot T C =25 C 56 W Operating and storage temperature T j, T stg -55... 175 C IEC climatic category; DIN IEC 68-1 55/175/56 Parameter Symbol Conditions Values Unit min. typ. max. Thermal characteristics Thermal resistance, junction - case R thjc - - 2.7 K/W SMD version, device on PCB R thja minimal footprint - - 75 6 cm² cooling area 4) - - 5 Electrical characteristics, at T j =25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS = V, I D =1 ma 3 - - V Gate threshold voltage V GS(th) V DS =V GS, I D =25 µa 1-2.2 Zero gate voltage drain current I DSS V DS =3 V, V GS = V, T j =25 C -.1 1 µa V DS =3 V, V GS = V, T j =125 C - 1 1 Gate-source leakage current I GSS V GS =2 V, V DS = V - 1 1 na Drain-source on-state resistance 5) R DS(on) V GS =4.5 V, I D =3 A - 7.2 9 mω V GS =1 V, I D =3 A - 5 6 Gate resistance R G - 1.4 - Ω Transconductance g fs V DS >2 I D R DS(on)max, I D =3 A 34 67 - S 2) See figure 3 for more detailed information 3) See figure 13 for more detailed information 4) Device on 4 mm x 4 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 7 µm thick) copper area for drain connection. PCB is vertical in still air. 5) Measured from drain tab to source pin Rev. 2.1 page 2 21-4-7

IPD6N3L G Parameter Symbol Conditions Values Unit min. typ. max. Dynamic characteristics Input capacitance C iss - 17 23 pf Output capacitance C oss V GS = V, V DS =15 V, f =1 MHz - 64 85 Reverse transfer capacitance C rss - 35 52 Turn-on delay time t d(on) - 5 - ns Rise time t r V DD =15 V, V GS =1 V, - 3 - Turn-off delay time t d(off) I D =3 A, R G =1.6 Ω - 2 - Fall time t f - 3 - Gate Charge Characteristics 6) Gate to source charge Q gs - 5.6 - nc Gate charge at threshold Q g(th) - 2.8 - Gate to drain charge Q gd V DD =15 V, I D =3 A, - 2.5 - Switching charge Q sw V GS = to 4.5 V - 5.3 - Gate charge total Q g - 1.8 14.4 Gate plateau voltage V plateau - 3.2 - V Gate charge total Q g V DD =15 V, I D =3 A, V GS = to 1 V - 22 3 Gate charge total, sync. FET Q g(sync) V DS =.1 V, V GS = to 4.5 V - 9.4 - nc Output charge Q oss V DD =15 V, V GS = V - 17 - Reverse Diode Diode continuous forward current I S - - 5 A T C =25 C Diode pulse current I S,pulse - - 35 Diode forward voltage V SD V GS = V, I F =3 A, T j =25 C -.88 1.1 V Reverse recovery charge Q rr V R =15 V, I F =I S, di F /dt =4 A/µs - - 1 nc 6) See figure 16 for gate charge parameter definition Rev. 2.1 page 3 21-4-7

1 IPD6N3L G 1 Power dissipation 2 Drain current P tot =f(t C ) I D =f(t C ); V GS 1 V 6 6 5 5 4 4 P tot [W] 3 I D [A] 3 2 2 1 1 5 1 15 2 5 1 15 2 T C [ C] T C [ C] 3 Safe operating area 4 Max. transient thermal impedance I D =f(v DS ); T C =25 C; D = Z thjc =f(t p ) parameter: t p parameter: D =t p /T 1 3 1 limited by on-state resistance 1 µs 1 2 1 µs.5 I D [A] 1 1 DC 1 µs 1 ms Z thjc [K/W] 1.2.1.5 1 ms.1.2.1 1 single pulse 1-1 1-1 1 V DS [V] 1 1 1 2.1 1-6 1-5 1-4 1-3 1-2 1-1 t p [s] 1 Rev. 2.1 page 4 21-4-7

IPD6N3L G 5 Typ. output characteristics 6 Typ. drain-source on resistance I D =f(v DS ); T j =25 C R DS(on) =f(i D ); T j =25 C parameter: V GS parameter: V GS 12 5 V 2 1 1 V 4.5 V 16 3 V 4 V 8 3.2 V 3.5 V I D [A] 6 4 3.5 V R DS(on) [mω] 12 8 4 V 4.5 V 5 V 1 V 2 3.2 V 4 11.5 V 3 V 2.8 V 1 2 3 V DS [V] 2 4 6 8 1 I D [A] 7 Typ. transfer characteristics 8 Typ. forward transconductance I D =f(v GS ); V DS >2 I D R DS(on)max g fs =f(i D ); T j =25 C parameter: T j 1 1 8 8 6 6 I D [A] g fs [S] 4 4 2 2 175 C 25 C 1 2 3 4 5 V GS [V] 2 4 6 8 1 I D [A] Rev. 2.1 page 5 21-4-7

1 1 1 IPD6N3L G 9 Drain-source on-state resistance 1 Typ. gate threshold voltage R DS(on) =f(t j ); I D =3 A; V GS =1 V V GS(th) =f(t j ); V GS =V DS ; I D =25 µa 12 2.5 1 2 8 R DS(on) [mω] 6 98 % typ V GS(th) [V] 1.5 1 4 2.5-6 -2 2 6 1 14 18 T j [ C] -6-2 2 6 1 14 18 T j [ C] 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f(v DS ); V GS = V; f =1 MHz I F =f(v SD ) parameter: T j 1 4 1 Ciss 1 3 Coss 1 25 C 175 C, 98% C [pf] I F [A] 175 C 25 C, 98% 1 2 1 Crss 1 1 1 5 1 15 2 25 3 V DS [V] 1..5 1. 1.5 2. V SD [V] Rev. 2.1 page 6 21-4-7

IPD6N3L G 13 Avalanche characteristics 14 Typ. gate charge I AS =f(t AV ); R GS =25 Ω parameter: T j(start) 1 V GS =f(q gate ); I D =3 A pulsed parameter: V DD 12 15 V 1 6 V 24 V 15 C 1 C 25 C 8 I AV [A] 1 V GS [V] 6 4 2 1 1-1 1 1 1 t AV [µs] 1 2 1 3 5 1 15 2 25 3 Q gate [nc] 15 Drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS) =f(t j ); I D =1 ma 34 V GS 32 Q g 3 V BR(DSS) [V] 28 26 V gs(th) 24 22 Q g(th) Q sw Q gate 2-6 -2 2 6 1 14 18 T j [ C] Q gs Q gd Rev. 2.1 page 7 21-4-7

IPD6N3L G Package Outline PG-TO252-3 Rev. 2.1 page 8 21-4-7

IPD6N3L G Package Outline PG-TO252-3-23 PG-TO251-3-11: Outline PG-TO251-3-21: Outline Rev. 2.1 page 9 21-4-7

IPD6N3L G Package Outline PG-TO251-3-11 Rev. 2.1 page 1 21-4-7

IPD6N3L G Package Outline PG-TO251-3 PG-TO251-3-11: Outline PG-TO251-3-21: Outline Rev. 2.1 page 11 21-4-7

IPD6N3L G Published by Infineon Technologies AG 81726 Munich, Germany 28 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 2.1 page 12 21-4-7