256K (32K x 8) Static RAM

256K (32K x 8) Static RAM Features High speed: 55 ns and 70 ns Voltage range: 4.5V 5.5V operation Low active power (70 ns, LL version) 275 mw (max.) Low standby power (70 ns, LL version) 28 µw (max.) Easy memory expansion with and features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead reverse TSOP-1, and 600-mil 28-lead PDIP packages Functional Description [1] The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable () and active LOW output enable () and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active LOW write enable signal () controls the writing/reading operation of the memory. When and inputs are both LOW, data on the eight data input/output pins (I/O 0 through I/O 7 ) is written into the memory location addressed by the address present on the address pins (A 0 through A 14 ). Reading the device is accomplished by selecting the device and enabling the outputs, and active LOW, while remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable () is HIGH. Logic Block Diagram INPUTBUFFER I/O 0 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 ROW DECODER 512 x 512 ARRAY SENSE AMPS I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 COLUMN DECODER POR DOWN I/O 6 I/O 7 A14 A13 A12 A11 A 1 A 0 Note: 1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com. Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 Document #: 38-05248 Rev. *B Revised August 27, 02

Pin Configurations A 5 A6 A7 A 8 A 9 A10 A11 A 12 A13 A14 I/O0 I/O1 I/O 2 GND Narrow SOIC Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 19 18 17 16 14 15 A4 A3 A2 A1 A0 I/O7 I/O6 I/O5 I/O4 I/O3 A 5 A6 A7 A 8 A 9 A10 A11 A 12 A13 A14 I/O0 I/O1 I/O 2 GND DIP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 19 18 17 16 14 15 A4 A3 A2 A1 A0 I/O7 I/O6 I/O5 I/O4 I/O3 A 1 A 2 A 3 A 4 A5 A 6 A7 A 8 A 11 7 8 A 12 A 10 6 9 A 13 A 9 5 10 A 14 4 11 I/O 3 TSOP I 0 12 I/O 1 2 Reverse Pinout 13 I/O 2 1 Top View 14 GND 28 15 I/O (not to scale) 3 16 A 8 A7 A 6 A 5 A 4 A 3 A 2 A 1 22 23 24 25 26 27 28 1 2 3 4 27 26 25 24 23 22 21 19 18 17 16 17 18 19 21 A 0 I/O 7 I/O 6 I/O 5 I/O 4 TSOP I 15 I/O 3 14 Top View GND 13 I/O (not to scale) 2 12 I/O 1 11 I/O 0 A 5 10 9 A 14 A 6 9 10 A 13 A 11 7 8 A 12 I/O 4 I/O 5 I/O 6 I/O 7 A 0 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature... 65 C to +150 C Ambient Temperature with Power Applied...0 C to +70 C Supply Voltage to Ground Potential (Pin 28 to Pin 14)... 0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State [2]... 0.5V to + 0.5V DC Input Voltage [2]... 0.5V to + 0.5V Output Current into Outputs (LOW)... ma Static Discharge Voltage... > 01V (per MIL-STD-883, Method 3015) Latch-up Current... > 0 ma Operating Range Range Ambient Temperature Commercial 0 C to +70 C 5V ± 10% Industrial 40 C to +85 C 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions CY62256 55 CY62256 70 Min. Typ. [3] Max. Min. Typ. [3] Max. V OH Output HIGH Voltage = Min., I OH = ma 2.4 2.4 V V OL Output LOW Voltage = Min., I OL = 2.1 ma 0.4 0.4 V V IH Input HIGH Voltage 2.2 +0.5V 2.2 +0.5V V IL Input LOW Voltage 0.5 0.8 0.5 0.8 V I IX Input Leakage Current GND < V I < 0.5 +0.5 0.5 +0.5 µa I OZ Output Leakage Current GND < V O <, Output Disabled 0.5 +0.5 0.5 +0.5 µa I CC I SB1 Operating Supply Current Automatic Power-down Current TTL Inputs = Max., I OUT = 0 ma, 28 55 28 55 ma f = f MAX = 1/t RC L 25 50 25 50 ma LL 25 50 25 50 ma Max., > V IH, 0.5 2 0.5 2 ma V IN > V IH or V IN < V IL, f = f MAX L 0.4 0.6 0.4 0.6 ma LL 0.3 0.5 0.3 0.5 ma Notes: 2. V IL (min.) = 2.0V for pulse durations of less than ns. 3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (T A = 25 C, ). Parameters are guaranteed by design and characterization, and not 100% tested. Unit V Document #: 38-05248 Rev. *B Page 2 of 11

Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions I SB2 Capacitance [4] Automatic Power-down Current CMOS Inputs Max., > 0.3V V IN > 0.3V, or V IN < 0.3V, f = 0 CY62256 55 CY62256 70 Min. Typ. [3] Max. Min. Typ. [3] Max. Unit 1 5 1 5 ma L 2 50 2 50 µa LL 0.1 5 0.1 5 µa Indust l Temp Range LL 0.1 10 0.1 10 µa Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 6 pf C OUT Output Capacitance = 5.0V 8 pf AC Test Loads and Waveforms Data Retention Characteristics Parameter Description Conditions [5] Min. Typ. [3] Max. Unit V DR for Data Retention 2.0 V I CCDR Data Retention Current L = 3.0V, > 0.3V, 2 50 µa LL V IN > 0.3V, or V IN < 0.3V 0.1 5 µa t CDR [4] t R [4] 5V OUTPUT 100 pf INCLUDING JIG AND SCOPE R1 1800Ω (a) R2 990Ω Data Retention Waveform R1 1800 Ω 5V OUTPUT 3.0V 10% 5pF R2 GND 990Ω <5ns INCLUDING JIG AND SCOPE (b) Equivalent to: THÉ VENIN EQUIVALENT 639Ω OUTPUT 1.77V ALL INPUT PULSES LL Ind l 0.1 10 µa Chip Deselect to Data Retention Time 0 ns Operation Recovery Time t RC ns 90% 90% 10% <5ns 3.0V DATA RETENTION MODE V DR > 2V 3.0V t CDR t R Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. No input may exceed + 0.5V. Document #: 38-05248 Rev. *B Page 3 of 11

Switching Characteristics Over the Operating Range [6] Parameter Read Cycle Description CY62256 55 CY62256 70 Min. Max. Min. Max. t RC Read Cycle Time 55 70 ns t AA Address to Data Valid 55 70 ns t OHA Data Hold from Address Change 5 5 ns t A LOW to Data Valid 55 70 ns t D LOW to Data Valid 25 35 ns t LZ LOW to Low-Z [7] 5 5 ns t HZ HIGH to High-Z [7, 8] 25 ns t LZ LOW to Low-Z [7] 5 5 ns t HZ HIGH to High-Z [7, 8] 25 ns t PU LOW to Power-up 0 0 ns t PD HIGH to Power-down 55 70 ns Write Cycle [9, 10] t WC Write Cycle Time 55 70 ns t S LOW to Write End 45 60 ns t AW Address Set-up to Write End 45 60 ns t HA Address Hold from Write End 0 0 ns t SA Address Set-up to Write Start 0 0 ns t P Pulse Width 40 50 ns t SD Data Set-up to Write End 25 30 ns t HD Data Hold from Write End 0 0 ns t HZ LOW to High-Z [7, 8] 25 ns t LZ HIGH to Low-Z [7] 5 5 ns Switching Waveforms [11, 12] Read Cycle No. 1 Unit t RC ADDRESS t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 100-pF load capacitance. 7. At any given temperature and voltage condition, t HZ is less than t LZ, t HZ is less than t LZ, and t HZ is less than t LZ for any given device. 8. t HZ, t HZ, and t HZ are specified with C L = 5 pf as in (b) of AC Test Loads. Transition is measured ±500 mv from steady-state voltage. 9. The internal Write time of the memory is defined by the overlap of LOW and LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write cycle #3 ( controlled, LOW) is the sum of t HZ and t SD 11. Device is continuously selected., = V IL. 12. is HIGH for Read cycle. Document #: 38-05248 Rev. *B Page 4 of 11

Switching Waveforms (continued) Read Cycle No. 2 [12, 13] t RC t A DATA OUT t D t LZ HIGH IMPEDAN DATA VALID t HZ t HZ HIGH IMPEDAN t LZ SUPPLY CURRENT t PU 50% t PD 50% ICC ISB [9, 14, 15] Write Cycle No. 1 ( Controlled) t WC ADDRESS t AW t HA t SA t P t SD t HD DATA I/O NOTE 16 DATA IN VALID t HZ [9, 14, 15] Write Cycle No. 2 ( Controlled) t WC ADDRESS t S t SA t AW tha t SD t HD DATA I/O DATA IN VALID Notes: 13. Address valid prior to or coincident with transition LOW. 14. Data I/O is high impedance if = V IH. 15. If goes HIGH simultaneously with HIGH, the output remains in a high-impedance state. Document #: 38-05248 Rev. *B Page 5 of 11

Switching Waveforms (continued) Write Cycle No. 3 ( Controlled, LOW) [10, 15] t WC ADDRESS t AW t HA t SA t SD t HD DATA I/O NOTE 16 DATA IN VALID t HZ t LZ Note: 16. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05248 Rev. *B Page 6 of 11

Typical DC and AC Characteristics NORMALIZED I CC, I SB AA NORMALIZED t NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 I CC 0.8 0.6 V IN =5.0V 0.4 0.2 I SB 0.0 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) NORMALIZED ACSS TIME vs. SUPPLY VOLTAGE 1.4 1.3 1.2 1.1 0.9 0.8 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) NORMALIZED I CC NORMALIZED t AA 1.4 1.2 0.8 0.6 0.4 0.2 0.0 55 25 125 1.6 1.4 1.2 0.8 0.6 55 25 125 AMBIENT TEMPERATURE ( C) OUTPUT SOUR CURRENT vs. OUTPUT VOLTAGE 1 OUTPUT SOUR CURRENT (ma) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED ACSS TIME vs. AMBIENT TEMPERATURE 100 80 60 40 I CC =5.0V V IN =5.0V AMBIENT TEMPERATURE ( C) =5.0V =5.0V 0 0.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) I SB2 µa OUTPUT SINK CURRENT (ma) STANDBY CURRENT vs. AMBIENT TEMPERATURE 3.0 2.5 2.0 1.5 0.5 0.0 =5.0V V IN =5.0V -0.5 55 25 105 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 1 100 80 60 40 I SB AMBIENT TEMPERATURE ( C) =5.0V 0 0.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) Document #: 38-05248 Rev. *B Page 7 of 11

Typical DC and AC Characteristics (continued) TYPICAL POR-ON CURRENT vs. SUPPLY VOLTAGE 3.0 TYPICAL ACSS TIME CHANGE vs. OUTPUT LOADING 30.0 NORMALIZED I CC vs.cycle TIME 1.25 NORMALIZED I PO 2.5 2.0 1.5 0.5 DELTA t AA (ns) 25.0.0 15.0 10.0 5.0 =4.5V NORMALIZED I CC 0 0.75 =5.0V V IN =0.5V 0.0 0.0 2.0 3.0 4.0 5.0 0.0 0 0 400 600 800 1000 0.50 10 30 40 SUPPLY VOLTAGE (V) CAPACITAN (pf) CYCLE FREQUENCY (MHz) Truth Table Inputs/Outputs Mode Power H X X High-Z Deselect/Power-down Standby (I SB ) L H L Data Out Read Active (I CC ) L L X Data In Write Active (I CC ) L H H High-Z Deselect, Output Disabled Active (I CC ) Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 55 CY62256LL 55SNI SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Industrial CY62256LL 55ZI Z28 28-lead Thin Small Outline Package 70 CY62256 70SNC SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Commercial CY62256L 70SNC CY62256LL 70SNC CY62256L 70SNI CY62256LL 70SNI Industrial CY62256LL 70ZC Z28 28-lead Thin Small Outline Package Commercial CY62256LL 70ZI Z28 Industrial CY62256 70PC P15 28-lead (600-Mil) Molded DIP Commercial CY62256L 70PC P15 CY62256LL 70PC P15 CY62256LL 70ZRI ZR28 28-lead Reverse Thin Small Outline Package Industrial Document #: 38-05248 Rev. *B Page 8 of 11

Package Diagrams 28-lead (600-mil) Molded DIP P15 51-85017-A 28-lead (300-mil) SNC (Narrow Body) SN28 51-85092-*B Document #: 38-05248 Rev. *B Page 9 of 11

Package Diagrams (continued) 28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28 51-85071-*G 28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28 51-85074-*F All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05248 Rev. *B Page 10 of 11 Cypress Semiconductor Corporation, 02. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Document Title: CY62256 256K (32K x 8) Static RAM Document Number: 38-05248 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 113454 03/06/02 MGN Change from Spec number: 38-00455 to 38-05248 Remove obsolete parts from ordering info, standardize format *A 115227 05/23/02 GBI Changed SN Package Diagram *B 116506 09/04/02 GBI Added footnote 1. Corrected package description in Ordering Information table Document #: 38-05248 Rev. *B Page 11 of 11