CCD linear image sensors

S55-048-0 S56-048-0 Back-thinned CCD image sensors with electronic shutter function The S55-048-0 and S56-048-0 are back-thinned CCD linear image sensors with an internal electronic shutter for spectrometers. These image sensors use a resistive gate structure that allows a high-speed transfer. Each pixel has a lengthwise size needed by spectrometers but ensures readout with low image lag. Image lag on these products is reduced by nearly a magnitude of as compared to the previous products (S55-048-0, S56-048-0). Note that the transmission of long wavelengths in the dead layer covering the horizontal shift register was reduced compared to previous products. Features Built-in electronic shutter Minimum integration time: μs High sensitivity from the ultraviolet region (spectral response range: 00 to 0 nm) Readout speed: MHz max. Image lag: 0.% typ. Applications Spectrometers Image readout Structure Parameter S55-048-0 S56-048-0 Pixel size (H ) 4 500 μm 4 00 μm Number of total pixels (H ) 8 Number of effective pixels (H ) 048 Image size (H ) 8.67 0.500 mm 8.67.000 mm Horizontal clock phase -phase Output circuit Two-stage MOSFET source follower Package 4-pin ceramic DIP (refer to dimensional outline) Window* Quartz glass* Cooling Non-cooled *: Temporary window type (ex. S55-048N-0) is available upon request. *: Resin sealing Resistive gate structure In ordinary CCDs, one pixel contains multiple electrodes and a signal charge is transferred by applying different clock pulses to those electrodes [Figure ]. In resistive gate structures, a single high-resistance electrode is formed in the active area, and a signal charge is transferred by means of a potential slope that is created by applying different voltages across the electrode [Figure ]. Compared to a CCD area image sensor which is used as a linear sensor by line binning, a one-dimensional CCD having a resistive gate structure in the active area offers higher speed transfer, allowing readout with low image lag even if the pixel height is large. [Figure ] Schematic diagram and potential of ordinary -phase CCD P P P P [Figure ] Schematic diagram and potential of resistive gate structure N - N N - N N - N N - N P + N N - N P KMPDC030EA REGL REGH STG TG Resistive gate P Potential slope KMPDC03EB www.hamamatsu.com

Absolute maximum ratings (Ta=5 C) Parameter Symbol Min. Typ. Max. Unit Operating temperature* 3 * 4 Topr -50 - +60 C Storage temperature Tstg -50 - +70 C Output transistor drain voltage OD -0.5 - +5 Reset drain voltage RD -0.5 - +8 Output amplifier return voltage ret -0.5 - +8 All reset drain voltage ARD -0.5 - +8 Horizontal input source voltage ISH -0.5 - +8 All reset gate voltage ARG - - +5 Storage gate voltage STG - - +5 Horizontal input gate voltage IGH, IGH - - +5 Summing gate voltage SG - - +5 Output gate voltage OG - - +5 Reset gate voltage RG - - +5 Transfer gate voltage TG - - +5 Resistive gate voltage High REGH Low REGL - - +5 Horizontal shift register clock voltage PH, PH - - +5 Soldering conditions* 5 Tsol 60 C, within 5 s, at least mm away from lead roots - *3: Package temperature *4: The sensor temperature may increase due to heating in high-speed operation. We recommend taking measures to dissipate heat as needed. For more details, refer to the technical information Resistive gate type CCD linear image sensors with electronic shutter. *5: Use a soldering iron. Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the product within the absolute maximum ratings. Operating conditions (Ta=5 C) Parameter Symbol Min. Typ. Max. Unit Output transistor drain voltage OD 5 8 Reset drain voltage RD 3 4 5 All reset drain voltage ARD 3 4 5 All reset gate voltage High* 6 ARGH 7 8 9 Low* 7 ARGL 0.5 Output gate voltage OG.5 3.5 4.5 Storage gate voltage STG.5 3.5 4.5 Substrate voltage SS - 0 - Resistive gate high voltage High REGHH 0.5.5 Low REGHL -.5-9.5-8.5 Resistive gate low voltage High REGLH - REGHH - 8.0 - Low REGLL -.5-9.5 - Output amplifier return voltage* 8 ret - Test point Horizontal input source ISH - RD - Horizontal input gate IGH, IGH -.5-9.5 - Horizontal shift register clock voltage High PHH, PHH 5 6 8 Low PHL, PHL -6-5 -4 Summing gate voltage High SGH 5 6 8 Low SGL -6-5 -4 Reset gate voltage High RGH 7 8 9 Low RGL -6-5 -4 Transfer gate voltage High TGH 9.5.5.5 Low TGL -6-5 -4 External load resistance RL.0..4 kω *6: All reset on *7: All reset off *8: Output amplifier return voltage is a positive voltage with respect to Substrate voltage, but the current flows in the direction of flow out of the sensor.

Electrical characteristics [Ta=5 C, fc=5 MHz, operating conditions: Typ. (P.), timing chart (P.6, 7)] Parameter Symbol Min. Typ. Max. Unit Signal output frequency fc - 5 MHz Line rate LR - 4 khz Horizontal shift register capacitance CPH, CPH - 00 - pf All reset gate capacitance CARG - 0 - pf Resistive gate capacitance S55-048-0-00 - CREG S56-048-0-000 - pf Summing gate capacitance CSG - - pf Reset gate capacitance CRG - - pf Transfer gate capacitance CTG - 0 - pf Charge transfer efficiency* 9 CTE 0.99995 0.99999 - - DC output level out 9 Output impedance Zo - 300 - Ω Output amplifier return current Iret - 0.4 - ma Power consumption S55-048-0 PAMP* - 75 - PREG* 50 0 60 S56-048-0 PAMP* - 75 - PREG* 30 60 90 mw Resistive gate resistance* S55-048-0 0.4 0.7.4 RREG S56-048-0 0.7.. kω *9: Charge transfer efficiency per pixel of CCD shift register, measured at half of the full well capacity *: Power consumption of the on-chip amplifier plus load resistance *: Power consumption at REG *: Resistance value between REGH and REGL Electrical and optical characteristics [Ta=5 C, fc=5 MHz, operating conditions: Typ. (P.), timing chart (P.6, 7)] Parameter Symbol S55-048-0 S56-048-0 Min. Typ. Max. Min. Typ. Max. Unit Saturation output voltage sat - Fw Sv - - Fw Sv - Full well capacity* 3 Fw 50 00-50 00 - ke - Linearity error* 4 LR - ±3 ± - ±3 ± % CCD node sensitivity Sv 9 9 μ/e - Dark current* 5 Non-MPP operation - 0 300-00 600 DS MPP operation - 40-5 60 ke - /pixel/s Non-MPP operation - - 300 - - 300 Dark output nonuniformity DSNU MPP operation - - - - - - % Readout noise Nr - 30 45-30 45 e - rms Dynamic range* 6 DR - 6670 - - 6670 - - Defective pixels* 7 - - - 0 - - 0 - Spectral response range λ 00 to 0 00 to 0 nm Peak sensitivity wavelength λp - 600 - - 600 - nm Photoresponse nonuniformity* 8 * 9 PRNU - ±3 ± - ±3 ± % Image lag* 8 * 0 Average image lag of all pixels - 0. - 0. L Maximum image lag of all pixels - 3-3 % *3: Operating voltages typ. *4: Signal level= ke- to 50 ke-. Defined so that the linearity error is zero when the signal level is at one-half the full well capacity. *5: Dark current is reduced to half for every 5 to 7 C decrease in temperature. *6: Dynamic range (DR) = Full well capacity / Readout noise *7: Pixels that exceed the DSNU or PRNU maximum *8: Measured at one-half of the saturation output (full well capacity) using LED light (peak emission wavelength: 660 nm) Fixed pattern noise (peak to peak) *9: Photoresponse nonuniformity = Signal 0 [%] *0: Percentage of unread signal level when a one-shot light pulse is irradiated so that the output is half the saturation output. The integration time during measurement is 5 μs for the S55-048-0 and 0 μs for the S56-048-0. For details, see the technical information (resistive gate type CCD linear image sensor with electronic shutter). 3

Spectral response (without window)* 0 (Typ. Ta=5 C) 0.5 (Typ. Ta=5 C) 80 0.4 Quantum efficiency (%) 60 40 Photosensitivity (A/W) 0.3 0. 0 0. 0 00 400 600 800 00 00 0 00 400 600 800 00 00 Wavelength (nm) Wavelength (nm) KMPDB036EA KMPDB0440EA *: Spectral response with quartz glass is decreased according to the spectral transmittance characteristic of window material. Spectral transmittance characteristic of window material 0 (Typ. Ta=5 C) 80 Transmittance (%) 60 40 0 0 00 300 400 500 600 700 800 900 00 Wavelength (nm) KMPDB0303EA 4

Device structure (conceptual drawing of top view in dimensional outline) Thinning Effective pixels Horizontal shift register Effective pixels 9 8 7 6 D63 D64 Horizontal CCD shift register D77 D78 D79 D80 3 Thinning 4 DD S045 S046 S047 S048 Resistive gate area D65 D66 D67 D68 D69 D70 S S S3 S4 D7 D7 D73 D74 D75 D76 0 7 8 Storage area D63 D64 Horizontal CCD shift register D77 D78 D79 D80 4 3 5 Horizontal shift register 5 3 4 6 9 Note: When viewed from the direction of the incident light, the horizontal shift register is covered with a thick silicon layer (dead layer). However, long-wavelength light passes through the silicon dead layer and may possibly be detected by the horizontal shift register. To prevent this, provide light shield on that area as needed. Note that the transmission of long wavelengths in the dead layer covering the horizontal shift register was reduced compared to previous products. Signal charges that undergo photoelectric conversion at each pixel of the photosensitive area are directed upward or downward based on the boundary line at the center of the photosensitive area and transferred.then, they are combined through the horizontal registers and read out by the amplifier. KMPDC0543EB 5

Timing chart Non-MPP operation line output period ARG REGH, REGL TG (REGH=+, REGL=-7.0 ) Tpwv Tovr Tpwh, Tpws Tpwar (electronic shutter: closed) Tinteg (electronic shutter: open) PH PH SG Tpwr RG 3..7 8 9 30... N* OS D D D79 D80 D3..D70, S...S048, D7..D78 Normal readout period Dummy readout period * Apply clock pulses to the specified terminals during the period of dummy readout. Set the total number of clock pulses N, according to the integration time. KMPDC054EB Parameter Symbol Min. Typ. Max. Unit ARG Pulse width Tpwar - - μs Rise and fall times Tprar, Tpfar 00 - - ns TG Pulse width Tpwv - - μs Rise and fall times Tprv, Tpfv 0 - - ns PH, PH* Rise and fall times Tprh, Tpfh - - ns Pulse width Tpwh 50 0 - ns Duty ratio - 40 50 60 % Pulse width Tpws 50 0 - ns SG Rise and fall times Tprs, Tpfs - - ns Duty ratio - 40 50 60 % RG Pulse width Tpwr 5 5 - ns Rise and fall times Tprr, Tpfr 5 - - ns TG - PH Overlap time Tovr - μs Integration time S55-048-0 5 - Tinteg S56-048-0 0 - μs *: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude. 6

MPP operation line output period ARG REGH, REGL Tpwv Tovr Tpwar (electronic shutter: closed) (REGH=+, REGL=-7.0 ) Tinteg (electronic shutter: open) Tpwreg (REGH, REGL=-9.5 ) Tregtr TG Tpwh, Tpws PH PH SG Tpwr RG 3..7 8 9 30... N* OS D D D79 D80 D3..D70, S...S048, D7..D78 Normal readout period Dummy readout period * Apply clock pulses to the specified terminals during the period of dummy readout. Set the total number of clock pulses N, according to the integration time. KMPDC054E KMPDC054EB Parameter Symbol Min. Typ. Max. Unit ARG Pulse width Tpwar * 3 - - μs Rise and fall times Tprar, Tpfar 00 - - ns Pulse width Tpwreg - Tinteg - Tregtr - μs Rise and fall times Tprreg, Tpfreg 0 - - ns REGH, REGL Transfer time S55-048-0 5 - Tregtr μs S56-048-0 0 - TG Pulse width Tpwv - - μs Rise and fall times Tprv, Tpfv 0 - - ns PH, PH* 4 Rise and fall times Tprh, Tpfh - - ns Pulse width Tpwh 50 0 - ns Duty ratio - 40 50 60 % Pulse width Tpws 50 0 - ns SG Rise and fall times Tprs, Tpfs - - ns Duty ratio - 40 50 60 % RG Pulse width Tpwr 5 5 - ns Rise and fall times Tprr, Tpfr 5 - - ns TG - PH Overlap time Tovr - μs Integration time S55-048-0 5 - Tinteg S56-048-0 0 - μs *3: The Min. value of Tpwar is equal to the normal readout period. *4: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude. 7

Dimensional outline (unit: mm) Photosensitive area 8.67 3.3 ± 0.35 Gold-plated, Alloy 4 4 3 A.03 ± 0.3.4 ± 0.5 Index mark 7.94 ± 0.3 0.6 ± 0.05* +0.05 0.5-0.03 38. ± 0.4.7 ± 0.5 Index mark Photosensitive surface.47 S55-048-0: A=0.500 S56-048-0: A=.000 3.0 ± 0.5 0.46 ± 0.05.7 ± 0..54 ± 0.3.83 ± 0.7 * Glass thickness (refractive index.5) Weight: 3.8 g typ. KMPDA030EA Pin connections Pin no. Symbol Function Remark (standard operation) OS Output transistor source RL=. kω OD Output transistor drain +5 3 OG Output gate +3.5 4 SG Summing gate Same pulse as PH 5 ret Output amplifier return + 6 RD Reset drain +4 7 REGL Resistive gate (low) -7 (Non-MPP operation) 8 REGH Resistive gate (high) + (Non-MPP operation) 9 PH CCD horizontal register clock- +6 /-5 PH CCD horizontal register clock- +6 /-5 IGH Test point (horizontal input gate-) -9.5 IGH Test point (horizontal input gate-) -9.5 3 ARG All reset gate +8 /+ 4 ARD All reset drain +4 5 ISH Test point (horizontal input source) Connect to RD 6-7 SS Substrate GND 8 RD Reset drain +4 9-0* 5 STG Storage gate +3.5 * 5 STG Storage gate +3.5-3 TG Transfer gate +.5 /-5 4 RG Reset gate +8 /-5 *5: Pins 0 and are shorted inside the package. 8

OS output waveform example (fc=5 MHz, RL=. kω, OD=+5 ) DC level (Reset level) Signal Reset feed-through Signal level High-speed signal processing circuit example (using S55/S56-048-0 and analog front-end IC) To FPGA +5 +3.3 4 3 0 9 8 7 6 5 4 3 RG TG NC STG STG NC RD SS NC ISH ARD ARG OS OD OG SG ret RD REGL REGH PH PH IGH IGH 3 4 5 6 7 8 9. k +OD μf 330 0. μf 5 6 7 8 9 0 3 4 5 6 7 8 SDATA SCLK SLOAD ADD ASS CAPB CAPT INB CML ING OFFSET INR ASS ADD AD986KRS D0 (LSB) D D D3 D4 D5 D6 D7 (MSB) DR SS DR DD OEB ADCCLK CDSCLK CDSCLK 4 3 9 8 7 6 5 4 3 330 330 330 330 To FPGA S55/S56-048-0 KMPDC056EA 9

Related information www.hamamatsu.com/sp/ssd/doc_en.html Precautions Disclaimer Image sensors Technical information Resistive gate type CCD linear image sensors with electronic shutter C65-0 Driver circuit for CCD linear image sensor (sold separately) The C65-0 is a driver circuit designed for HAMAMATSU CCD linear image sensors. The C65-0 can be used in spectrometer when combined with the CCD linear image sensor. Features Built-in 6-bit A/D converter Interface of computer: USB.0 Operates by DC+5 Information described in this material is current as of December, 05. Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always contact us for the delivery specification sheet to check the latest specifications. The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product use. Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. www.hamamatsu.com HAMAMATSU PHOTONICS K.K., Solid State Division 6- Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (8) 53-434-33, Fax: (8) 53-434-584 U.S.A.: Hamamatsu Corporation: 360 Foothill Road, Bridgewater, N.J. 08807, U.S.A., Telephone: () 908-3-0960, Fax: () 908-3-8 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr., D-8 Herrsching am Ammersee, Germany, Telephone: (49) 85-375-0, Fax: (49) 85-65-8 France: Hamamatsu Photonics France S.A.R.L.: 9, Rue du Saule Trapu, Parc du Moulin de Massy, 988 Massy Cedex, France, Telephone: 33-() 69 53 7 00, Fax: 33-() 69 53 7 United Kingdom: Hamamatsu Photonics UK Limited: Howard Court, Tewin Road, Welwyn Garden City, Hertfordshire AL7 BW, United Kingdom, Telephone: (44) 707-94888, Fax: (44) 707-35777 North Europe: Hamamatsu Photonics Norden AB: Torshamnsgatan 35 6440 Kista, Sweden, Telephone: (46) 8-509-03-00, Fax: (46) 8-509-03-0 Italy: Hamamatsu Photonics Italia S.r.l.: Strada della Moia, int. 6, 000 Arese (Milano), Italy, Telephone: (39) 0-9358733, Fax: (39) 0-935874 China: Hamamatsu Photonics (China) Co., Ltd.: B0, Jiaming Center, No.7 Dongsanhuan Beilu, Chaoyang District, Beijing 000, China, Telephone: (86) -6586-6006, Fax: (86) -6586-866 Cat. No. KMPD55E0 Dec. 05 DN