Available at Digi-Key** www.digikey.com High Precision TCXO / VCTCXO Oscillators 2111 Comprehensive Drive Phone: 60-81- 722 Fax: 60-81- 00 US Headquarters: 60-81-722 European Headquarters: +-61-72221 Description: The Connor-Winfield s T0/T200 and the TV0/TV200 series have very high frequency stability with excellent phase noise performance. Available in a x7mm surface mount package. These TCXO's and VCTCXO's through the use of Analog Temperature Compensation are capable of holding sub 0-ppb or 200-ppb stabilities over the commercial or industrial temperature ranges. The surface mount package is designed for highdensity mounting and is optimum for mass production. Applications: Basestation, Communications,DSL / ADSL, Femtocell, IP Timing, LTE, Precision GPS, SONET / SDH, WiMAX / WiBro, WLAN. T200V 121 20.0 MHZ Features: Models: T0 / T200-Series TV0 / TV200-Series Package T0-T200 Series x 7mm Pad TV0-TV200 Series x 7mm Pad Frequencies Available:, 12.8, 1.2, 20.0, 2.76 or 0.0 MHz. Vdc Operation Output Logic: LVCMOS Frequency Stability: T0 / TV0: +/-0 ppb, 0 to 70 C T200 / TV200: +/-200 ppb, -0 to 8 C Fixed Frequency - TCXO Optional Control Voltage - VCTCXO Low Jitter <0.0 ps RMS Low Phase Noise Tri-State Enable/Disable: Available on T0 / T200 Models. Tape and Reel Packaging RoHS Compliant / Lead Free Absolute Maximum Ratings Storage Temperature -0-8 C Supply Voltage () -0. -.6 Vdc Input Voltage (Vc) -0. - + 0. Vdc Ordering Information T 200 V - 20.0M Type / Package TCXO / VCTCXO Series T =.0x7.0 mm Pads TV =.0x7.0 mm Pads Frequency Stability and Temperature Range 0 = ±0 ppb, 0 to 70 C 200 = ±200 ppb, -0 to 8 C Supply Voltage =. Vdc Output Logic = LVCMOS TCXO or VCTCXO F = TCXO V = VCTCXO Output Frequency Frequency Format -xxx.xm Min -xxx.xxxxxxm Max *Amount of numbers after the decimal point. M = MHz Example: Part Number Page 1 of 6 T0F-01.2M = x7mm pad package, ±0 ppb, 0 to 70 C,. Vdc, LVCMOS Output, TCXO, 1.2 MHz T200V-020.0M = x7mm pad package, ±200 ppb, -0 to 8 C,. Vdc, LVCMOS Output, VCTCXO, 20.0 MHz TV0F-0.0M = x7mm pad package, ±0 ppb, 0 to 70 C,. Vdc, LVCMOS Output, TCXO,.0 MHz TV200V-012.8M = x7mm pad package, ±200 ppb, -0 to 8 C,. Vdc, LVCMOS Output, VCTCXO, 12.8 MHz
Phone: 60-81- 722 Fax: 60-81- 00 Operating Specifications Available Output Frequencies (Fo).0, 12.8, 1.76, 1.2, 20.0, 2.76, 2.0, and 0.0 MHz Frequency Calibration @ 2 C -1.0-1.0 ppm 1 Frequency Stability (See Ordering Information for full part number) Model T0x, TV0x -0-0 ppb 2 Model T200x, TV200x -200-200 ppb 2 Frequency vs. Load Stability -0.0-0.0 ppm ±% Frequency vs. Voltage Stability -0.0-0.0 ppm ±% Static Temperature Hysteresis - - 0.0 ppm Freq. shift after reflow soldering -1.0-1.0 ppm Long Term Stability -1.0-1.0 ppm Aging per Life (20 Years) -.0 -.0 ppm per Day -0-0 ppb per Second -.6E-1 Operating Temperature Range (See Ordering Information for full part number) Model T0x, TV0x 0-70 C Model T200x, TV200x -0-8 C Supply Voltage ().1.0.6 Vdc Supply Current (Icc) - - 2.1 ma Jitter: Period Jitter -.0.0 ps RMS Integrated Phase Jitter (12K to 20M) - 0. 1.0 ps RMS 6 SSB Phase Noise for Fo=.0 MHz @ 1 Hz offset - -60 - dbc/hz @ Hz offset - -8 - dbc/hz @ 0 Hz offset - -126 - dbc/hz @ 1 KHz offset - -1 - dbc/hz @ KHz offset - -11 - dbc/hz @ 0 KHz offset - -12 - dbc/hz @ 1 MHz offset - -1 - dbc/hz Start-Up Time - - ms Control Voltage Input Characteristics Control Voltage 0. 1.6.0 V Frequency Pullability ± - - ppm Control Voltage Slope Positive Slope Monotonic Linearity - - % Input Impedance 0K - - Ohm Modulation Bandwidth (db) - - KHz Page 2 of 6
Phone: 60-81- 722 Fax: 60-81- 00 Enable /Disable Input Characteristics (Pad 8) (Models T0F, T200F, T0V and T200V Only) Enable Input Voltage -(Vih) 70% - - Vdc 7 Disable Input Voltage - (Vil) - - 0% Vdc 7 Function Low: High or Open: Output Disabled (High Impedance) Enabled LVCMOS Output Characteristics Load (CL) - 1 - pf 8 Voltage (High) (Voh) 0% - - Vdc (Low) (Vol) - - % Vdc Duty Cycle at 0% of 0 % Rise / Fall Time % to 0% - 8 ns Package Package Characteristics Hermetically sealed ceramic package with grounded metal cover Environmental Characteristics Vibration: Vibration per Mil Std 88E Method 2007. Test Condition A. Shock: Mechanical Shock per Mil Std 88E Method 2002. Test Condition B. Soldering Process: RoHS compliant lead free. See soldering profile on page 2. Notes: 1. Initial calibration @ 2 C. ±2 C, for VCTCXO's Vc = 1.6V. Specifications at time of shipment after 8 hours of operation. 2. Frequency stability vs. change in temperature. [±(Fmax-Fmin)/2.Fo]. For VCTCXO's - Vc -= 1.6V. Frequency change after reciprocal temperature ramped over the operating range. Frequency measured before and after at 2 C. Two consecutive reflows after 1 hour recovery @ 2 C.. Frequency drift over 1 year @ 2 C. 6. BW = 12 KHz to Fo/2 MHz 7. Leave Pad 8 on models, T0F, T200F, T0V, T200V unconnected if enable / disable function is not required. When tri-stated, the output stage is disabled but the oscillator and compensation circuit are still active (current consumption < 1 ma). 8. Attention: To achieve optimal frequency stability, and in some cases to meet the specification stated on this data sheet, it is required that the circuit connected to this TCXO output must have the equivalent input capacitance that is specified by the nominal load capacitance. Deviations from the nominal load capacitance will have a graduated effect on the stability of approximately 20 ppb per pf load difference. Page of 6
Phone: 60-81- 722 Fax: 60-81- 00 T0/T200 Package Outline T0/T200 Suggested Pad Layout T0/T200 Pad Connections Pin 1 0.00 (0.762mm) ( Places) 0.08 (0.6mm) ( Places) 0.276 ± 0.006 (7.0mm) T200V 121 20.0 MHZ 1 2 8 Bottom View 7 6 0.0 (2.mm) 0.17 ± 0.006 (.0mm) 0.02(6 Places) (0.6mm) 0.0 (2.mm) 0.07 Max. (2.0mm) 0.00 (1.02mm) (6 Places) Dimensional Tolerance: ±.00 (.127mm) ±.02 (.08mm) 0.21 (.6mm) 0.07 (0.mm) 1 0.2 (7.mm) 0.00 (0.76mm) 8 7 6 2 0.01 (1.28mm) Keep Out Area 0.01 (1.28mm) * Do not route any traces in the keep out area. It is recommended the next layer under the keep out area is to be ground plane. 1: Do Not Connect 2: Do Not Connect : Do Not Connect : : Output 6: Do Not Connect 7: Do Not Connect 8: Enable / Disable : Supply Voltage ( : VCTCXO: Control Voltage (Vc) TCXO: N/C T0/T200 and TV0/TV200 Series Alternate Package Outline 0.276 ±0.006 (7.0mm) T200 1 2.76 MHZ 0.17 ±0.006 (.0mm) 0.0 (2.mm) Alternate package applies to all part numbers at select frequencies. The differences are the top view crystal size, and the overall height. Bottom view, suggested pad layout, and pad connections all remain the same as above. TV0/TV200 Package Outline TV0/TV200 Suggested Pad Layout TV0/TV200 Pad Connections Pad 1 0.0 (0. 0mm) ( Places) 0.276 ± 0.006 (7.0mm) TV0F 121.0 MHZ () 1 2 (Bottom View) 0.17 ± 0.006 (.0mm) 0.07 Max. (2.0mm) Dimensional Tolerance: ±.00 (.127mm) ±.02 (.08mm) 0.0 ( 1.0mm) ( Places) 0.16 (.2mm) () 1 0.22 2 (.7mm) 0.071 (1.8mm) Places 0.07 (1.2mm) Places Keep Out * Area * Do not route any traces in the keep out area. It is recommended the next layer under the keep out area is to be ground plane. 1: VCTCXO: Voltage Control (Vc) TCXO: N/C 2: : Output : Supply () Page of 6
...... 2111 Comprehensive Drive Phone: 60-81- 722 Fax: 60-81- 00 T0 / T200 Design Recommendations T0 / T200 Test Circuit, should have Connect a 0.01uF bypass capacitor <0.1 (2.mm) from the pad. 8 6 0.0 (0.2mm) Recommended clearance inductance for internal copper flood. 0 Ohm trace <1 by design Buffer Enable/ Disable DNC DNC 1, should have Supply Voltage 8 7 6 1 2 1 pf Output TOP LAYER GROUND LAYER OSC 0 Ohm Trace Without Output Vias Buffer 0.1 uf nf TCXO = N/C VCTCXO = Vc DNC DNC DNC DNC = Do Not Connect BOTTOM LAYER TV0 / TV200 Design Recommendations TV0 / TV200 Test Circuit, should have Connect a 0.01uF bypass capacitor <0.1 (2.mm) from the pad. 1 2 0.0 (0.2mm) Recommended clearance inductance for internal copper flood., should have TOP LAYER GROUND LAYER OSC 0 Ohm Trace Without Output Vias Buffer 0 Ohm trace <1 by design Buffer Supply Voltage 0.1 uf nf TCXO = N/C VCTCXO = Vc 1 2 1 pf Output BOTTOM LAYER Attention: To achieve optimal frequency stability, and in some cases to meet the specification stated on this data sheet, it is required that the circuit connected to this TCXO output must have the equivalent input capacitance that is specified by the nominal load capacitance. Deviations from the nominal load capacitance will have a graduated effect on the stability of approximately 20 ppb per pf load difference. Page of 6
Phone: 60-81- 722 Fax: 60-81- 00 LVCMOS Output Waveform Phase Noise Information 1V/Div Solder Profile x7 mm Tape and Reel Information Temperature 260 C 260 C 220 C 180 C 10 C 120 C 1 0 Up to 120 s Typical s 60 to 0 s Typical Meets IPC/JEDEC J-STD-020C Revision History Revision Date Changes A00 12/0/11 Advanced information data sheet released A01 0/2/12 Added 12.8 MHz and +/-0ppb 0 to 70 C Models 02 0/26/12 Updated integrated phase jitter to 0. ps RMS nominal. 0 /12/12 Removed M series 0 01/0/1 Updated phase noise information 0 02/0/1 Updated to 2.76 MHz and 0.0 MHz Frequencies 06 06/1/16 Input Voltage, Frequency vs Load and Voltage Stability edits Page 6 of 6