NAVAL POSTGRADUATE SCHOOL MONTEREY CALIFORNIA THESIS SYMMETRICAL RESIDUE-TO-BINARY CONVERSION ALGORITHM PIPELINED FPGA IMPLEMENTATION AND TESTING LOGIC FOR USE IN HIGH-SPEED FOLDING DIGITIZERS by Ross Alan Monta December 5 Thesis Advisor: Thesis Co Advisor: Philli E. Pace Douglas Fouts Aroved for ublic release; distribution is unlimited.
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REPORT DOCUMENTATION PAGE Form Aroved OMB No. 74-88 Public reorting burden for this collection of information is estimated to average hour er resonse including the time for reviewing instruction searching eisting data sources gathering and maintaining the data needed and comleting and reviewing the collection of information. Send comments regarding this burden estimate or any other asect of this collection of information including suggestions for reducing this burden to Washington headquarters Services Directorate for Information Oerations and Reorts 5 Jefferson Davis Highway Suite 4 Arlington VA -4 and to the Office of Management and Budget Paerwork Reduction Project (74-88) Washington DC 5.. AGENCY USE ONLY (Leave blank). REPORT DATE December 5 4. TITLE AND SUBTITLE: Symmetrical Residue-to-Binary Conversion Algorithm Pielined FPGA Imlementation and Testing Logic for Use in High-Seed Folding Digitizers. 6. AUTHOR(S) Ross Alan Monta 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) Naval Postgraduate School Monterey CA 994-5 9. SPONSORING /MONITORING AGENCY NAME(S) AND ADDRESS(ES) Office of Naval Research (Code ) Arlington VA -995. REPORT TYPE AND DATES COVERED Master s Thesis 5. FUNDING NUMBERS 8. PERFORMING ORGANIZATION REPORT NUMBER. SPONSORING/MONITORING AGENCY REPORT NUMBER. SUPPLEMENTARY NOTES The views eressed in this thesis are those of the author and do not reflect the official olicy or osition of the Deartment of Defense or the U.S. Government. a. DISTRIBUTION / AVAILABILITY STATEMENT b. DISTRIBUTION CODE Aroved for ublic release; distribution is unlimited.. ABSTRACT (maimum words) The robust symmetrical number system (RSNS) can lay a significant role in the reduction of encoding errors within a low-ower folding analog-to-digital converter (ADC). A key art of this ADC design is the logic block that converts the symmetrical residues from each channel into a more convenient binary outut. This thesis describes a robust symmetrical residue-to-binary conversion algorithm for moduli m = 7 m = 8 and m = 9 (ADC dynamic range M = 6 ). Also described is a ielined digital logic imlementation for use in high seed rogrammable logic or alication secific integrated circuits. To verify correct oututs of the robust symmetrical residue-to-binary conversion algorithm a digital test circuit is described that generates the thermometer code (symmetrical residues) for the -channel ADC design. 4. SUBJECT TERMS ADC Robust Symmetrical Numbering System (RSNS) Xilin 7. SECURITY CLASSIFICATION OF REPORT Unclassified 8. SECURITY CLASSIFICATION OF THIS PAGE Unclassified 9. SECURITY CLASSIFICATION OF ABSTRACT Unclassified 5. NUMBER OF PAGES 85 6. PRICE CODE. LIMITATION OF ABSTRACT NSN 754--8-55 Standard Form 98 (Rev. -89) Prescribed by ANSI Std. 9-8 UL i
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Aroved for ublic release; distribution is unlimited. SYMMETRICAL RESIDUE-TO-BINARY CONVERSION ALGORITHM PIPELINED FPGA IMPLEMENTATION AND TESTING LOGIC FOR USE IN HIGH-SPEED FOLDING DIGITIZERS Ross A. Monta Major United States Marine Cors B.S. Carnegie Mellon University 995 Submitted in artial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING from the NAVAL POSTGRADUATE SCHOOL December 5 Author: Ross Alan Monta Aroved by: Philli E. Pace Thesis Advisor Douglas Fouts Co-Advisor Jeffrey B. Knorr Chairman Deartment of Electrical and Comuter Engineering iii
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ABSTRACT The robust symmetrical number system (RSNS) can lay a significant role in the reduction of encoding errors within a low-ower folding analog-to-digital converter (ADC). A key art of this ADC design is the logic block that converts the symmetrical residues from each channel into a more convenient binary outut. This thesis describes a robust symmetrical residue-to-binary conversion algorithm for moduli m = 7 m = 8 and m = (ADC dynamic range M = 6 ). Also described is a ielined digital logic 9 imlementation for use in high seed rogrammable logic or alication secific integrated circuits. To verify correct oututs of the robust symmetrical residue-to-binary conversion algorithm a digital test circuit is described that generates the thermometer code (symmetrical residues) for the -channel ADC design. v
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TABLE OF CONTENTS I. INTRODUCTION... A. FOLDING ANALOG TO DIGITAL CONVERTER BRIEF HISTORY... B. PRINCIPAL CONTRIBUTIONS... C. THESIS OUTLINE... II. RSNS RESIDUE-TO-BINARY CONVERSION...7 A. GENERAL BACKGROUND...7 B. APPLICATION TO ADC...7. Position Bit Equations...8. Even Residue Flags..... Modulus Residue Sub-Sequence Flags... 4. Conditional Bit Reversal... 5. Alignment Logic...4 6. Encoder...5 7. Adder...5 III. LOGIC DESIGN FOR ROBUST SYMMETRICAL NUMBERING SYSTEM LOGIC BLOCK...7 A. MATLAB REALIZATION...7. Thermometer Code to Position Bit Conversion...8. Even Residue Flags...8. MRSS...8 4. Conditional Bit Reversal...9 5. Alignment Logic...9 6. Encoder... 7. Adder... B. XILINX REALIZATION.... Thermometer Code to Position Bit Conversion and Even Residue Flags.... Modulus Residue Sub-Sequence Flags...4. Conditional Bit Reversal...5 4. Alignment Logic...6 5. Encoder...7 6. Adder...8 IV. TEST DEVELOPMENT AND VERIFICATION... A. THERMOMETER CODE DEVELOPMENT.... MATLAB.... Field Programmable Gate Array Schematic Cature... B. THERMOMETER CODE VERIFICATION...45. MATLAB...45. Field Programmable Gate Array Schematic Cature...46 vii
V. VERIFICATION OF TEST RESULTS...49 A. MATLAB CODE...49 B. FPGA DESIGN...5 VI. CONCLUSION AND RECOMMENDATIONS FOR FUTURE WORK...5 A. CONCLUSIONS...5 B. RECOMMENDATIONS FOR FUTURE RESEARCH...54. Program FPGA in Order to Test Performance of the Design....54. Imlement the RSNS Digital Processing Portion of the ADC and Test in ASIC Simulator Software....54 APPENDIX A. MATLAB CODE FOR GENERATING THERMOMETER CODE INPUTS...55 APPENDIX B. CODE FOR IMPLEMENTATION OF RESIDUE-TO- BINARY IN MATLAB...6 LIST OF REFERENCES...65 INITIAL DISTRIBUTION LIST...67 viii
LIST OF FIGURES Figure. Block Diagram of the Symmetrical Residue-to-Binary Converter...8 Figure. Adder imlementation for RSNS-to-binary for []....5 Figure. Adder imlementation of RSNS-to-binary for this thesis...5 Figure 4. Hierarchical View of RSNS-to-binary converter...7 Figure 5. -to- Multileer...9 Figure 6. Channel Position Bit and Even Bit Flag Schematic... Figure 7. Channel Position Bit and Even Bit Flag Schematic... Figure 8. Channel Position Bit and Even Bit Flag Schematic...4 Figure 9. MRSS Xilin Schematic...5 Figure. MRSS Xilin Schematic...5 Figure. Channel Conditional Bit Reversal Schematic...5 Figure. Channel Conditional Bit Reversal Schematic...6 Figure. Alignment Logic for Position Bits after Inversion...7 Figure 4. Binary to 5 Bit Encoder Schematic...8 Figure 5. 7 Bit Adder Schematic...9 Figure 6. Karnaugh mas for Channel ( m = 7 )Thermometer code bits S and S...4 Figure 7. Karnaugh mas for Channel ( m = 7 )Thermometer code bits S and S...5 Figure 8. Karnaugh mas for Channel ( m = 7 ) Thermometer code bits S4 and S5...5 Figure 9. Karnaugh ma for Channel ( m = 7 ) Thermometer code bit S6...5 Figure. Thermometer Code 7-Bit Generator...6 Figure. Karnaugh mas for Channel ( m = 8) Thermometer code bits S and S...7 Figure. Karnaugh mas for Channel ( m = 8) Thermometer code bits S and S...8 Figure. Karnaugh mas for Channel ( m = 8) Thermometer code bits S4 and S5...8 Figure 4. Karnaugh mas for Channel ( m = 8) Thermometer code bits S6 and S7...8 Figure 5. Thermometer Code 8 Bit Generator...9 Figure 6. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S...4 Figure 7. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S...4 Figure 8. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S...4 Figure 9. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S...4 i
Figure. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S4...4 Figure. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S5...4 Figure. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S6...4 Figure. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S7...4 Figure 4. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S8...4 Figure 5. Thermometer Code 9 Bit Generator...44 Figure 6. MATLAB Thermometer Code samle...45 Figure 7. Hierarchal Schematic of Additional testing circuits....46 Figure 8. Test-Bench Inuts and Oututs from Thermometer Code Generators...47 Figure 9. Grah of Outut of MATLAB Logic code...49 Figure 4. RSNS-to-Binary Waveform Oututs for Dynamic Range Values :...5 Figure 4. RSNS-to-Binary Waveform Oututs for Dynamic Range Values :4...5 Figure 4. RSNS-to-Binary Waveform Oututs for Dynamic Range Values 4:6...5 Figure 4. RSNS-to-Binary Waveform Oututs for Dynamic Range Values 6:48...5 Figure 44. RSNS-to-Binary Waveform Oututs for Dynamic Range Values 48:6...5 Figure 45. RSNS-to-Binary Waveform Oututs for Dynamic Range Values 6:7...5 Figure 46. RSNS-to-Binary Waveform Oututs for Dynamic Range Values 7:84...5 Figure 47. RSNS-to-Binary Waveform Oututs for Dynamic Range Values 84:96...5 Figure 48. RSNS-to-Binary Waveform Oututs for Dynamic Range Values 96:8...5 Figure 49. RSNS-to-Binary Waveform Oututs for Dynamic Range Values 8:...5 Figure 5. RSNS-to-Binary Waveform Oututs for Dynamic Range Values :5...5
LIST OF TABLES Table. List of Variables...4 Table. Encoder Truth Table... Table. Channel Thermometer Code... Table 4. RSNS Gray Code Proerty Showing the Number of Comarators for each channel... Table 5. Channel ( m = ) Waveform Truth Table...4 7 Table 6. Channel ( m = ) Waveform Truth Table...7 8 Table 7. Channel ( m = 9 ) Waveform Truth Table...4 i
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ACKNOWLEDGMENTS During the writing of this Thesis the easiest tasks became difficult and time slied away faster than was eected. This fact made me areciate the little things in life that much more. I owe my dear wife Dru and my five children Blake Jordan Chandler Dominic and Rylie my most sincere areciation for utting u with the long hours and the stress. I would also like to thank my Advisors for their tutelage and suort during this most enlightening endeavor. Their assistance in both technical and rofessional discussion of this subject matter made it both educational and enjoyable. This work was suorted by the Office of Naval Research. (ONR code ). In closing I would like to thank my Family both souse and children along with my arents and siblings for the suort they have shown me throughout my life. With them and the suort and blessings of my God I have and will continue to erform my military and family duties to the best of my ability. iii
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EXECUTIVE SUMMARY The goal of this thesis is to eand on already eisting theory in order to create a high resolution high seed low ower Analog to Digital Converter (ADC). Once imlemented this ADC will have many uses to include incororation into miniaturized sensor networks system-on-a-chi (SOC) and many other areas where size and ower consumtion are limiting factors. The most recent work in this area was done by Brian Luke in a Dissertation for his Doctorate at the Naval Postgraduate School []. This work demonstrated the theory behind a channel folding ADC that utilized the RSNS conversion in order to reduce the ower consumtion and size of a system. The focus in his study was for SOC alications. The ower and size savings of the design were significant; however it did not achieve a high enough resolution. Utilizing the theory develoed in the above dissertation a roject for a higher resolution folding ADC was initiated. In this thesis the focus was to eand on the folding ADC s RSNS digital rocessing to achieve higher resolution from the overall circuit being develoed. The contribution of the research contained in this thesis was two fold. First to verify the theory contained in [] for a three channel RSNS folding ADC could be eanded to achieve higher resolution. Second to design and test a circuit using the eanded higher resolution equations roduced and to verify the actual results match the eected theoretical results. In order to accomlish the eansion verification the first decision to be made was to establish the moduli for the three channels of the system. Initially 5 6 and 7 were considered. However they did not sufficiently increase the resolution to the required value. Moduli 7 8 and 9 for channels and resectively were chosen and found to accomlish an accetable resolution for theoretical validation of the digital system. This thesis demonstrated and verified the theoretical eansion of the folding circuit by imlementing the equations in MATLAB. The results of the MATLAB v
simulation demonstrated a useful dynamic range of 6 or 7-bits. The MATLAB also verified the roer test vectors and the oerational range of the system. Once the theory was verified a circuit was designed using Xilin Project Navigator and Mentor Grahics Model Sim rograms. The schematic cature functionality of Xilin was utilized and due to the etensive amount of wiring took several months to comlete. In order to test the design catured in Xilin a Model Sim waveform had to be generated. Due to limitations of the waveform generator associated with Model Sim additional logic to roduce a roer signal to test the system had to be designed. Utilizing the test vectors verified with MATLAB a waveform was generated and rocessed through the Xilin system. The result of the testing was that a dynamic range of 6 was achieved and theoretical and actual results matched. The net ste is to convert the Xilin design over to alication secific integrated circuit (ASIC) software for simulation with the folding analog ortion of the ADC. Once comleted this system will have far reaching alication to the DoD in Electronic Warfare Sensor Systems Unmanned Aerial Vehicle (UAV) and any other area where ower and size constraints are relevant. vi
I. INTRODUCTION A. FOLDING ANALOG TO DIGITAL CONVERTER BRIEF HISTORY Analog to Digital Converters (ADC) are integral arts of almost all communication and detection systems available today. These devices allow a smooth flow into the digital rocessing caabilities of today s high seed digital comuting from our analog surroundings to rocess information. Folding circuits added a new dimension to the ADC imlementation. The folding of the analog signal allows the reetitive use of comarators thereby reducing the die size and increasing the current that can be used for each comarator increasing the analog band-width.[] This significant attribute of lower ower consumtion and smaller die sace has led to research in this area for use in data collection with unmanned aerial vehicles (UAVs) and System on a Chi alications that are of increasing interest to the DoD. Currently most folding ADCs are using 64 comarators for an 8-bit resolution [] [9] []. There are some ADCs that use 6 comarators for the 8-bit resolution. However the error correction logic associated with this ielined imlementation creates an eorbitant amount of logic overhead [7]. The limitations of these current systems led to this thesis research. B. PRINCIPAL CONTRIBUTIONS In [] it was shown theoretically that a three channel folding ADC of fold moduli 4 and 5 could be designed using the Robust Symmetrical Number System (RSNS). In this thesis the equations develoed in [] were scrutinized and the general equations for a larger moduli three channel folding ADC were eanded. The moduli chosen for this thesis were 7 8 and 9. The equations resulting from this eansion were verified utilizing software analysis. Using the above moduli a seven bit ADC can be designed using only 4 comarators vice 64 which is the average number for an eight bit ADC [ ]. This
demonstrates the savings made ossible in using the RSNS folding ADC model for on chi designs for significantly more comlicated alications in terms of energy and sace savings due to comarator savings. The major contribution of the research contained in this thesis is two fold. First it shows verification of the general equations for a three channel RSNS folding ADC. Second it shows the testing of circuits designed using these equations and that they roduce the eected theoretical outut results. The first contribution was accomlished using MATLAB. The fist ste was to eand the equations given in [] then convert them into MATLAB synta for modeling and simulation. The major ortion of the work using MATLAB was creating the test vectors for the equations. Once the code was written and eecuted the result was a seven bit outut with a useful dynamic range of 6. The second contribution was accomlished using Xilin Project Navigator and Mentor Grahics Model Sim rograms. The first ste was to convert the equations utilized for the MATLAB ortion to NAND NOR INVERTER and XOR gates for imlementation in hardware. The rewritten equations were then imlemented using the schematic cature functionality of Xilin Project Navigator. As with the MATLAB code the harder ortion was creating the test signal for the system. Using the Mentor Grahic Model Sim rogram that has a symbiotic relationshi with the Xilin Project Navigator a test-bench waveform was created that roduced the eected results and that were eactly the same as the MATLAB results. The thesis work was carried out by first accomlishing the MATLAB verification so that significant resources would not be brought to bear on this subject unless the equations and analysis were verified. Once the MATLAB verification was comleted the schematic cature ortion was started. Due to the comleity and etensive amount of wiring the imlementation of the equations in logic took several months to comlete. Once the schematics of the RSNS-to-binary system were comleted a test-bench waveform needed to be created to test the system using Model Sim. Model Sim has a function generator for this urose; however it did not ossess the function needed to easily create the needed test-bench for this system. The available functions were
evaluated and a resetting counter function was chosen. Utilizing this function additional logic was designed to convert a resetting counter inut to the desired function needed for the RSNS-to-binary converter. The new logic was front loaded to the RSNS-to-binary logic and the aroriate waveform was rocessed through the system. The resulting data demonstrated the circuit functioned roerly. C. THESIS OUTLINE Chater II is a brief summary of the RSNS and is an eansion of the equations used for the main body of work in this thesis. This chater will be used to reassert the model in [] for the 4 and 5 moduli ADC. Along with the 4 and 5 moduli the general equations for each major comonent will be given and eanded to address moduli 7 8 and 9. This chater will delineate all the equations used for the following chaters for design of the RSNS-to-Binary conversion circuit. All equations in this chater and all following chaters will be Boolean eression using a binary numbering system unless otherwise secified. Table is a list of the most commonly used variables in this thesis. The bit order will use the highest number as the most significant bit (MSB) and zero as the least significant bits (LSB) as denoted by the bit order subscrit.
Variable Descrition Subscrit i Subscrit k m Modulus Channel Number i s ik Thermometer Code Inut from Channel Number Bit Order Comarators ik Position bit conversion Channel Number Bit Order n i Dynamic Range Filtered Outut Bit Order g Encoder Outut Bit Order i h System Outut Bit Order i Table. List of Variables Chater III will outline the rocess used to convert the equations develoed in Chater II from general Boolean equations into MATLAB code and the aroriate least roduct term equations for the Xilin Project Navigator schematic cature. The chater is broken into two major sections; the first is on the imlementation of the general equations from Chater II to MATLAB code and the second section the imlementation for the Xilin schematic cature. Each section breaks down the conversion by the major comonents for the RSNS-to-binary converter. Chater IV is a detailed descrition of how the testing of the system had to be set u in order to verify the roer functioning of the RSNS-to-binary conversion logic. The first section of this chater focuses on the develoment of the creation of inuts for the system. There are secific requirements laced on the inuts for the system and the second ortion of this chater ensures that these requirements are satisfied. 4
Chater V shows the combined results of the test vectors and waveforms created in Chater IV and the imlementing of them via the rogram and circuit design in Chater III. Chater VI wras u the conclusions of the work and future work to be accomlished. 5
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II. RSNS RESIDUE-TO-BINARY CONVERSION A. GENERAL BACKGROUND The Robust Symmetrical Number System (RSNS) utilizes modulo arithmetic to decomose an integer into one or more symmetrical residues. Unlike other numbering systems such as the Residue Numbering System (RNS) or Symmetrical Numbering System (SNS) the RSNS contains built-in redundancy to eliminate the need for etensive error correction []. In [] three methods for converting RSNS residues to binary were discussed and this thesis utilizes the third method in which an algorithmic aroach is used that is based on the underlying RNS structure of RSNS. B. APPLICATION TO ADC Information obtained for this chater follows the revious work in [] and utilizes the equations given therein to generate the equations for the basic design demonstrated in Chater III. This Chater attemts to summarize the information in [] and use that information to develo the equations for this thesis. The RSNS-to-binary ortion develoed in this thesis takes logical s and s from the oututs of a bank of 4 comarators at the end of an analog folding circuit. These comarator oututs are searated into channels of moduli 7 8 and 9 with the same number of comarator oututs as the moduli number for each channel. These comarator signals are the inut to the RSNS-to-binary conversion system and are labeled s with each channel labeled with m. The three channels are broken down as ij follows; m 7 s s s s s s s i = [ ] m 8 [ s s s s s s s s ] 6 5 4 [ ] 8 7 6 5 4 = and 7 6 5 4 m = 9 s s s s s s s s s reresenting the thermometer code for each channel. A block diagram of the thermometer code to binary conversion algorithm is shown in Figure. The dynamic range for the -channel system with air-wise relatively rime moduli is found using equation () from [4]. 7
With 5 = + + 7 () M RSNS m m m = 7 the maimum dynamic range for the m = 7 m = 8 and m = 9 system designed in this thesis is 5 M RSNS = ( 7 ) + ( 7) + 7 =. [ s... s ] 6 [ s... s ] 7 [ s... s ] 8 [... ] 6 [... ] 7 [... ] 8 [... ] 6 a a [... ] 7 a a [... ] 8 a a [... ] n n 4 [ g... g ] [ h 6... h ] Position Bit Even Residue Conditional Inversion Alignment Encoder Adder [ e e e ] MRSS [ MRSS MRSS ] Figure. Block Diagram of the Symmetrical Residue-to-Binary Converter. Position Bit Equations The Thermometer code inuts [ s6... s ] [ s7... s] and [ s8... s] are first converted to RSNS Position Bits. Position Bits are moduli deendent and are decomosed modulo residues of the Thermometer code inuts. Position Bits ma from the Thermometer code inuts in accordance with the moduli of the channel. [ s... s ] 6 [ s7... s] and [ s8... s] ma to [ 6... ] [ 7... ] and [ 8... ] for m = 7 m = 8 and m = 9. For m = m = 4 and m = 5 [ s... s ] [ s... s] and [ s4... s ] ma to [... ] [... ] and [ 4... ]. The following equations were taken from [] and used in the develoment of this thesis work. The following are the derived osition bit equations utilizing binary thermometer code inuts from the analog circuit for moduli three four and five: = s = s = s s () 8
for m = = s = s s = s = s s () for m = 4 = s = s s = s = s s 4 = s s 4 (4) for m = 5. Using truth tables and Boolean algebra the general forms of the above equations for even and odd moduli were shown to be: i i i i i i i i5 ( ) ( ) ( ) ( ) ( ) mi imi imi i mi i ( ) ( 4) ( ) mi imi imi i + imi imi imi = s = s s = s s = s s = s imi = s s = s s i4 i6 = s s i i4 = s s i i (5) for even moduli and 9
i i i i i i i i5 mi i mi i mi i + ( ) imi ( ) imi ( ) imi = s = s s = s s = s s = s im ( 4) im ( ) i ( ) imi = s s ( ) im ( ) imi = s s i4 i6 = s s i i4 = s s i i i i (6) mi for odd moduli. The term is defined as the greatest ositive integer less than or m i equal to i.e. if the result is.54 then.54 =. Equations (5) and (6) above were used to generate the signal bit maing to osition bits for the higher moduli used in this thesis. The equations are as follows: = s 5 5 = s s = s s = s = s s 4 4 6 = s s 5 4 = s s 6 (7) for m = 7 and
= s 5 5 7 4 6 = s s = s s = s s = s = s s 5 4 6 = s s 6 4 = s s 7 (8) for m = 8 and = s 5 5 7 4 7 = s s = s s = s s = s = s s 5 6 8 = s s 6 4 6 = s s 7 4 = s s 8 (9) for m = 9. An eamle of the above equations would be [ s6... s ] = [] would ma to [... ] = []. 6. Even Residue Flags After osition bit conversion the net ste is to determine if the Thermometer code inut to the three channels is even or odd. This is done in by counting the number of inut bits that are one for each of the Thermometer code channels and asserting the even signal if the number is even and not asserting the signal if the number is odd. That is for channel two ( m = 8) if the Thermometer code inut bits are [... ] [ ] s s = then the even residue flag for channel two would be asserted 7 since there are four ones in the thermometer code inut.
The equations for an even residue with m = m = 4 and m = from [] are shown in equation (). The e reresents an even bit flag and will be asserted when the channel is even with the subscrit designating the channel. 5 e = s + s s e = s + s s + s e = s + s s + s s 4 () In general the equations for even moduli () and for odd moduli () can be generated as e s s s s s s () 4 ( ) i = i + i i + i i + + im i e s s s s s s s () = + + 4 + + ( ) ( ) i i i i i i im i im i This thesis chose to use equations () and () to get the following equations for the even flags for m = m = 8 and m = 9. 7 e = s + s s + s s + s s 4 5 6 e = s + s s + s s + s s + s 4 5 6 7 e = s + s s + s s + s s + s s 4 5 6 7 8 () Following the eamle above for m = 8 e = would be asserted.. Modulus Residue Sub-Sequence Flags The Modulus Residue Sub-Sequence (MRSS) flags are used to determine if the osition bits of a channel( ij ) must have the bit order reversed. The discussion of this in [] elains how these flags effect the conditional bit reversal of channel two and three of the system. Equation (4) shows the general equations from [] with the subscrit N being the number of channels in the system.
MRSS = e e N MRSS = e e N MRSS = e e N MRSS = e e N N MRSS = e e N N (4) The three-channel circuit utilized in this thesis uses equation (4) to generate equation (5) which is used in the net section to erform the conditional inversion of the osition bits. MRSS = e e MRSS = e e MRSS = e e (5) For eamle for e = e = and e = MRSS = and MRSS = 4. Conditional Bit Reversal Conditional bit reversal of the osition bits is based on the MRSS s where each channel is reversed deending on a different MRSS flag. When a channel is reversed its bit order is reversed i.e. if the signal... 7 met the conditions to be inverted it would be transosed to 7 6.... In order to kee continuity of variable naming all osition bits after the conditional bit reversal will have a subscrit of a added to delineate them from the bits before the conditional bit reversal logic i.e. channel two osition bit labels would be changed to... a a 7a Channel one is never reversed. Channel two is bit reversed if MRSS is asserted. Channel three is reversed if MRSS is asserted. This can be accomlished with simle multileers. The logic and equations used for this will be shown in Chater III. For our -channel case MRSS is not used.
5. Alignment Logic The RSNS relies on least ositive solution (LPS) ositional alignment to align the congruence equations resulting from the incoming RSNS symmetrical residue vectors. It can be shown that the RNS residue osition bits for the m = m = and m = 5 4 system can be aligned using eight -inut NAND gates. Using -inut NAND gates the m = m = 8 and m = 9 system can accomlish the alignment using twenty-one 7 gates. Utilizing the code in the aendices of [] the start oint for the alignment logic is 4aa 6a. Equation (6) shows all twenty-one of the gate equations needed for the system. n = 4a a 6a n = 5a 4a 7a n = 6a 5a 8a n = a 6a a n = 4 a 7a a n = 5 a a a n = 6 a a a n = 7 4a a 4a n = 8 5a a 5a n = 9 6a 4a 6a n = a 5a 7a n = n a 6a 8a = a 7 a a n = a a a n = 4 4a a a n = 5 5a a a n = 6 6a a 4a n = 7 a 4a 5a n = 8 a 5a 6a n = 9 a 6a 7a n = a 7a 8a (6) 4
This range determination of n is the longest vector where the combinations of the ositions bits ja ka la does not have a reeated combination of j k and l. Within the dynamic range of the system only one NAND gate outut from equation (6) will be active at a time. This unique attribute of the RSNS-to-binary algorithm is where the usefulness of RSNS is realized. 6. Encoder The oututs from the alignment logic are encoded into a 5-bit outut because only one NAND gate is active at one time and can be encoded in binary in 5 bits. The equations for the encoding logic are not difficult and will not be included in this section. They are shown grahically in Chater III. 7. Adder The adder designed for this thesis follows the equation shown in Figure and is for the m = m = 4 and m = 5 system []. The RSNS-to-binary imlementation in this thesis is three-channels and uses the same basic equations. However the equations are eanded in this thesis so that the inuts to the adder are consistent with the 5-bit outut from the Encoder described in the revious section. This is shown in Figure. g g g g e MRSS MRSS g g g g e h h h h h h 5 4 + carry-in Figure. Adder imlementation for RSNS-to-binary for []. g g g g g e MRSS MRSS 4 g g g g g e 4 h h h h h h h 6 5 4 + carry-in Figure. Adder imlementation of RSNS-to-binary for this thesis. 5
The chater contained an elanation of the concet for the Symmetrical Residueto-binary conversion algorithm. This information will be the basis for the following chaters and will aid the rocess of designing the code and logic in the net chater. 6
III. LOGIC DESIGN FOR ROBUST SYMMETRICAL NUMBERING SYSTEM LOGIC BLOCK An overview of the RSNS circuit for rocessing the thermometer code roduced by the analog folding circuits is shown in Figure 4. The 6 major levels of logic were develoed from the theory and equations discussed in Chater II. Position Bit Even Residue Conditional Inversion Encoder MRSS Alignment Adder Figure 4. Hierarchical View of RSNS-to-binary converter A. MATLAB REALIZATION Programming the RSNS-to-binary logic equations in MATLAB for verification of the equations derived in Chater II was the net ste in develoing the m = 7 m = and m = 9 converter. This section walks through the basic algorithm to convert 8 the binary logic equations to MATLAB logical equations. The code develoed during this hase was based on the assumtion that the thermometer code or symmetrical 7
residues would be assed as a arameter to the system. Aendi B shows the code created by using the algorithm shown in the following sections. First the algorithm mas the inut to the roer variable naming for the system i.e. it takes the twenty-four binary inut bits and renames them [ S... S ] [... ] and [... ] 8 6 S S 7 S S. The twenty-four bits are then rocessed as described in the remainder of this section.. Thermometer Code to Position Bit Conversion Equations (7) (8) and (9) show the general Position Bit conversion equations for the RSNS-to-binary converter develoed in this thesis. Changing these equations from standard Boolean format to MATLAB synta we would get for eamle = ss maed to P=and(Snot(S)). Aly this maing to equations (7) (8) and (9) gives the osition bit conversion for m = 7 m = 8 and m = 9.. Even Residue Flags Equation () shows the secific Even Residue Flag equations. A simle maing to MATLAB synta from equation () would ma e = s + ss + ss4 + s5s6 to E=or(not(S)or(and(Snot(S))or(and(Snot(S4))and(S5not(S6))))). Alying this maing to the remainder of equation () gives the even residue flags for m = m = 8 and m = 9. 7. MRSS Equation (5) shows the MRSS flag generation. The MATLAB synta for MRSS = e e is MRSS=or(EE). Aly this synta to the remaining ortion of (5) gives the MRSS flags for m = 7 m = 8 and m = 9. 8
4. Conditional Bit Reversal Conditional bit reversal is accomlished by use of a multileer. Multileers are imlemented using an OR of the AND of a signal and its comliment with the two oututs i.e. Pa is either P7 or P deending on MRSS being asserted or not asserted resectively. The Boolean eression for this multileer ortion would be = MRSS + MRSS which is then converted and maed in MATLAB to a ( 7 ) Pa=or(and(P7MRSS)and(Pnot(MRSS))). Alying this logic to all the ositions bits of channel two and three generates the conditional bit reversal for m = 7 m = and m = 9. Figure 5 shows a -to- multileer where the outut is inut if 8 the control signal is asserted and inut otherwise. Control signal Inut Inut Outut Figure 5. -to- Multileer 5. Alignment Logic The theory resented in Chater II called for -inut NAND gates to be used in the alignment logic. However MATLAB does not have NAND commands. Therfore modifications to the system had to be made to the alignment logic to allow the use of an AND gate in the MATLAB code. This was accomlished by following which signal should be asserted and adjusting accordingly to allow roer use of MATLAB coding. Equation (6) shows all equations for the alignment by maing n = 4 6 to a a a n=(and (P4aand(PaP6a))); and continuing this for the rest of (6) we get the Alignment Logic ortion. 9
6. Encoder The Encoder eresses the subscrit number of the asserted AND gate and generates a five bit outut [g4gggg]. For eamle if n4 was the active AND gate then the outut of the encoder would be []. The equations utilized in Aendi B were derived from the truth table shown in Table. Each outut bit of the Encoder is the OR of all the logic s in the column below the resective outut designator in Table. For eamle if we look at g4 there are logic s at n6 n7 n8 n9 and n. If any of these gates are active then g4 will be asserted. Thus g4= n6+ n7+ n8+ n9+ n(where + reresents OR) which converts to MATLAB of g4=or(n6or(n7or(n8or(n9n)))). Following this we get the Encoder from Table. Active AND gate g4 g g g g n n n n n4 n5 n6 n7 n8 n9 n n n n n4 n5 n6 n7 n8 n9 n Table. Encoder Truth Table
7. Adder The adder is a standard 7 bit adder. Once the inuts are arranged according to Figure the equations for the adder can be roduced as shown in Aendi B. The outut is given by 7 matrices h h h h h4 h5 and h6. Since the binary outut is not easily verified using MATLAB lots a matri called decimal was created for easier visual verification of the outut and is the decimal conversion of the h6 to h binary outut. Verification and testing for this code will be discussed in Chaters IV and V. B. XILINX REALIZATION This section shows the schematics created in Xilin Project Navigator to create the RSNS-to-binary conversion logic. Xilin was chosen for this because it was a readily available rogram with schematic cature functions along with a good test-bench simulator for verification of roer circuit oeration. The equations used were modifications of those in Chater II. The only changes were the alication of DeMorgan s Theorem to those equations in order to redominantly use NAND NOR and INVERTER gates only. A few XORs were used for the adder and MRSS logic blocks. Note in the following schematic diagrams the labels are as in Xilin Project Navigator.. Thermometer Code to Position Bit Conversion and Even Residue Flags For m = 7 equation (7) and () are used and DeMorgan s Theorem was alied to get equation (7) and (8) and when drawn in Xilin results in Figure 6. = s 5 5 5 = s s = s + s = s s = s + s = s = s s = s + s 4 4 6 4 6 = s s = s + s 5 4 4 = s s = s + s 6 (7)
( )( )( ) e = s + s s + s s + s s = s s s s s s s (8) 4 5 6 4 5 6 Inut (:6) From Moduli 7 Folded Wave comarators P(:6) e Figure 6. Channel Position Bit and Even Bit Flag Schematic For m = 8 equation (8) and () are used and DeMorgan s Theorem alied to get equation (9) and () and when drawn in Xilin results in Figure 7. = s 5 5 5 7 5 7 4 6 = s s = s + s = s s = s + s = s s = s + s = s = s s = s + s 5 4 6 4 6 = s s = s + s 6 4 4 = s s = s + s 7 (9)
( )( )( ) e = s + s s + s s + s s + s = s s s s s s s s () 7 4 5 6 7 4 5 6 Inut (:7) From Moduli 8 Folded Wave comarators S(:7) e Figure 7. Channel Position Bit and Even Bit Flag Schematic For m = 9 equation (9) and () are used and DeMorgan s Theorem alied to get equation (9) and () and when drawn in Xilin results in Figure 8.
= s 5 5 5 7 5 7 4 7 = s s = s + s = s s = s + s = s s = s + s = s = s s = s + s 5 6 8 6 8 = s s = s + s 6 4 6 4 6 = s s = s + s 7 4 4 = s s = s + s 8 () ( )( )( )( ) e = s + s s + s s + s s + s s = s s s s s s s s s () 4 5 6 7 8 4 5 6 7 8 Inut (:8) From Moduli 9 Folded Wave comarators P(:8) Figure 8. Channel Position Bit and Even Bit Flag Schematic e. Modulus Residue Sub-Sequence Flags Equation (5) is used to get Figures 9 and. 4
Inut Inut e e Outut MRSS Figure 9. MRSS Xilin Schematic Inut Inut e e Outut MRSS Figure. MRSS Xilin Schematic. Conditional Bit Reversal Channel is never reversed. Therefore in Xilin P(6:) will be a single bus line to the net block of logic. Channel which is an 8-bit to 8-bit multileer with MRSS as the control signal is shown in Figure. Again this reverses the Position Bit order when MRSS is asserted. MRSS P (7:) Pa (7:) Figure. Channel Conditional Bit Reversal Schematic 5
Channel which is a 9-bit to 9-bit multileer with MRSS as the control signal as shown in Figure. Again this inverts the Position Bit order when MRSS is asserted. MRSS Pa(8:) P (8:) Figure. Channel Conditional Bit Reversal Schematic 4. Alignment Logic Figure is a direct maing of equation (6). The only modification is the insertion of inverters for roer functioning of the follow on encoder. 6
P(:6) Pa(:7) Pa(:8) N (:) Figure. Alignment Logic for Position Bits after Inversion 5. Encoder The comonent equations in Equation () are the logical binary eressions for a to 5 bit encoder. The circuit is shown in Figure 4. This simle logic is all that is required for this section because only one NAND in the Alignment Logic can be active in the Dynamic Range at one time. ( )( )( )( ) ( )( )( )( ) ( )( )( ) ( )( )( ) ( )( ) g = n + n + n n + n + n n + n n + n 5 7 9 5 7 9 g = n + n + n n + n + n n + n n + n 6 7 4 5 8 9 g = n + n + n n + n + n n + n + n 4 5 6 7 4 5 g = n + n + n n + n + n n + n 8 9 4 5 g = n + n + n n + n 4 6 7 8 9 () 7
N(:) g (:4) Figure 4. Binary to 5 Bit Encoder Schematic 6. Adder A standard adder design was selected for this thesis vice a carry-look-ahead adder since the logic involved in the design of the RSNS-to-binary logic will be faster than the analog circuit roviding the inuts. Figure 5 shows the adder circuit and Figure shows the roer bit alignment for the inuts. 8
A(:6) B(:5) Carry-in h (6:) Figure 5. 7 Bit Adder Schematic This chater has shown the imlementation of the theory and design of the revious chater. The net ste is to ensure the inuts to these systems meets the RSNS residue requirements of the Residue-to-Binary converter. 9
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IV. TEST DEVELOPMENT AND VERIFICATION A. THERMOMETER CODE DEVELOPMENT The inuts for the RSNS-to Binary logic must be the three thermometer codes for each channel having RSNS Gray code roerties for all 4 inuts. Table demonstrates a small section of the thermometer code for m = 7 and shows that higher-order bits can only be asserted as after all the less significant bits are asserted to. The bits fill and ebb in bit order from lower to higher without skiing any bits. The thermometer code roerty is resent in all three RSNS channels. Bit number t = t = t = t = 4 t = 5 t = 6 t = 7 t = 8 P6 P5 P4 P P P P Table. Channel Thermometer Code Gray code sequences only change binary bit in the code grou when going from one samle eriod to the net [5]. Table 4 shows the Gray code scheme used for the RSNS-to-Binary logic. The number in the channel rows are the number of s asserted for that channel. As shown in Table 4 only one bit in all channels changes at any time samling. In terms of the circuit this means only one of twenty-four comarator inuts change at any one samle time. Another fact demonstrated in Table 4 is that each
channel will hold a value for three samle eriods before changing. This is to assist in ensuring the Gray code roerty of the inuts. Channel t= t= t= t=4 t=5 t=6 t=7 t=8 6 6 6 5 5 5 4 4 6 6 7 7 7 8 8 8 6 5 5 5 4 4 4 Table 4. RSNS Gray Code Proerty Showing the Number of Comarators for each channel Another roerty of the inuts is that the channels are time shifted. Channels two and three are shifted left one and two samle eriods resectively as is shown in Table 4. This is critical to the conversion rocess and assists in the Gray code functionality of the system. The develoment of the thermometer code for testing both the MATLAB code and the Xilin Project Navigator schematic turned out to be much more difficult than initially eected because of these unique inut requirements. The following section will elaborate on how this was accomlished for the testing and ultimate verification of the RSNS-to-binary algorithm.. MATLAB Creating a thermometer code with Gray code roerties in MATLAB was a tedious task. The first task was to create twenty-four matrices to reresent the twentyfour inuts from the comarators. To accomlish this the matrices were sorted by channel that is utilizing the fact that there are seven matrices in channel matrices reresenting channel m = 9 m = 7 eight m = 8 and nine matrices reresenting channel. Each channel holds a signal for three samling eriods. One full cycle of the thermometer code would be from to down to i.e. with m =7 one full cycle mi would be[ 4 5 6 7 6 5 4 ]. With the samle hold and thermometer
code roerties alied it can be seen that the size of a matri for a RSNS moduli is (mi ). Alying this equation to moduli m = 7 m = 8 and m = it is found that the matrices for the channels are 4 48 and 54 resectfully. Utilizing these numbers the MATLAB code in Aendi A generates matrices for each comarator outut of the aroriate length for one full thermometer cycle and include the aroriate shifts for channels two and three. 9 The net ste is to make all the matrices equal size in order to cover all ossible combinations of the shifted channels. This was accomlished by using iterative for loos to eand the matrices. Equation (4) was used to establish the number of coies of each matri that must be concatenated together in order facilitate roer alignment. m [(m )*(m )] m [(m ) *(m )] m [(m )*( m )] (4) Once the first two sections of MATLAB code in Aendi A are eecuted twenty-four matrices of equal length and encomassing all combinations of alignment are roduced and ready to be assed to the code in Aendi B for rocessing.. Field Programmable Gate Array Schematic Cature Xilin test-bench software does not have a thermometer code roduction function but it does have a resetting counter. The resetting counter will not roduce the sequence [ ] but will roduce [ ]. Therefore to get thermometer code inuts for the system some digital logic to convert the resetting counter to a thermometer code had to be designed. The oututs of reset counters are the binary equivalent of the decimal value and the inut to the thermometer code generators described in the following aragrahs and tables. As an eamle Table 5 shows the inuts to the thermometer code generator for m = 7 as [I I I I]. Table 5 shows a truth table for channel. The information in Table 5 is then ut into Karnaugh mas for bits S thru S6 as shown in Figures 6 7 8 and 9. These
Karnaugh mas roduce the least sum equations shown in Equation(5). These equations were then utilized to imlement the channel thermometer code generator in Xilin as shown in Figure. 4 5 9 6 8 7 7 6 6 5 5 4 4 S S S S S4 S5 S6 I I I I Therm Decimal 4 5 9 6 8 7 7 6 6 5 5 4 4 S S S S S4 S5 S6 I I I I Therm Decimal Table 5. Channel ( 7 m = ) Waveform Truth Table 4 II II S II II S II II S II II S Figure 6. Karnaugh mas for Channel ( 7 m = )Thermometer code bits S and S
S S II II II II Figure 7. Karnaugh mas for Channel ( m = 7 )Thermometer code bits S and S S4 II II S5 II II Figure 8. Karnaugh mas for Channel ( m = 7 ) Thermometer code bits S4 and S5 S6 II II Figure 9. Karnaugh ma for Channel ( m = 7 ) Thermometer code bit S6 5
s = I + I + I + I = I + I + I + I = + + + = ( )( )( ) = + + = ( )( )( ) = + + = ( )( )( ) = + + = ( )( )( ) = + = ( )( I ) s I I I I I I I I I I I I I I s I I I I I I I I I I I I s I I I I I I I I I I I I I I I I s II III III II III III 4 s I I I I I I I I I I I 5 s = I I I = I + I + I 6 (5) Inut (:) From Xilin Resetting Counter S(:6) Figure. Thermometer Code 7-Bit Generator Table 6 shows a truth table for channel ( m = 8). The information in Table 6 is then ut into Karnaugh ma for bits S thru S7 as seen in Figures and 4. These Karnaugh mas roduce the least sum equations shown in Equation(6). These 6
equations were then utilized to imlement the channel ( 8 m = ) thermometer code generator in Xilin as shown in Figure 5. 5 4 9 8 7 6 5 4 S S S S S4 S5 S6 S7 I I I I Therm Decimal 5 4 9 8 7 6 5 4 S S S S S4 S5 S6 S7 I I I I Therm Decimal Table 6. Channel ( 8 m = ) Waveform Truth Table S 7 II II II II S II II S II II S Figure. Karnaugh mas for Channel ( 8 m = ) Thermometer code bits S and S
S S II II II II Figure. Karnaugh mas for Channel ( m = 8) Thermometer code bits S and S S4 II II S5 II II Figure. Karnaugh mas for Channel ( m = 8) Thermometer code bits S4 and S5 S6 II II S7 II II Figure 4. Karnaugh mas for Channel ( m = 8) Thermometer code bits S6 and S7 8
s = I + I + I + I = I + I + I + I = + + + = ( )( )( )( ) = + + + = ( )( )( )( ) = + + = ( )( )( ) = + + = ( )( )( ) = + I+ III = ( III)( III)( III) = + = ( )( ) s I I I I I I I I I I I I I I I I s II II III II II II III II s II II III II II III s I I I I I I I I I I I I I I I I 4 s I I I I I 5 s I I I I I I I I I I I I I I 6 s = I I I I = I + I + I + I 7 (6) Inut (:) From Xilin Resetting Counter Figure 5. Thermometer Code 8 Bit Generator S(:7) Table 7 shows a truth table for channel ( m = 9 ). The information in Table 7 is then ut into Karnaugh mas for bits S thru S8 as shown in Figures 6 7 8 9 and 4. These Karnaugh mas roduce the least sum equations shown in Equation (7). These equations were then utilized to imlement the channel thermometer code generator in Xilin as shown in Figure 5. 9
7 6 5 4 4 5 6 7 8 9 9 8 8 7 7 6 6 5 5 4 4 S S S S S4 S5 S6 S7 S8 I I I I I4 Therm Decimal 7 6 5 4 4 5 6 7 8 9 9 8 8 7 7 6 6 5 5 4 4 S S S S S4 S5 S6 S7 S8 I I I I I4 Therm Decimal Table 7. Channel ( 9 m = ) Waveform Truth Table II II S II II I4= I4= II II II II S II II II II I4= I4= Figure 6. Karnaugh ma for Channel ( 9 m = ) Thermometer code bit S 4
S I4= I4= II II II II Figure 7. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S S I4= I4= II II II II Figure 8. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S S I4= I4= II II II II Figure 9. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S 4
S4 I4= I4= II II II II Figure. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S4 S5 I4= I4= II II II II Figure. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S5 S6 I4= I4= II II II II Figure. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S6 4
S7 I4= I4= II II II II Figure. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S7 S8 I4= I4= II II II II Figure 4. Karnaugh ma for Channel ( m = 9 ) Thermometer code bit S8 4
( )( ) ( )( ) ( )( ) s = I + I + I + I + I = I + I + I I + I 4 4 s = I I + I + I + I = I I I + I + I 4 4 s = I + I + I I = I + I I I = + + + = ( )( )( )( ) = + + + = ( )( )( )( ) = + + = ( )( III )( III ) = + = ( )( ) = + = ( )( ) s I I I I I I I I I I I I I I I I s I I I I I I I I I I I I I I I I I I I I 4 s I I I I I I I I I I 5 s IIII II IIII II 6 s I I I I I I I I I I I I 7 s = I I I I = I + I + I + I 8 (7) Inut (4:) From Xilin Resetting Counter Figure 5. Thermometer Code 9 Bit Generator S(:8) These logic blocks will enable the roduction of a test-bench waveform that will allow the testing of the logic designed in Chater III. 44
B. THERMOMETER CODE VERIFICATION The net ste is to verify the thermometer code with Gray code roerties was actually generated using the methods described in Section A. Without roer inuts the functioning of the symmetrical residue thermometer code-to-binary conversion circuit cannot be verified to be oerating correctly.. MATLAB Figure 6 is the grah of the oututs of the MATLAB code in Aendi A sorted by channel. As shown Channel goes from to 7 Channel goes from to 8 and Channel goes from to 9 showing that each channel has its individual thermometer code roerties. Figure 6 also shows the Gray code and shifting roerties that are required for the inuts of the system. The figure also shows that in any one samling eriod the signal of only one channel changes.. The left shift of one and two for Channels and resectively can be seen if we look at Channel being the base. In this case Channel changes one cycle before and Channel changes cycles before Channel. Channel Comarators Triggered 5 5 5 5 5 4 45 5 55 Samle Perio ods Channel Transition at t= 5 5 5 5 5 4 45 5 55 Samle Periods Channel Transition at t=- 5 5 5 5 5 4 45 5 55 Samle Periods Transition at t=- Figure 6. MATLAB Thermometer Code samle 45