Power MOSFET PRODUCT SUMMARY (V) 100 R DS(on) ( ) = 0.7 Q g (Max.) (nc) 16 Q gs (nc) 4.4 Q gd (nc) 7.7 Configuration Single TO0AB G DS ORDERING INFORMATION Package Lead (Pb)free SnPb G D S NChannel MOSFET FEATURES Dynamic dv/dt Rating Repetitive Avalanche Rated 175 C Operating Temperature Fast Switching Ease of Paralleling Simple Drive Requirements Compliant to RoHS Directive 00/95/EC Available RoHS* COMPLIANT DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low onresistance and costeffectiveness. The TO0AB package is universally preferred for all commercialindustrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO0AB contribute to its wide acceptance throughout the industry. TO0AB IRF50PbF SiHF50E3 IRF50 SiHF50 ABSOLUTE MAXIMUM RATINGS (T C = 5 C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 100 V GateSource Voltage ± 0 Continuous Drain Current at T C = 5 C 9. I D T C = 100 C 6.5 A Pulsed Drain Current a I DM 37 Linear Derating Factor 0.40 W/ C Single Pulse Avalanche Energy b E AS 00 mj Repetitive Avalanche Current a I AR 9. A Repetitive Avalanche Energy a E AR 6.0 mj Maximum Power Dissipation T C = 5 C P D 60 W Peak Diode Recovery dv/dt c dv/dt 5.5 V/ns Operating Junction and Storage Temperature Range T J, T stg 55 to 175 Soldering Recommendations (Peak Temperature) for 10 s 300 d C Mounting Torque 63 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. V DD = 5 V, starting T J = 5 C, L = 3.5 mh, R g = 5, I AS = 9. A (see fig. 1). c. I SD 9. A, di/dt 110 A/μs, V DD, T J 175 C. d. 1.6 mm from case. 10 lbf in 1.1 N m * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91017 www.vishay.com S110511Rev. B, 1Mar11 1
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 6 CasetoSink, Flat, Greased Surface R thcs 0.50 C/W Maximum JunctiontoCase (Drain) R thjc.5 SPECIFICATIONS (T J = 5 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage = 0 V, I D = 50 μa 100 V Temperature Coefficient /T J Reference to 5 C, I D = 1 ma 0.13 V/ C GateSource Threshold Voltage (th) =, I D = 50 μa.0 4.0 V GateSource Leakage I GSS = ± 0 V ± 100 na = 100 V, = 0 V 5 Zero Gate Voltage Drain Current I DSS = 80 V, = 0 V, T J = 150 C 50 μa DrainSource OnState Resistance R DS(on) = I D = 5.5 A b 0.7 Forward Transconductance g fs = 50 V, I D = 5.5 A b.7 S Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance C iss C oss C rss = 0 V, = 5 V, f = 1.0 MHz, see fig. 5 360 150 34 Total Gate Charge Q g 16 I D = 9. A, = 80 V, GateSource Charge Q gs = 4.4 see fig. 6 and 13 b GateDrain Charge Q gd 7.7 TurnOn Delay Time t d(on) 8.8 Rise Time t r V DD = 50 V, I D = 9. A, 30 TurnOff Delay Time t d(off) R g = 18, R D = 5., see fig. 10 b 19 Fall Time t f 0 Between lead, Internal Drain Inductance L D 6 mm (0.5") from 4.5 D package and center of G Internal Source Inductance L S die contact 7.5 S DrainSource Body Diode Characteristics MOSFET symbol D Continuous SourceDrain Diode Current I S 9. showing the G integral reverse Pulsed Diode Forward Current a I SM S 37 p n junction diode A Body Diode Voltage V SD T J = 5 C, I S = 9. A, = 0 V b 1.8 V Body Diode Reverse Recovery Time t rr T J = 5 C, I F = 9. A, di/dt = 100 A/μs b 110 60 ns Body Diode Reverse Recovery Charge Q rr 0.53 1.3 μc Forward TurnOn Time t on Intrinsic turnon time is negligible (turnon is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle %. pf nc ns nh www.vishay.com Document Number: 91017 S110511Rev. B, 1Mar11
TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) 10 1 10 0 Top 15 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 4.5 V 10 1 10 0 5 C 175 C 0 µs Pulse Width T C = 5 C 0 µs Pulse Width = 50 V 10 1 10 0 10 1 4 5 6 7 8 9 10 91017_01, DraintoSource Voltage (V) 91017_03, GatetoSource Voltage (V) Fig. 1 Typical Output Characteristics, T C = 5 C Fig. 3 Typical Transfer Characteristics 91017_0 10 1 10 0 Top Bottom 15 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V 10 1 10 0 10 1, DraintoSource Voltage (V) 4.5 V 0 µs Pulse Width T C = 175 C R DS(on), DraintoSource On Resistance (Normalized) 91017_04 3.0.5.0 1.5 1.0 0.5 I D = 9. A = 0.0 60 40 0 0 0 40 60 80 100 10 140 160 180 T J, Junction Temperature ( C) Fig. Typical Output Characteristics, T C = 175 C Fig. 4 Normalized OnResistance vs. Temperature Document Number: 91017 www.vishay.com S110511Rev. B, 1Mar11 3
Capacitance (pf) 91017_05 750 600 450 300 150 0 10 0 10 1 = 0 V, f = 1 MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd C iss C oss C rss, DraintoSource Voltage (V) I SD, Reverse Drain Current (A) 91017_07 10 1 175 C 5 C 10 0 10 1 = 0 V 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1. V SD, SourcetoDrain Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage Fig. 7 Typical SourceDrain Diode Forward Voltage, GatetoSource Voltage (V) 91017_06 0 16 1 8 4 I D = 9. A = 0 V = 50 V = 80 V For test circuit see figure 13 0 0 4 8 1 16 0 Q G, Total Gate Charge (nc) 91017_08 10 3 5 Operation in this area limited by R DS(on) 10 5 10 µs 10 5 1 5 0.1 0.1 100 µs 1 ms 10 ms T C = 5 C T J = 175 C Single Pulse 5 1 10 5 10 5 10 3, DraintoSource Voltage (V) 5 Fig. 6 Typical Gate Charge vs. GatetoSource Voltage Fig. 8 Maximum Safe Operating Area www.vishay.com Document Number: 91017 4 S110511Rev. B, 1Mar11
10 8 6 4 R G Pulse width 1 µs Duty factor 0.1 % R D D.U.T. V DD Fig. 10a Switching Time Test Circuit 91017_09 0 5 50 75 100 15 150 175 T C, Case Temperature ( C) 90 % 10 % t d(on) t r t d(off) t f Fig. 9 Maximum Drain Current vs. Case Temperature Fig. 10b Switching Time Waveforms 10 Thermal Response (Z thjc ) 1 0.1 0 0.5 0. 0.1 0.05 0.0 0.01 Single Pulse (Thermal Response) 10 10 5 10 4 10 3 10 0.1 1 10 P DM t 1 t Notes: 1. Duty Factor, D = t 1 /t. Peak T j = P DM x Z thjc T C 91017_11 t 1, Rectangular Pulse Duration (s) Fig. 11 Maximum Effective Transient Thermal Impedance, JunctiontoCase Document Number: 91017 www.vishay.com S110511Rev. B, 1Mar11 5
L Vary t p to obtain required I AS t p V DD R G D.U.T I AS V DD A t p 0.01 Ω I AS Fig. 1a Unclamped Inductive Test Circuit Fig. 1b Unclamped Inductive Waveforms E AS, Single Pulse Energy (mj) 91017_1c 600 500 400 300 00 100 Top Bottom V DD = 5 V 0 5 50 75 100 15 150 I D 3.8 A 6.5 A 9. A Starting T J, Junction Temperature ( C) 175 Fig. 1c Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. Q G 1 V 0. µf 50 kω 0.3 µf Q GS Q GD D.U.T. V DS V G Charge Fig. 13a Basic Gate Charge Waveform 3 ma Fig. 13b Gate Charge Test Circuit I G I D Current sampling resistors www.vishay.com Document Number: 91017 6 S110511Rev. B, 1Mar11
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period = a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. = 5 V for logic level devices Fig. 14 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91017. Document Number: 91017 www.vishay.com S110511Rev. B, 1Mar11 7
www.vishay.com Package Information TO01 D L H(1) Q L(1) 1 E e 3 b M * b(1) Ø P C A F MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. A 4.14 4.70 0.163 0.185 b 0.69 1.0 0.07 0.040 b(1) 1.14 1.73 0.045 0.068 c 0.36 0.61 0.014 0.04 D 14.33 15.85 0.564 0.64 E 9.96 10.5 0.39 0.414 e.41.67 0.095 0.105 e(1) 4.88 5.8 0.19 0.08 F 0.43 1.40 0.017 0.055 H(1) 6.10 6.48 0.40 0.55 J(1).41.9 0.095 0.115 L 13.36 14.40 0.56 0.567 L(1) 3.33 4.04 0.131 0.159 Ø P 3.53 3.94 0.139 0.155 Q.59 3.00 0.10 0.118 ECN: X150003Rev. A, 19Jan15 DWG: 6031 Notes M* = 0.05 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM Outline conforms to JEDEC outline TO0AB with exception of dimension F e(1) J(1) Revison: 19Jan15 1 Document Number: 6654 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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