P5 Evolution: Pentium MMX

Transcription

1 P5 Evolution: Pentium MMX Pentium P5 with MMX Extensions Introduced: 01/1997 Data bus: 64bit Address bus: 32bit Vcc: 1.8V-2.8V MHz L1-caches: 16kB code and data (write-back). 4- way set associative. 4.5M transistors. 0.25/0.35 m BiCMOS. 321-pin socket 7 Bilg. Donanım 2008 Bilg. Tek. ve Prog. 1

2 P5 Evolution: Pentium MMX MMX MMX = Multi-media Extensions To meet growing importance and increasing demands of multimedia and communication applications 57 new instructions New instructions designed specifically to handle video and audio data SIMD = Single Instruction Multiple Data One instruction performs the same function on many pieces of data MMX is pipelined Bilg. Donanım 2008 Bilg. Tek. ve Prog. 2

3 6 th Gen. Processor: P6 P6 Processor Variations: Pentium Pro Original P6 processor. L2 cache: 256kB, 512kB or 1MB (full-core speed) Pentium II P6 with L2-cache: 512kB (half-core speed) Pentium II Xeon P6 with L2-cache: 512kB/1MB/2MB (full-core speed) Celeron P6 without L2 cache Celeron-A P6 with L2-cache: 128kB on-die (full-core speed) Pentium III P6 with SSE (MMX2), L2-cache: 256kB on-die (half-core speed) Pentium III Xeon P6 with SSE (MMX2), L2-cache: 512kB/1MB/2MB on-die (full-core speed) Bilg. Donanım 2008 Bilg. Tek. ve Prog. 3

4 P6: New Features... Dual Independent Bus (DIB): Two Separate Data Buses: One system bus (motherboard ) One cache bus Also called: back-side bus to the processor Advantage: Speed of the cache is scalable to the processor. In contrast: P5 Cache-speed = motherboard-speed. P6 processors: >1GHz Bilg. Donanım 2008 Bilg. Tek. ve Prog. 4

5 P6: Pentium Pro Introduced: 11/1995 (before P5 MMX) Outstanding feature: Integrated L2 cache 2 silicon dies: Processor & L2 cache (256kB, 512kB, 1MB) 5.5M + 63M = 68M transistors Bilg. Donanım 2008 Bilg. Tek. ve Prog. 5

6 P6: Pentium II Introduced: 05/1997 Abandoned: chip-in-a-socket Introduced: 242-pin SEC cartridge Much less expensive to manufacture Bilg. Donanım 2008 Bilg. Tek. ve Prog. 6

7 P6: Pentium II Processor core speeds: MHz Bus speeds: MHz 7.5M transistors. 0.25/0.35 m BiCMOS. MMX Power dissipation up to >40W! Heatsinks and fans required! Address-bus: 36bit Addressable: 64GB L2 cache Half core-speed. Supports up to 512MB Bilg. Donanım 2008 Bilg. Tek. ve Prog. 7

8 P6: Celeron L2 cache support up to 4GB of RAM MMX L1 cache: 2* 16kB Integral thermal diode for temperature monitoring 0.25/0.18 m technology Bilg. Donanım 2008 Bilg. Tek. ve Prog. 8

9 P6: Pentium III Introduced: 02/ M transistors 0.18 m coppermine technology Major improvements: SSE (Streaming SIMD Extensions) Integrated on-die L2 cache Available up to 1GHz Bilg. Donanım 2008 Bilg. Tek. ve Prog. 9

10 7 th Gen. Processor: Pentium 4 Introduced: 11/2000. Also called NetBurst Main technical details: Core speed range 1.3GHz..3GHz? 42M transistors m. System (front-side) bus: up to 400MHz ALU runs at twice the processor core frequency Hyper-pipelined 20-stage technology Very deep out-of-order instruction execution 20kB L1 cache. 256kB full-speed L2-cache. 8-way set associative. L2 supports up to 4GB RAM and ECC. SSE2 144 new SSE2 instructions Bilg. Donanım 2008 Bilg. Tek. ve Prog. 10

11 Bilg. Donanım 2008 Bilg. Tek. ve Prog. 11

20 Paketlenmiş L2 Ön_bellek Komut Ön belleği Sonraki_IP Veriyolu Bağdaştırma Birimi Sıralı işlem Algetir BTB L1 Komut Ön_belleği Algetir yükle L1 Veri Ön_belleği sakla Kod Çözme Birimi X3 MIS Sıralı işlem Algetir/ Kod çözme Birimi Sevketme/ İcra Birimi İnziva Birimi RAT Komut Havuzu (ROB) Bilg. Donanım 2008 Bilg. Tek. ve Prog. 20

22 With a single processor system, the processor can normally read a single instruction into the execution core per clock cycle. However, many instructions take more than a single clock cycle to execute due to something called memory latency, for example a load instruction must read data from memory which can take many clock cycles to arrive at the processor. The result is that a lot of time the processor is idle. Bilg. Donanım 2008 Bilg. Tek. ve Prog. 22

23 Hyper-threading is an Intel technology that enables the processor to execute alternative instructions when it would normally be idle. It is still a single processor but the processor presents itself as two logical processors to allow the operating system to schedule separate threads of instructions for execution on each logical processor. Bilg. Donanım 2008 Bilg. Tek. ve Prog. 23

24 A multi-core processor also presents itself as two logical processors to the operating system. However, this time there really are two execution cores on the processor. These two cores can execute separate threads of instructions in a truly simultaneous fashion but they are located on a single processor die and therefore use up less space. Unlike a situation where there are two processors in a system, the two execution cores share the some of the same cache which can be very helpful if the two threads of execution are executing the same instructions and if they are working on the same set of data. Bilg. Donanım 2008 Bilg. Tek. ve Prog. 24

25 A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores (normally a CPU) into a single package composed of a single integrated circuit (IC), called a die, or more dies packaged together. A dual-core processor contains two cores, and a quadcore processor contains four cores. A multi-core microprocessor implements multiprocessing in a single physical package. Bilg. Donanım 2008 Bilg. Tek. ve Prog. 25

26 Chipset İşlemci türünü belirler RAMtürünü ve kapasitesini belirler Anakartın desteklediği takılabilecek iç ve dış aygıtları belirler CPU, RAM veg/çaygıtları arasında elektronik ara yüz olarak görev yapar Bilg. Donanım 2008 Bilg. Tek. ve Prog. 26

29 Northbridge CPU RAM arasındaki iletişimi sağlamaktadır. Yeni AMD sistemlerinde video için de kullanılmaktadır. Southbridge Ek aygıtlar ve depolama aygıtlar Genişleme yuvaları, EIDE ve FDD controller I/O Controller Hub,ICH5(G/Ç Denetim Merkezi) yada peripheral bus controller(dış veri yolu denetleyici) Bilg. Donanım 2008 Bilg. Tek. ve Prog. 29

33 Intel based mainboard Northbridge için Memory controller hub,mch(bellek Denetim Merkezi), Southbridge için I/O controller hub, ICH, (G/Ç Denetim Merkezi) Bilg. Donanım 2008 Bilg. Tek. ve Prog. 33

34 There are several suppliers of chip sets for the motherboard: Intel SIS Opti Via ALi Triton first and second The interest in chip sets and their performance started in late 1995, when the Pentium processor became more popular. The Triton controllers were the first chip sets in this trend. Bilg. Donanım 2008 Bilg. Tek. ve Prog. 34

35 82430FX from late 1995 was Intel's next chip set and the first Triton. In February 1996 the second generation of Triton arrived. Two new chip sets were introduced: The 82430VX and 82430HX. The last (HX) was the fastest one. VX and HX The two sets were similar, yet different. 430HX consisted of two chips. It was designed for the more professional PCs. 430VX consisted of four chips, but the cost was slightly lower than HX. It was aimed at the home use PC market. Chip set 82430HX 82430VX Contents 82439HX System Controller (TXC) SB PCI ISA IDE Accelerator 82437VX System Controller (TVX) + two 82438VX Data Path Units (TDX) SB PCI ISA IDE Accelerator Bilg. Donanım 2008 Bilg. Tek. ve Prog. 35

36 Intel TX chip set The last chip set to Pentium processors were named 82430TX, which supports two new hot technologies: SD-RAM Ultra DMA TX firstly supports SD RAM and Ultra DMA hard disks. Two important technologies. But the TX-set cannot cache above 64 MB RAM. Bilg. Donanım 2008 Bilg. Tek. ve Prog. 36

37 VIA Apollo MVP3 This chip set for Socket 7 motherboards promises very good performance with its 100 MHz bus connecting the CPU with the L2 cache and possible PC100 SDRAM. Other features include: AGP graphics Supports up to 1 GB RAM in 64 Mbit FPM/EDO/SDRAM/PC100 modules 2 MB L2 cache support Virtual Clock Synchronization (VCS) for optimal timing. Bilg. Donanım 2008 Bilg. Tek. ve Prog. 37

38 Ali Aladdin 5 This Aladdin V chip set is for modern Socket 7 CPUs like AMD K6-2 running up to 350 MHz with a 100 MHz system bus. It consists of two chips, a north and a south bridge. There features are: M1541(AGP, CPU-to-PCI Bridge, Memory Cache & Buffer Controller) Interface for all socket 7 compatible processors High performance FPM/EDO/SDRAM DRAM controller 2-channel dedicated Ultra-33 IDE Master controller 2-port USB controller, SMBus controller, PS/2 Keyboard/Mouse controller Super I/O (Floppy Disk Controller, 2 serial port/1 parallel port) support. Two full function universal asynchronous receiver/ transmitters (UARTs), a flexible high performance internal data separator with send/receive 16 byte FIFOs. Serial Infra Red for wireless communications with other devices. Swap drives A & B. SPP, PS/2, EPP and ECP parallel port. 328-pin BGA Bilg. Donanım 2008 Bilg. Tek. ve Prog. 38

39 82450GX This chip set came out in 1995, It is supporting quad CPU configurations. That is PCs with 4 Pentium Pros FX - Natoma This was for a long time Intel's most widely used chip set for 6th. generation CPUs. This chip set can handle 2 CPUs on the same motherboard. 440FX consists of four controllers. Common for these chip sets is the 82371SB PCI-ISA accelerator, which provides good performance on the I/O Bilg. Donanım 2008 Bilg. Tek. ve Prog. 39

40 Intel 810 A new type of memory controller with built-in graphics technology. Support for up to 512 MB SDRAM. Built-in audio-codec controller. No ISA bus! Graphics Memory Controller Hub Integrated Controller Hub Firmware Hub Bilg. Donanım 2008 Bilg. Tek. ve Prog. 40

41 Graphics Memory Controller Hub The Graphics Memory Controller Hub (GMCH) is a MCH "north bridge" including a graphics controller and using Direct AGP (integrated AGP, where the graphics controller is directly connected to the system RAM) operating at 100 MHz I/O Controller Hub This "south bridge", the (ICH), employs an accelerated hub to give a direct connection from the graphics and memory to the integrated AC97 (Audio-Codec) controller, the IDE controllers, the dual USB ports, and the PCI bus. This promises increased I/O performance Firmware Hub (FWH) The Firmware Hub (FWH) stores system BIOS and video BIOS in a 4 Mbit EEPROM. AC97 The Integrated Audio-Codec 97 controller enables software audio and modem by using the processor to run sound and modem software. Bilg. Donanım 2008 Bilg. Tek. ve Prog. 41

42 820e In June 2000 Intel's revamped i820e chipset started shipping. Featuring a brand new ICH2 I/O controller hub (i82801ba), the new chip set holds: Four USB ports using dual controllers Integrated LAN controller Dual Ultra ATA/100 IDE controllers Dolby surround-capable six-channel audio. Bilg. Donanım 2008 Bilg. Tek. ve Prog. 42

47 Referanslar: Butler, T., 2004, Pentium Generations: A History and Technical Overview of Intel s Pentium Processors Bilg. Donanım 2008 Bilg. Tek. ve Prog. 47