Airbus Defence and Space. On-board digital electronics and software emerging technologies in space applications ETFA 2015, September 8 th, Luxembourg

Transcription

1 On-board digital electronics and software emerging technologies in space applications ETFA 2015, September 8 th, Luxembourg

2 Outline Introduction Spacecraft systems Applications Specific constraints Architecture Space systems on-board digital electronics and software State of the art technologies for processors and data-links Future needs and technology development strategy On-board processing Technology trends 2/50

3 Spacecraft systems applications Satellites Earth Observation Science Telecommunications Navigation Pleiades AIRBUS Defence and Space 3/50

4 Spacecraft systems applications Satellites Earth Observation Science Telecommunications Navigation Gaia AIRBUS Defence and Space 4/50

5 Spacecraft systems applications Satellites Earth Observation Science Telecommunications Navigation Alphasat I-XL communications satellite AIRBUS Defence and Space 5/50

6 Spacecraft systems applications Satellites Earth Observation Science Telecommunications Navigation Space exploration Cruise vehicles Specific manoeuvers Surface exploration (rovers) Bepi Colombo release at Mercury AIRBUS Defence and Space 6/50

7 Spacecraft systems applications Satellites Earth Observation Science Telecommunications Navigation Space exploration Cruise vehicles Specific manoeuvers Surface exploration (rovers) EXOMARS rover ESA 7/50

8 Spacecraft systems applications Satellites Earth Observation Science Telecommunications Navigation Space exploration Cruise vehicles Specific manoeuvers Surface exploration (rovers) Space Transportation Orbit service vehicles Manned Flight Launchers International Space Station and ATV-2 Johannes Kepler NASA 8/50

9 Spacecraft systems applications Satellites Earth Observation Science Telecommunications Navigation Space exploration Cruise vehicles Specific manoeuvers Surface exploration (rovers) Space Transportation Orbit service vehicles Manned Flight Launchers Ariane 5 launch of EUTELSAT 21B & STAR ONE C3 CNES ESA-CNES-ARIANESPACE 9/50

10 Spacecraft systems Satellites Earth Observation Science Telecommunications Navigation Space exploration Cruise vehicles Specific manoeuvers Surface exploration (rovers) Space Transportation Orbit service vehicles Manned Flight Launchers Various space systems Comet 67P/Churyumov-Gerasimenko on 3 August 2014 from a distance of 285 km. CNES ESA/Rosetta/MPS Common technology solutions 10/50

11 Spacecraft systems specific constraints Philae landing on the comet Chury 11/50

12 Spacecraft systems specific constraints Data Handling Limited Communications Limited data rates and low availability of the RF link except in geostationary orbit Indirect communication paths (using other spacecraft) Autonomous on-board data processing for bandwidth optimisation Automated on-board procedures and operation scheduling High capacity on-board data storage and compression Real-time autonomous control Navigation and Orbit control: autonomous avionics system Time reference, time distribution and synchronisation between on-board devices and with distant systems Robustness Long mission lifetime Maintainability limited to software Autonomous Failure Detection, Isolation and Recovery Operator error robustness Secured communications NASA 12/50

13 Spacecraft systems specific constraints Environment Tolerance to radiations for on-board electronics Cumulated radiation dose limits time-life + Destructive effects (latch-up) + Transients errors due to space particles (heavy ions, protons ) Rad hard component technologies (e.g. Silicon On Isolator) Fault-tolerant design inside the chips Fault-tolerant systems architecture with COTS components Poor electronics components and devices catalogue Lower processing performance w.r.t. ground applications Complex systems, heavy investments Technology gap on processing devices Electrical power: only solar energy Highly critical in deep space exploration Mechanical constraints Pre-operational life: Assembly Integration and Tests, transport, launch, orbit-transfer Extreme vacuum and thermal cyclic variations in operation 13/50

14 Spacecraft systems specific constraints Industrial efficiency Variety of missions / limited market Generic platforms and standard product families Requirement domain without precise mission selection Customisation for adaptation to mission Interfaces standardisation inter-operable products catalogue from several sources Payloads with specific instruments Legal constraints Geographical-return for international institutional missions ITAR / Export control Testability Full test coverage on highly complex systems Production, integration and validation methods and tools Quality Cost of non-quality Highly demanding development, manufacturing, assembly and verification processes Obsolescence Maintenance of manufacturing capability for critical components Strategic stocks 14/50

15 Spacecraft systems on-board architecture The International Space Station and the Space Shuttle 15/50

16 Spacecraft systems on-board architecture Satellites Two subsystems Payload Instruments Data Processing Mission specific (science instruments ) Huge volumes of non-real-time data High speed data links High Performance data processing High capacity data Storage (delayed transmission to ground stations) Platform Command and Control & Data Handling Mostly generic Control loop with real-time constraints Low data volumes Low speed data bus Low performance data processing Performance Reliability Low capacity data storage (Buffering) METOP Platform TERRASAR Platform 16/50

17 Spacecraft systems on-board architecture Satellites instruments High performance Computer (s) Payload processing Payload Software Thermal Regulation Thermal Control Electronics Thermal sensors Heaters Fluid loops RF Communications Electrical Power Data Data Storage Storage Power Control & Distribution Antennas Transponders Transponders Data management System On-board Buses and Networks Attitude and Orbit Control System (AOCS) Central Central Computer DMS Central Software Mechanisms Solar Panel Deployment Battery Sensors Actuators sun sensor Control Momentum Gyroscope gyroscopes star trackers magnetometer thrusters wheels magnetic torquers 17/50

18 Spacecraft systems on-board architecture Satellites Platform Data Handling Central On-Board Computer Main system bus Point-to-point Connections or connection to Main system bus Remote Terminal Remote Terminal Remote Terminal Remote Terminal Analogue interfaces To smart sensors (<10): Reaction wheels, star trackers, Gyroscopes, GPS receiver To dumb sensors (>100): Thermistors, switch closure 18/50

19 Spacecraft systems on-board architecture Satellite Payload data processing chain Payload Control Instrument or antenna Data Receiving Data Processing Data Transmission Antenna Data Storage 19/50

20 Spacecraft systems on-board architecture Typical scientific spacecraft architecture 20/50

21 Spacecraft systems on-board architecture Launcher example (Ariane 5) Fully automated system Stages separation Guidance Navigation and Control Generic equipment with specific mission configurations Low data volumes Critical real-time constraints High Availability Low speed data bus ENVOI DES ORDRES, ACQUISITION DES MESURES, AUTOTEST. INHIBITION EN CAS DE DEFAILLANCE EQ.Nominal N 1 OBC 1 (Maître) SIGNAL DE BON FONCTIONNEMENT BUS 1 BUS 2 MIL-STD-1553B UCTM COUPLEUR OBSERVATION DU CONTEXTE ET REPRISE EN CAS DE DEFAILLANCE DE L OBC MAITRE OBC 2 (Secours) EQ. Redondant N 1 Telemetry system High data volumes Segregated from the GNC system EQ.Nominal N i VERS ETAGES INFERIEURS VERS ETAGES INFERIEURS EQ. Redondant N i 21/50

22 Spacecraft systems on-board architecture In Orbit service & manned flight (ATV) RUSSIAN SEGMENT BUSES FTC 1 FTC 2 FTC 3 Sun Sensors to CMUs Propulsion Drive Electronics Gyros Earth Sensors Rendez-vous Sensors SYSTEM BUSES VTC CMU CMU MSU S Band UHF Power Distr. GPS CMU US SEGMENT BUSES Equipment Measurement & Command SENSORS ACTUATORS Launch Pad i/f BUSES ATV CORE ATV CARGO 22/50

23 now lets focus on future needs and technologies Pleiades takes high resolution pictures of the Earth 23/50

24 now lets focus on future needs and technologies Satellite avionics under test 24/50

25 Outline Introduction Spacecraft systems Applications Specific constraints Architecture Space systems on-board digital electronics and software State of the art technologies for processors and data-links Future needs and technology development strategy On-board processing Technology trends 25/50

26 State of the art On-board Processors Mil-Std-1750 Mil-STD-1750A standard architecture, many implementations 16 bits, typically 3 25 MHz Missions: ISS, ATV, Envisat, Rosetta, LansSat recent implementation still in use on Eurostar 3000 telecom satellites ERC-32 Sparc V7, 32 bits, typically MHz (0,5µm) Missions: ISS, ATV, Ariane 5, Vega Pleiades, TerraSar, Herschel, Gaia, Galileo Airbus Defence and Space Airbus Defence and Space Eurostar 3000 SCU ( processor) RUAG Space Vega On-Board Computer (ERC-32 processor) LEON 2 and LEON 3 Sparc V8, 32 bits, MHz (0,18nm) Spacecraft Controller on a Chip Leon 2 or Leon3 Specialised functions such as TM/TC, Reconfiguration, Modem Space standard I/O s: for 1553, SpaceWire, Can Bus Selected on almost all new Spacecraft OSCAR Computer (LEON-3 processor) 26/50

27 State of the Art Key data processing components Memories Commercial grade components with ECC s (EDAC or Reed Solomon) SDRAM or non volatile flash memory FPGA ( * ) Rad hard components (anti-fused technology: programmable only once) No common use (yet) of reprogrammable devices (radiation sensible) ASIC ( ** ) Space components developped in ASIC rad-hard technologies: Standard products: Spacecraft Controller on a Chip, I/O devices, memory control, Compression, FFT, GNSS processing, Specialized functions when processing performance cannot be reached through reprogrammable devices Rad-Hard libraries derived from commercial technologies : 180nm from ATMEL Aeroflex 90 nm STM 65 nm to be ready in 2016 (Commercial: 28nm or below) ( *) Field-Programmable Gate Array ( **) Application Specific Integrated Circuits Airbus Defence and Space Solid State Recorder up to 20 Tb with Flash memory Airbus Defence and Space CORECI recorder with ASIC s Up to 8.6 Gb/s image compression, cyphering and storage 27/50

28 State of the art Buses and Networks technologies Field bus or direct connections to many sensors and actuators Typical bandwidth: 10 to 100 Kbps Connections to local Remote Terminals or directly to on-board computer CAN bus, RS422, analogues Spacecraft control bus Main data link between the on-board functional sub-systems On Board Computers, remote terminals, sensors and actuators Key properties: reliability, real-time & dependability Typical data rate: 0,1 to 1 Mbps Mil-Std-1553B Payload data network For instruments data processing and storage Key properties: reliability & performance for data throughput Typical data rate: 10 Mbps to 1 Gbps Direct links or network topology SpaceWire ECSS (European Cooperation for Space Standardisation) European technology interoperability and harmonisation SpaceWire, MIL-STD-1553 and CAN bus 28/50

29 State of the art Mil-Std-1553 bus Well adapted for spacecraft command and control Master/Slave concept with 2 types of nodes One Master Bus Controller (BC), 31 slave remote Terminals (RT) Deterministic and reliable 1 Mbps Space standard for implementation requirements and communication services protocol (ECSS-E50-15) Large return on experience in many applications (space, aeronautics, ground transport ) Lot of sensors, commercial products, test equipment and know-how Industrial baseline on almost all space on-board data systems Launcher avionics (Ariane, Vega) Satellites platforms and payloads control In-Orbit infrastructure and manned flight (ISS, ATV) To Data Handling System BC RT 1 RT 2 RT 3 RT 31 To sensors/actuators 29/50

30 State of the art SpaceWire Spacecraft payload data network Adapted to space requirements from IEEE 1355 LVDS point to point connections with switched network capability 100 to 200 Mbps ECSS Space standard covers all layers and protocols Widely used worldwide Europe, US, Japan, Russia, China Active user community SpaceWire working group, International Conference Worldwide (small) industrial ecosytem 30/50

31 Outline Introduction Spacecraft systems Applications Specific constraints Architecture Space systems on-board digital electronics and software State of the art technologies for processors and data-links Future needs and technology development strategy On-board processing Technology trends 31/50

32 Future missions In development Space science and exploration program Bepi-Colombo, Solo, Euclid, Juice Metop-SG Next generation telecom Ariane 6 Human Flight: ORION Large constellations (OneWeb) Longer term Machine to Machine services Multi-service payloads Highly flexible and autonomous systems Space exploration robotic systems Vision based navigation Reusable launchers Space plane 32/50

33 Future Needs Challenging requirements New on-board functions, autonomy and flexibility Missions with high availability requirements High data throughput increasing with instruments technology Payload with many instruments Rapidly growing on-board data processing performance requirements Constraints Ground space communications limited bandwidth Limited power, volume & mass Harsh environment (mechanical, thermal, radiations ) Cost and competitiveness Context Increasing technology gap between space and ground electronics Limited choice of space-grade components Cost of technology development (cost, time, risks, business model) Space is a niche market 33/50

34 System analysis for high performance processing ➊ ➌ Variety of missions? Application categories 1 Image Processing Earth Observations Optical 2 Image Processing Earth Observations / Astro. NIR - IR. 3 Image Processing Astronomical Optical Star based. 4 Image Processing Astronomical Optical Wide field. 5 Image Processing Robotic Navigation 6 Radar SAR signal processing 7 Radar SAR On-board image processing & feature extraction 8 Telecom/SAR (Multi) Beam forming and Steerability. 9 Telecoms DSP Transparent 10 Telecoms DSP Regenerative 11 Soft Radio reconfigurable payload data communication interface. 12 Standard Compression 13 Payload Crypto 14 Radiometry Spectral analysis e.g. WBS 15 Others Performance metrics? Performance requirements Processing Gflop/s Flexibility Re-Prog Very High > 50 Very High Very Essential High 5-50 High Essential Medium Medium Prefferable Low < 0.5 Low Not Essential I/O Gbit/s Power Criticality Very High >100 High Very Limited High Medium Limited Medium 0,2-1 Low Not Critical Low <0,2 Memory % activity High 50-75% Medium 25-50% Medium < 25% ➋ ➍ Driving Performance Requirements? Requirements per categories Category Flexibilty Processing I/O Power % Memory 1.(1-3) Not Essential High Not Critical High High 2.(1-3) Prefferable High Not Critical High High 3.(3) Essential Very High High Limited Low 4.(1,3) Not Essential Medium High Limited Medium 5.(1,2) Essential High Low Very Limited Medium 6.(1,3) Not Essential High Medium Limited Low 7.(1,2) Very Essential Very High Very High Limited High 8.(2,3) Not Essential Very High Very High Not Critical Medium 9.(2,3) Not Essential Very High Very High Not Critical 10.(2) Very Essential Very High Very High Not Critical High 11.(1,2) Very Essential High Medium Not Critical Low 12.(1,2) Not Essential Medium Medium Not Critical 13.(1,2) Not Essential Medium Medium Not Critical 14.(1-3) Not Essential High Medium Limited Low Technology solutions? Processing classes Medium Processing, Medium Input, reprogrammable Processing M single instructions per second. I/O Mbits/s/channel I/O. Memory Mbit fast Memory High Processing, High Input, reprogrammable Processing M single Instructions per second. I/O Mbits/s/channel I/O. Memory Mbit fast Memory High Processing, High Input, no or limited reprogrammability Processing M single Instructions per second. I/O Mbits/s/channel I/O. Memory Mbit fast Memory 34/50

35 I/O performance - Log10(Gbps) System analysis for high performance processing Processing power and I/O performance , , ,5 0-0, , , , , Very High processing > 100 GFlop Typically requires ASIC technology Increase flexibility with high performance reporgrammable FPGA High processing GFlop Typically requires reprogrammable FPGA or a very efficient processing architecture with several multi/many cores Medium processing GFlop One or several µp (multicore) µp or reprogrammable FPGA -1, processing performance - Log10(GFlop) Sustained development of space grade processing technology One single technology/product cannot cover the full range Adapt our systems to use high performance COTS processing devices 35/50

36 Space technology development strategy Fill the technology gap without re-inventing the wheel for space Synergies between Space, Aeronautics and other domains Enable use of commercial electronics Develop a coherent set of interoperable products Develop the relevant methods and tools for Model Driven Development Focus technology developments on their competitiveness Space TAXI Space WHEEL 36/50

37 Outline Introduction Spacecraft systems Applications Specific constraints Architecture Space systems on-board digital electronics and software State of the art technologies for processors and data-links Future needs and technology development strategy On-board processing Technology trends 37/50

38 On-Board Software Reference Architecture Reference architecture definition with ESA and European Industry (SAVOIR) Standard functional interfaces Generic specifications Common basis for European industry interoperable building block development 38/50

39 Next Generation execution platform Multi-core processors and COTS processors ARM Multicore COTS FPGA technologies (Virtex, ProAsic, Spartan, Zynq ) NGMP (multicore Leon) in shorter term CBC COTS Based Computers Performance Ecosystem Secured framework for Software integration on central computer Time and Space Partitioning (enabling technology) Hypervisor, operating system, schedulability issues on multicore etc On-Board Software framework based on reusable product lines Execution platform with hypervisor, Real-Time Operating System and standard I/O s handling Data Handling Software and operational standards (PUS, FMS, CFDP ) Auto-coded AOCS application + integration of third party software IMA 4 Space Cost Satellite Data Communication Network (SDCN) I/Os: multi communication standards with common API to IMA execution platform Legacy interfaces (1553/SpW/Can) to comply with current satellites equipment product lines New interfaces supporting higher data-rate and lower cost with more convergence toward COTS technologies (e.g. Ethernet) SpaceFibre (1 to 5 Gbps) interoperable with SpaceWire Networks Trade-off SDCN technology Ethernet based solution for satellite is supported by Airbus R&T with CNES/DLR/ESA studies in the pipe ESA roadmap for TTE, including physical characterization on Ethernet devices in progress and ECSS standardisation FP7 Mission project «AFDX for Space» ESA studies to allow use of SpaceWire for platform command and control (SpaceWire AOCS, N-Mass, SpaceWire-D) Ariane 6 decision on TTE technology selection can influence the roadmap Potential technology choices in constellations could eventually give momentum for future evolutions on standard product lines Ethernet 4 Space 39/50

40 ARM Processor ARM processor Could be a basis for a next generation processor Efficient architecture Low Power consumption AvionicX project (CNES) ARM based breadboard computer with TTE interfaces Evaluation on launcher and satellite use cases ARM4Space project (H2020) Rad-Tolerant ARM based architecture for space use ASCOT project Definition of a next generation Spacecraft controller on a chip based on ARM Cortex All embedded spacecraft control function as current SCoC High Speed interfaces New embedded processing functions (e.g. GNSS) ARM is selected for Ariane 6 on-board computer The AvionicX Breadboard with embedded ARM Cortex 5 40/50

41 Software on Multicore processors Multicore Processors NGMP (multicore Leon 4) will be available in 2016 Almost all COTS high performance processing devices include several cores Methods, tools to optimize application software parallelisation on several cores New approaches for schedulability analysis based on probabilistic approach WCET formal proof too pessimistic Projects Proxima (H2020) and ProArtis for Space (ESA) Record task start time Task 1 Record task endtime Record task start time Task 2 Record task endtime Start TDI cycle / record start time Start tasks Record task start time Task 3 Record task endtime Wait for tasks execution completion End TDI cycle / record end time Record task start time Task 13 Record task endtime 41/50

42 On-board communications TTE or AFDX TTE or AFDX Cold Redundancy Hot Redundancy APME: Antenna Pointing Mechanism Electronics DST: Deep Space Transponder SADE: Solar Array Drive Electronics TTRM: TM, TC, RM and MM Module PM: Processor Module PCM: Power converters Module Legend APME Unit Communication Trans A DST-1 Receive A Trans B Receive B DST-2 High Speed on-board Network Single network common standard platform and payload networks on satellites Functional and telemetry data for launchers reduces costs to adapt products for a given mission Simplify interface with Ground Test equipment (EGSE) Network Configuration, Verification, Qualification, Security and Certification issues Need for embedded support functions (Network management, FDIR, debug, security functions..) Need for engineering support tools: modeling simulation, network analysis, formal proof Several European projects Switched Ethernet with different protocols/qos AFDX (Mission project), Time-Triggered Ethernet, Standard Ethernet Synergy with aeronautics Ariane 6 and Orion/MPCV selected TT-Ethernet Evolution of the SpaceWire standard / SpaceFibre Sensor Networks Many simple terminals (e.g. thermistors) on spacecraft: lots of wires Wireless (main issues with EMC and power autonomy, not data handling & protocols) Payload Instrument1 Instrument2 Instrument3 Instrument4 Instrument5 Instrument6 Instrument7 Instrument8 Instrument9 Instrument10 DC/DC A TTRM A board PCM A DC/DC A PM A board A B A OBC Controller memory A SSMM DC/DC B TTRM B board PCM B DC/DC B PM B board B Controller memory B //2 //2 //2 PCDU SADE Doors control Unit A //4 //4 //4 STR 2 STR 1 IMU B IMU A RIU TMTC A TMTC B Reaction wheel Unit 3/4 hot redundancy AOCS //8 //8 //x Thrusters Thrusters Thrusters Thrusters Sun Sensor Sun Sensor Thermistors Thermistors Thermistors Thermistors Thermistors Satellite Data Communication Network Ethernet 4 Space 42/50

43 IMA and Software Partitioning IMA 4 Space Hypervisors for time an space partitioning Project IMA for Space (ESA) defined the partitioning concept for space evaluated feasibility with several use cases and hypervisor technologies Baseline for SAVOIR reference architecture Project OBC-SA (DLR) Development of the OMAC4S test bed IMA Kernel Qualification Specification of Hypervisor functions and qualification requirements Adaptation of hypervisors to targets: Multicore (ARM, NGMP ) RTEMS and other operating systems Space qualification planned in 2016 for Xtratum, PikeOS, 43/50

44 High Performance Payload Processing Custom ASIC s High performance Limited to specific applications High non-reccuring cost Outdated silicon technology COTS based processor boards and Rad-hard programmable components Medium performance High recurring cost US dependant technology quickly obsolete State of the art Need for flexible generic processing at lower costs Instrument Instrument DDR COTS PM Instrument link COTS PM Switch Matrix RTC HS link SDCN Network FUTURE COTS PM Partition System ICPU RTC Software Partition Instrument A MMU Kernel Partition Instrument B Core Core Core Core High Performance Payload Processing (H3P) Performance H3P COTS based computing architecture tailored to mission requirements Availability Reliability 44/50

45 COTS Based Computing Architecture SmartIO to mitigate radiations effects ESA project High Performance COTS Based Computer Concept Rad hard SmartIO component is in charge of the interface between the COTS world and the rad hard world. It implements the fault mitigation techniques COTS components are managed by the SmartIO, shared memory mechanisms The SmartIO buffers input data in a fast local memory, and replay it in case of error Benefits SmartIO / PM link is a high level data link: SpW or SRIO, PCIe flexibility PM are slaves of the SmartIO : simplicity of the fault model reduced radiation campaign SmartIO includes a µ processor to manage fault mitigation techniques versatility Batch processing and results checking using signature performance Memory From instrument SmartIO To Mass memory Rad-Hard Processor Module Processor Module Processor Module COTS High Performance COTS Based Processor board developed with TI DSP C /50

46 HW/SW codesign CoDesign Process for parallel S/W and HW functions development Trans-domain collaboration (Socket and Projet P projects) Modelling techniques (System C) Co-simulation HW/SW Coherent development of HW and SW Seamless design flow Autocoding Very efficient hybrid execution platforms such as Zynq 46/50

47 SimOPS SW Dev. STB ATB Jsynoptic Linux / Windows FVB (Functional Verification Bench) Operating System SimAIT CCS FVB :Functional Verification Bench Processor Em ulator (Sim Leon / Sim ERC32 ) OBC Model FVB Models (Actuator Models, Sensor Models, Enviroment / Dynamics SM&C Bus Models (1553, Spw, Connectors, TMTC) Models ) FVB Models Equipment M odels Sim TG Simulation Kernel Linux / W indows SM&C I/F SCOE M odels AOCS Controller SW CSW Cradle SimTG Simulation Kernel Linux / Windows SatSim: Operations Simulator OBCP Dev. TM/TC, Mission SW data Specifc FVB Services TM/TC, Mission SW data Verification Info CCS Operating System EFM (Electrical / Functional Model) TM/TC, Relation to Harness MPO EGSE (EM) FVB Models Operating System Engineering/ Operations MCS EGSE (EM) EFM: Electrical/ Functional Model Equipment Models SM&C Bus Models (1553, Spw, Connectors, TMTC) SimTG Simulation Kernel Real -Time Linux TM/TC, Mission SW data, Relation to Harness SRDB S/C Config, Verification Infos MTM-MIS SimFE I /F SimOPS Jsynoptic Linux / Windows Units TM/TC MPO EGSE (FM) MCS EGSE (FM) SM&C - Corba Processor Emulator Operating System (SimLeon / SimERC32) OBC Model SVF-Dev (Software Verification Facitlity CSW Development) SimFE I/F SimFE HW I/F 1 SimOPS Linux / Windows SVF: Software Verification Facility Jsynoptic STB (Software Test Bench) Numerical RF-Test Bench SRDB Mirror SRDB Input Bus Models (1553, Spw, Connectors, TMTC) SimTG Simulation Kernel Linux / Windows Hybrid TBC: TM/TC, Verif. Info SM&C Bus Models (1553, Spw, Connectors, TMTC) SimTG Simulation Kernel Real -Time Linux TM/TC TM/TC, Verif. Info FVB Models Equipment Models STB: Software Test Bed Validity Local Unit MON FMON SimFE I/F SimFE I/F SimFE HW I/F Instruments TM/TC MIS ESOC MMO Legend: Main Input to SRDB Test Bench FIR Lx Monitoring (PMON, FMON) S/S S/S FMON FMON Architecture RAMS/FDIR Analyses & Verification Reconfiguration Function Orders (FIR) Inputs to FDIR SW Specs e.g. AOCS (SM/FM/FIR lists) Failures modes & propagation Inputs to FV Test Specs 4 (Simulation traces) 2 HW HW e.g. OBC e.g. STR FDIR Maturity & Complexity Metrics (KPIs) Cascading effect (timed), observables dysfunctional behaviour Dynamic FMECA Generation Block Failure Effects STR Loss of tracking Effect1(T0) Effect2(T0+xx) FMECA enhanced with failure propagation time FIR Lx FIR Lx Step-by-Step Simulation Monitoring Recovery Final State MON#32 (T+xx) FIR L2 (T0+xx) Mission cont. FDIR enrichment (HSIA) Instrument1 Instrument2 Instrument3 Instrument4 Instrument5 Instrument6 Instrument7 Instrument8 Instrument9 Instrument10 Payload OBC OBC Memory Memory Antenna Antenna Pointing Pointing Mechanism Mechanism PCDU PCDU Deep Space Deep Transponder Space Tx Transponder Tx Platform Communication Solar Array Solar Array drive drive Deep Space Deep Transponder Space Rx Transponder Rx Reaction Reaction Reaction Reaction wheel wheel wheel wheel IMU IMU RIU RIU STR STR AOCS Thrusters Thrusters Thrusters Thrusters FSS FSS Sun FSS Sensor Thermistors Thermistors Thermistors Thermistors Thermistors Model Driven Development System-Software engineering methods and tools Write and manage good requirements Handle MBSE and requirements in the same referential Customize methods and tools to manage product lines Technologies Connect interdisciplinary models for GS : RAMS, Design, Performance,. Evaluate the system operability during design and how to use design information during operation Implement extended enterprise Implements standards to support our design method SVF SW Verif. SVF OBCP Dev. SVF FCP Dev. FVI Simulation Use Cases Modelling & Simulation RANGE Satellite Reference DataBase RANGE MBSE approach around the functional avionics level Verification Engineering Operational Engineering RAMS / FDIR Modelling approach presentation 3 FDIR Integration Iterative & Incremental RAMS/FDIR modelling RANGE Ground System Engineering RAMS & FDIR Engineering Avionics modelling AOCS Engineering Others specialists (mechanical, electrical,...) Data processing Flight S/W Engineering AOCS autocoding RANGE High Speed Deterministic Links RANGE SysML OBSW RANGE 47/50

48 On-board processing technology trends Summary Missions Product lines (Astrobus/E3000): incremental changes No short term perspective of interface nor big computer change: Cost is the main driving factor for improvements Space Science, Instruments and Exploration Autonomous Robotics and mission planning / high performance processing / low power consumption Various robustness requirements vs. radiations New constellation projects - OneWeb New business conditions: implies changes/accelerations in technology priorities Recurring COST becomes a dominant driver Trends Lower the number of electronics equipment through centralisation of data processing functions Higher performance On Board Computers (and lower cost) Competitive/export markets including constellations: Maximise the use of COTS based processing Institutional specific missions: multicore Leon (Leon4/NGMP) / Rad-Tolerant Reconfigurable FPGA (BRAVE) Secured Software application framework allowing integration on central computer of several applications with different criticality levels Hypervisor for partitioning Increase data rates toward and within central computer Switched Ethernet Data Network More Less COST 48/50

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51 Space Selfie To: From: EARTH ROSETTA and the Comet Chury (67P-Churyumov-Gerasimenko)

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