An Overview of the Virginia Tech Program in Software Radios Implemented with Reconfigurable Computing

Transcription

1 An Overview of the Virginia Tech Program in Software Radios Implemented with Reconfigurable Computing Contributing Faculty P. M. Athanas, J. H. Reed, W. L. Stutzman, W. B. Tranter, B. D. Woerner, S. F. Midkiff Research Associates and Research Faculty Yeongjee Chung, Francis Dominique, Ivan Howitt, Lori Hughes, Randall Nealy, Aurelia Scharnhorst Student Researchers Tom Biedka, Ray Bittner, Mike Buehrer, Rick Cameron, Mark Cherbaka, Neiyer Correal, Carl Dietrich, Kai Dietz, Rich Ertel, Anwarul Hannon, Scott Harper, Yanchen He, Zhong Hu, Song Kim, Jeff Laster, Monika Maheshwari, Nitin Mangalvedhe, Raqibul Mostafa, Steve Nicoloso, Martin Pechanec, Paul Petrus, Kim Phillips, Pascal Renucci, Nattavut Smavatkul, Srikathyayani Srikanteswara, Steve Swanchara, Mariecel Torres, Matt Valenti, Yufei Wu, Weimen You Sponsored by DARPA under the GloMo Program Web Address:

2 Objective of the Project Design and build a high speed radio testbed using configurable computing modules and advanced receiver architectures Improved capacity Flexibility of platform Increases in processing power of platform Demonstrate smart antennas at the handset Create a hardware/software testbed to prove networking concepts 2

3 Overview of the Presentation Software Radio Using Reconfigurable Computing Introduction to Reconfigurable Computing Example Application: Multiuser Detection Architecture for a General Purpose Configurable Radio Evolution of the Configurable Computing Platform and Configurable Radio Smart Antennas at the Handset Project goals Measurements 3 Hardware development

4 Introduction to Reconfigurable Computing Configurable Computing (CC) Attempts To Increase Performance And Silicon Utilization Efficiency Through Logic Recycling using FPGA and FPGA-like Devices Hardware Algorithms Can Be Paged Into/Out Of CC Modules Much As Operating Systems Perform Software Paging Factors Impacting the Performance Logic Speed Speed Of Reconfiguration Flexibility Of Configuration 4

5 FPGAs vs. DSPs FPGAs can support multiple memory ports FPGAs outperform DSPs: Parallelism in the algorithm Simple operations in a fixed sequence FPGAs provide greater computational density using less power Large data sets, low resolution (8-12 bits) Simple control DSPs outperform FPGAs MAC operations Complex arithmetic 5

6 Wormhole RTR Stream Format Stream Format Program/Flow Header Data Configuration information Routing information Variable size Possibly removed as stream routs Application data stream Possibly chained Variable size 6

7 Multiuser Receiver Data Flow STAGE 1 STAGE 2 I ACTUAL RECV D SIGNAL Q I FROM DDC Q BUFFER RECV D SIGNAL & INITIALIZE STREAMS MATCHED FILTER CORRELATOR MATCHED FILTER CORRELATOR ACQUISTION AND TRACKING REGENERATE & COMBINE ESTIMATED RECV D SIGNAL REGENERATE & COMBINE GENERATE REVISED RECV D SIGNAL & BUFFER MATCHED FILTER CORRELATOR REVISED RECV D SIGNAL MATCHED FILTER CORRELATOR DEMODULATE OUTPUT RECV D DATA 7

8 Multiuser Receiver Hardware Reconfigurable Computing Platform Multiuser Receiver Host PC RF Front End Transmitter Digital Downconverter 8

9 Reconfigurable Computing Modules Under Development Turbo Coder/Decoder Equalizer/ Single User CDMA Receiver Symbol/Carrier/Code Synchronizers Next Modules Generic sample rate converter Coder/Decoder library Demodulator library 9

10 Phase 1 Implementation of the 1 - Proposed Reconfigurable Receiver Architecture Configurable Radio RF Front End Digital Downconverter Antenna Diversity Sampling Tracking Acquisition Filtering/ Adaptive Equalization Complex FIR Filter Despread Binary Correlator Noncoherent Demod FSK PSK Deinterleave FEC Decoder Block Convolutional Turbo Combiner RF Front End Digital Downconverter Receiver Control Host/ Network API To Be Determined Sigtek ST114 Direction for replacement of DSP µp functions with reconfigurable computing 10

11 Phase 3 Final Architecture 3 - Proposed Reconfigurable Receiver (PCI-based) RF Input Circuitry Channel 1 A D C Graychip DDC Combiner FPGA I FIFO Q FIFO DSP INPUT MODULE FPGA PROCESSING MODULE #1 PROCESSING MODULE #2 RF Input Circuitry Channel 2 A D C Graychip DDC SRAM SRAM SRAM SRAM D P R A M S R A M PROCESSING MODULE #3 PROCESSING MODULE #4 ANALOG SUPPLY DIGITAL SUPPLY PCI-BASED HOST INTERFACE SRAM SRAM OUTPUT MODULE FPGA PROCESSING MODULE #5 PROCESSING MODULE #6 Features ANALOG INPUT RF OUTPUT ANALOG SUPPLY CODEC I/Q MOD FREQ SYNTH D A C D A C R A M R A M XMIT FPGA RAM FEC DPLL Wider bandwidth front end Stallion processor Run-time reconfiguration Library of communication functions 11

12 Hardware Based Simulator Fast simulation engine by taking advantage of reconfigurable processor Supports radio development effort Enable reset init_stat reg length PN sequence generator (Data) PC (Preprocessor for system configuration and for setting system parameters) External input Ac θ mod_sel reset σ 2 2x1 MUX Modulator I Q Noise generator I Receiver (Demod and data decisions) PC (Postprocessor for data collection and analysis) seed Q 12

13 Adaptive Antenna and Direction Finding Algorithms and Hardware 13

14 Third Generation Array f=2050 MHZ Front End for Antenna 1 BPF X IF LPF IF AMP ADC / DDC (SigTek ST-114) Local ~ Oscillator f=1982 MHZ f=2050 MHZ Front End for Antenna 8 BPF X IF LPF IF AMP ADC / DDC (SigTek ST-114) Spatial Filters DSP Despreaders TI C549/C541 Code Timing Demodulator and Beamforming Algorithm Local ~ Oscillator f=1982 MHZ Demonstrate interference rejection through spatial filtering Applications Perform AoA estimation for position location applications Developing spatial channel models Study algorithm performance 14

15 MPRG Vector Measurement System Fully functional 8 elements, 1.25 MHz Bandwidth, GHz center frequency Flexible for adapting various antenna/polarization inputs, carrier frequencies, bandwidths, real-time algorithms, or data collection scenarios Eight Harris Programmable Direct Digital Downconverters, eight C54x DSPs, one Analog Devices New features being added CDMA capability Improved system executive processing 15

16 Research Issues Adaptive array algorithm performance in real situations Vector channel measurements Practical AOA algorithm and hardware development Adaptive array algorithm convergence issues 16

17 Measurement Result Signal strength using LSCMA Channel B signal strength Channel A signal strength time Indoor environment GHz carrier stationary rx and tx 10 second collect 17

18 Circular Model (Macrocell)* Base Station R Circular Scatterer Region Models macrocell environments Scatterers are uniformly distributed in a circular region about the mobile Approximate radius, 30 m < R < 200 m 18

19 Probability Density [log10(f)] Joint TOA-AOA (Circular BS View) f τθ, ( τθ, b ) b = ( D τ c )( D c+ τ c 2τc Dcos( θb )) 2 3 4π Rm( Dcos( θb) τc) 0 D 2τcDcos( θb ) + τ c : τc Dcos( θb ) : else R m D = 1km R m = 100m -1 5 Angle of Arrival (degrees) Time of Arrival (usec)

20 Summary of GloMo2 Accomplishments Over one hundred publications produced Three generations of smart antennas built Three spread spectrum receivers built Vector channel models created Fully reconfigurable radio being built 20