Router and switch architecture

Transcription

1 Router and switch architecture Martin Heusse Router internals

2 Contenu Router architecture Routing table data structure Router internals 2

3 What is routing? Packet reception Interface FIFO (ring buffer?) holds groups of bits as they arrive Packet queued until treated by central or interface card (throw interrupt) Check CRC, is there space in memory Packet classification (Dropped? Accepted? Switching method?) Moved to input hold queue Interface Classify Ring buffer (sometimes) Int. FIFO Int. queue Packet routing Packet forwarding Look up routing table Rewrite header (Ethernet, NAT?, TTL, checksum ) Packet moved to output hold queue Router internals 3

4 Input and Output queues Input queues absorb transient forwarding subsystem saturation Configurable Output queues holds burst of packets directed to one interface Switching Generally, queues hold a given number of packets (not bytes) How would you implement a queue? Ring? Chained list? What is the storage unit (MTU size bin, packet, particle ) There can be several queues in parallel (various priorities) Router internals 4

5 Shared memory first generation Ex.: conventional PC, Cisco 28, HP ProCurve 7xxx Everything stored in same memory space Bus Shared memory memory (routing table) Limiting factor: memory access Router internals 5

6 Shared memory first generation (cont.) Cisco 25xx Series CIsco 25xx (993) WIC Mgmt Card Daughter and Hub Cards WIC Slots 2524, 2525 Async Hub Ports 255, Ether/TR WAN Intf System Bus M 683 Sys Ctrl ASIC On Board DRAM Bus Boot ROM DRAM SIMM Dual UART NVRAM PCMCIA Flash Router internals 6

7 Shared memory first generation (cont.) CIsco 72 Cisco 72x Series PA 5 PA 3 PA PCI Bridge PCI Bridge PCI Bridge PCI Bus PCI Bus 2 PCI Bridge PCI Bridge PCI Bridge PA 6 PA 4 PA 2 I/O Controller Fast Ether Boot ROM NVRAM PCMCIA Dual UART Boot Flash PCI Bus I/O Bus Midplane EEPROM PCI Bridge Sys Ctrl GT 64 DRAM PCI Bridge Bus NPE SRAM! NPE- R 47 R 5 Layer 2 Cache NPE-2 Router internals 7

8 Shared memory first generation (cont.) Juniper M4 Decoupling of control plane and forwarding plane forwarding by a dedicated ASIC 998 4Gb/s JunOS based on FreeBSD Router internals 8

9 Shared memory first generation (cont.) PIC: Physical Interface Card Router internals 9

10 Intelligent line cards 2d generation Ex.: Cisco 75 Line cards have some intelligence, write into each other s memory Bus memory Limiting factor: shared bus (needs to be N times faster than each of N interfaces) Central processor dedicated only to control plane Distinct from Forwarding plane Router internals

11 Intelligent line cards 2d generation (cont.) CIsco 75 Cisco 75xx Series Dual UART Boot ROM NVRAM PCMCIA Boot Flash I/O Bus RSP Register FPGA Diag Bus FPGA Sys Ctrl DRAM ASICs Layer 2 Cache MemD Ctrl ASICs Diag Bus Bus SRAM QA ASIC R 46 R 47 R 5 Cy Bus Cy Bus IP/VIP IP/VIP Cy Bus Arbiter IP/VIP IP/VIP 6 94_6F9_c4 999, Cisco Systems, Inc. 72 Router internals

12 Intelligent line cards 2d generation (cont.) Versatile Interface Processors (/interface) PA PA PCI Bus PCI Bus 2 VIP PCI Bridge 2 PCI Bridge PCI Bus Boot ROM SRAM PMA ASICs DRAM Packet Bus DRAM Ctrl ASICs I/O Ctrl ASIC CYA ASICs Bus R 46 R 47 R 5 Layer 2 Cache EEPROM CBus Diag Bus Router internals 2

13 Intelligent line cards + crossbar switch 3d generation Ex. Cisco 76, juniper T-series, HP ProCurve Switch 42vl Crossbar switch: Routing of N simultaneous packet (or cell) Router internals 3

14 Head of line blocking Crossbar needs to be N times faster than each line or need one buffer / output on each input (i.e. one buffer per crosspoint) What goes through the crossbar? ATM cells particles? ( packet reassembly) packets Router internals 4

15 Cisco router performance (packets/s) Router Process switching Fast switching NPE-G dCEF per slot Router internals 5

16 A step further Check Cisco CEF ( Cisco express forwarding) Banyan switch MPLS: packets carry an identifier of their processing Router internals 6

17 Routing table Static entries, routing protocols, ARP Can be large! Entries in use are cached (on interface cards, if applicable) the cache holds a small subset of know destinations Router internals 7

18 Longest match lookup Routing table storage Source: Ruiz-Sanchez, M.A.; Biersack, E.W.; Dabbous, W., Survey and taxonomy of IP address lookup algorithms, Network, IEEE, vol.5, no.2, pp.8-23, Mar/Apr 2 Prefixes a * b * c * d * e * f * g * h * i * a d c e f g h i b Router internals 8

19 Path-compressed trie Prefixes a * b * c * d * e * f * g * h * i * b 3 2 a d c e f g h i Useful for sparsely populated space. But many prefixes used in IPv4 Backtracking necessary : after reaching e and finding out that it does not match, need to go back to d (for for example) Router internals 9

20 Disjoint prefix trie Prefixes a * b * c * d * e * f * g * h * i * a! c e d! b a # a " f g h i Disjoint prefixes do not overlap Router internals 2

21 There are other techniques! Router internals 2

22 Sources S. Keshav; An engineering approach to computer networking Cisco Router Architecture Ross & Kurose Computer Networking Router internals 22