COMPARISON OF COMPACTION TECHNIQUES IN VLSI PHYSICAL DESIGN. (M.Tech-VLSI Department, JSS Academy of Technical Education, Noida)

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1 COMPARISON OF COMPACTION TECHNIQUES IN VLSI PHYSICAL DESIGN Chetan Sharma & Shobhit Jaiswal 2 (M.Tech-VLSI Department, JSS Academy of Technical Education, Noida) ( chetan202@gmail.com ) & 2 ( jaiswalshobhit9@gmail.com ) Abstract: The rapid growth in integration technology has been made possible by the automation of various steps involved in the design and fabrication of VLSI chips. The main factors which decide the quality of any chip are power consumption, area and performance of the chip. The demand of light weighted & compact chip is increase day by day. This paper reviewed the different techniques of compaction of any chip and comparison among them because different techniques have different tradeoffs. The appropriate technique is used depending upon requirements. Keywords: CAD Tool, Layout design rules, Shadow propagation, Scanline, Flooring. Introduction: In the VLSI design cycle there are many steps: System specification, functional design, logic design, circuit design, physical design, design verification, fabrication, packaging, testing and debugging. The physical design is important step in the chip designing. The process of converting the specification of an electrical circuit into a layout is called the physical design process. Due to extremely small size of the individual components, physical design is an extremely tedious and error prone process. Almost all phases of physical design extensively use Computer Aided Design (CAD) tools, means steps are partially or fully automated. The main steps in VLSI physical design are partitioning, placement, routing and compaction. Compaction is very important step in the physical design due to the incereasively need of small size chips. The operation of layout area minimization without violating the design rules and without altering the original functionality of 60

2 layout is called as compaction. The input of compaction is layout and output is also layout but by minimizing area. Compaction is done by three ways: (a) By reducing space between blocks without violating design space rule.(b) By reducing size of each block without violating design size rule.(c) By reducing shape of blocks without violating electrical characteristics of blocks. Therefore compaction is very complex process because this process requires the knowledge of all design rules. Due to the use of strategies compaction algorithms are divided into one-dimensional algorithms (either in x-dimension or y-dimension), two dimensional algorithms (both in x- dimension and y-dimension) and topological algorithm (moving of separate cells according to routing constraints) Problem formulation: Given: Layout consists of set of geometrical Design style specific compaction problem: The scope and impact of compaction is different on different design styles: (a)full custom style: There are large scope of compaction in full custom design style because of randomly sizes of block and random space between blocks. (b) Standard cell design style: In this style height of blocks are fixed. Therefore scope is limited to channel compaction. (c) Gate array design style: In the gate array design style position of gate is fixed so scope is limited to optimizing wiring. Compaction Techniques: There are different compaction techniques as shown in fig (a) 3/2 -Dimensional feature M = {M, M 2, M 3,.M n ) Each M i has minimum size = s (M i ) Minimum space between M i & M j = d (M i, M j ) where <j, j<n Objective: The objective of compaction is to minimize layout area by moving feature close to each other and by resizing the feature such that: Size (Mi) s (M i ) Distance (M i, M j ) d (Mi,Mj) Compaction Techniques Hierarchical compaction - Dimensional 2- Dimensional Fig (a)- Types of compaction techniques Scan line Algorith m Shadow Path Propagation 6

3 -Dimensional compaction: In this technique compaction is done only in one dimension either in x-direction or y- direction until no further compaction is possible as discussed previous. There are two types of constraints which relates to these compaction techniques (i) Separation constraint (ii) Connectivity constraint. The techniques in -Dimensional compaction are described below: (a) Shadow propagation Technique: It is a widely used technique for compaction. The shadow is caused by shining of imaginary light from behind the feature under consideration. Now graph is formed by making two lists, one has the blocks which are covered by shadow and another one has not covered blocks by shadow of light is forwarding behind block no. then block no. 3,6,, is covered by shadow which are shown in fig (b) and the flow graph of shadow propagation is shown in fig(c) which is made by shaded blocks by shadow i.e. block no.3, 6,,. Interval generation of shadow propagation is shown in fig (d) Fig (b)- Shadow propagation method. 3 Fig (c)- Flow graph of shadow propagation Fig (d)- Interval generation for shadow propagation of fig (b) 62

4 (b) Scanline Technique: The scanline is an imaginary horizontal or vertical line that cuts through the layout in x or y compaction as shown below. The trade off in this technique is the much time consumption. Thus we use 3/2-D Compaction. 3/2-D Compaction: Fig (e)- Example of Scanline method In this method all the arranged blocks are cut by this scanline. The scanline traverses from the top to bottom of the layout for x- compaction. Similarly, for y-compaction the scanline traverses from the left to the right of the layout as shown in fig (e). 2-Dimensional compaction: In this method compaction is done in both dimension x-dimension as well as in y- dimension. 2-D compaction is in general much better than performing -D compaction. If 2-D compaction, solved optimally, produces minimum-area layouts. In this technique we move the blocks in such a way that it not only compact the circuit but also resolve interferences. Since the geometry is not as free as in 2-D Compaction. In this method two lists are formed one is ceiling another is floor. First is formed by the blocks which are appeared from the top & second is formed by the blocks which are appeared from the bottom. Selects the lowest block in the ceiling list and moves it to the place on the floor which maximizes the gap between floor and ceiling. The process is continued until all blocks are moved from ceiling to floor. Conclusion: This paper shows that how the compaction is useful in VLSI Design cycle and various techniques using in compaction and their tradeoffs. -Dimension method is quite simple but provides less compaction as compare to other method. 2- D Compaction provides more compaction form but require more time. So 3/2-D Compaction is mostly used. 63

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