High-Power Factor Flyback Converter for LED Driver with FL7732 PSR Controller. Bridge-Diode D R SN R START D VDD C VDD Q MOSFET

Transcription

1 A9750 HighPower Facor Flyback Converer for LED Driver wih FL77 PR Conroller nroducion This highly inegraed PWM conroller, FL77, provides several feaures o enhance he performance of lowpower flyback converers. The proprieary opology enables simplified circui design for LED lighing applicaions. By using singlesage opology wih primaryside regulaion, a LED lighing board can be implemened wih few exernal componens and minimized cos, wihou requiring an inpu bulk capacior and feedback circuiry. To implemen high power facor and low THD, consan onime conrol uilizes an exernal capacior conneced a he COM pins. Precise consancurren conrol regulaes accurae oupu curren across changes in inpu volage and oupu volage. The operaing frequency is proporionally changed by he oupu volage o guaranee DCM operaion wih higher efficiency and simple design. FL77 provides proecion funcions such as openled, shorled and overemperaure proecion. The currenlimi level is auomaically reduced o minimize he oupu curren and proec exernal componens in shorled condiion. This applicaion noe presens pracical design consideraion for an LED driver employing Fairchild emiconducor PWM PR conroller FL77. includes designing he ransformer, selecing he componens, and implemening consan curren regulaion. The sepbysep design procedure helps engineers design a power supply. The design procedure is verified hrough an experimenal prooype converer. Figure 1 shows he ypical applicaion circui of primaryside conrolled flyback converer using FL77 creaed in he design example. L BridgeDiode D C 1 R C P R TART C O D D DD C DD A 7 FL77 COM DD 4 Q MOFET 5 C Gae 8 GD 6 GD C 1 R 1 C COM R EE R C Figure 1. Typical Applicaion Circui Rev /17/1

2 A9750 Basic Operaion Generally, Disconinuous Conducion Mode (DCM) operaion is preferred for primaryside regulaion because i allows beer oupu regulaion. The operaion principles of DCM flyback converer are as follows: Mode During he MOFET urnon ime ( O ), inpu volage (.pk ) is applied across he primaryside inducor (L m ). Then, drain curren ( D ) of he MOFET increases linearly from zero o he peak value ( pk ), as shown in Figure. During his ime, he energy is drawn from he inpu and sored in he inducor..peak Q n:1 C O M D D D D Figure. Mode : Q[O], D[OFF] D OUT Mode.peak n:1 D D When he MOFET (Q) is urned off, he energy sored in he inducor forces he recifier diode (D) o be urned on. While he diode is conducing, oupu volage ( OUT ), ogeher wih diode forwardvolage drop ( F ), is applied across he secondaryside inducor and diode curren ( D ) decreases linearly from he peak value ( pk P / ) o zero. A he end of inducor curren discharge ime ( D ), all energy sored in he inducor has been delivered o he oupu. Q M D D D C O OUT Gae MODE MODE MODE Figure 4. Mode : Q[OFF], D[O] D n OUT.peak n:1 D D D C O OUT M M D D D Q D D D Figure 5. Mode : Q[OFF], D[OFF] O Mode A A O When he diode curren reaches zero, he ransformer auxiliary winding volage begins o oscillae by he resonance beween he primaryside inducor (L m ) and he effecive capacior loaded across MOFET (Q). D Figure. Basic Funcion of DCM Mode Flyback Rev /17/1

3 A9750 Consan Curren Regulaion The oupu curren ( O ) can be esimaed by using he peak drain curren ( pk ) of MOFET and discharging ime ( D ) of inducor curren because oupu curren ( O ) is same as he average of he diode curren ( D ) in seady sae. The oupu curren esimaor idenifies he peak value of he drain curren wih a peakdeecion circui and calculaes he oupu curren using he inducor discharging ime and swiching period ( ). This oupu informaion is compared wih an inernal precise reference o generae error volage ( COM ), which deermines he duy cycle of he MOFET in Consan Curren Mode. Wih Fairchild s innovaive TRUECURRET echnique, he consan oupu curren can be precisely conrolled. 1 P o C (1) REE TRUECURRET curren predicion. D 1 calculaion makes a precise oupu 7 COM Oupu volage is deeced by he auxiliary winding and resisive divider conneced o he pin, as shown in Figure 7. OC Linear Frequency Conroller Freq. 6 Figure 8. Linear Frequency Conrol OUT When oupu volage decreases, secondary diode conducion ime is increased and he linear frequency conrol lenghens he swiching period, which reains DCM operaion in he wide oupu volage range, as shown in Figure 8. The frequency conrol also lowers primary rms curren wih beer power efficiency in fullload condiion. 1 C Error Amp. REF Peak Deecor TrueCurren Calculaion O = O.nom Primary Curren D econdary Curren no T D Deecor 6 O = 75% O.nom n O 4 Figure 6. Deecion for TRUECURRET Calculaion pk = C D.pk R O = 60% O.nom 4 D n O 5 4 T O 5 D 5 T D D D Figure 9. Primary and econdary Curren Figure 7. TRUECURRET Calculaion Principle Linear Frequency Conrol As menioned above, DCM should be guaraneed for high power facor in flyback opology. To mainain DCM in he wide range of oupu volage, frequency is linearly changed by he oupu volage in linear frequency conrol. BCM Conrol The end of secondary diode conducion ime is possibly over a swiching period se by linear frequency conrol. n his case, FL77 doesn allow CCM and he operaion mode changes from DCM o BCM. Therefore, FL77 originally eliminaes subharmonic disorion in CCM. Rev /17/1

4 A9750 Proecions The FL77 have several selfproecion funcions, such as overvolage proecion, overemperaure proecion, and pulsebypulse curren limi. All he proecions are implemened as AuoResar Mode. DD DD_OP DD_O LED Open! OpenLED Proecion FL77 proecs exernal componens, such as diode and capacior a secondary side, in openled condiion. During swichoff, he DD capacior is charged up o he auxiliary winding volage, which is applied as he refleced oupu volage. Because he DD volage has oupu volage informaion, he inernal volage comparaor a he DD pin can rigger oupu overvolage proecion (OP), as shown in Figure 9. When a leas one LED is opencircuied, oupu load impedance becomes very high and oupu capacior is quickly charged up o OP x / A. Then swiching is shu down and he DD block goes ino Hiccup Mode unil he openled condiion is removed, as shown in Figure 10. DD_OFF OUT DD_OP x / A GATE Figure 11. Waveforms a OpenLED Condiion DD 4 OP nernal Bias DD good horled Proecion (OCP) n case of shorled condiion, he swiching MOFET and secondary diode are usually sressed by he high powering curren. However, FL77 changes he OCP level in he shor LED condiion. When volage is lower han 0.4, OCP level changes o 0. from 0.7, as shown in Figure 1 so ha powering is limied and exernal componens curren sress is relieved. DD good R Q Figure 10. nernal OP Block hudown Gae Driver Under olage Lockou (ULO) The urnon and urnoff hresholds are fixed inernally a 16 and 7.5, respecively. During sarup, he DD capacior mus be charged o 16. The DD capacior coninues o supply DD unil power can be delivered from he auxiliary winding of he main ransformer. DD is no allowed o drop below 7.5 during his sarup process. This ULO hyseresis window ensures ha DD capacior properly supplies DD during sarup. OCP A < 0.4 OCP = 0.. A > 0.6 OCP = 0.7. LEB 1 C Figure 1. nernal OCP Block Figure 1 shows operaional waveforms a shorled condiion. Oupu volage is quickly lowered o 0 righ afer he LEDshor even. Then, he refleced auxiliary volage is also 0 making volage less han OCP level limis primaryside curren and DD hiccups up and down in beween ULO hyseresis. 6 Rev /17/1 4

5 A9750 LED hor! Overolage Proecion (OP) The OP prevens damage in overvolage condiions. f he DD volage exceeds a openloop feedback condiion, he OP is riggered and he PWM swiching is disabled. A openled condiion, DD reaches DD_OP. Then, auoresar sequence causes a delay, limiing oupu volage. C 0. DD OverTemperaure Proecion (OTP) The builin emperauresensing circui shus down PWM oupu if he juncion emperaure exceeds 150 C. There is hyseresis of 10 C. DD_O DD_OFF Figure 1. Waveforms a horled Condiion A shorled condiion, is low due o low oupu volage. Then, OCP level is changed o 0. o reduce oupu curren. Rev /17/1 5

6 A9750 Design Procedure n his secion, a design procedure a of singlesage flyback using FL77 is presened using he schemaic of Figure 1 as a reference. An offline LED driver wih 16.8 W (4 /0.7 A) oupu has been seleced as a design example. The design specificaions are as follows: npu volage range: 90 ~ 64 AC and 50 ~ 60 Hz ominal oupu volage and curren: 4 /0.7 A Minimum efficiency: 87% Maximum swiching frequency: 65 khz ep 1. nducor elecion (L m ) FL77 operaes wih consan urnon and urnoff ime, as shown Figure 14. When MOFET urnon ime ( O ) and swiching period ( ) are consan, is proporional o and can implemen high power facor. Max. Peak wich Curren (W.PK) wich Curren (W) Peak npu Curren (in.pk) npu olage (in) npu Curren (in) hen.pk and.min.pk can be expressed as:. pk. rms (4). min. pk. rms (5) where he.rms and.rms are rms line inpu curren and volage, respecively. O is required o calculae reasonable L m value. Wih Equaion () ~ (5), he urnon ime, O, is obained as: L O m f. rms. rms The inpu power is given as: P PO s. rms (7) Wih Equaion (6) and (7), he L m value is obained as: O O (. rms ) f s (8) P (6) Consan OnTime (O) Consan OffTime Figure 14. Theoreical Waveform The singlesage flyback using FL77 is assumed o operae in DCM due o consan O and. npu volage is applied across he magneizing inducance (L m ) during O, charging he magneic energy in L m. Therefore, he maximum peak swich curren ( W.pk ) of MOFET occurs a peak poin of line volage, as shown Figure 14. The peak inpu curren (.pk ) is also shown a he peak inpu volage of one line cycle. Once he maximum O is decided, W.pk of MOFET is obained a he minimum line inpu volage and fullload condiion as: (Design Example) ince he minimum inpu volage is 90 AC, he maximum O occurs a fullload condiion. Assuming he maximum O is 7.4 µs a 65 khz of he maximum frequency, he magneizing inducance is obained as: (7.410 ) L m 74µH 16.8 The maximum peak curren of MOFET a nominal oupu power is calculaed as: W. pk A O.min pk W. pk () where.min.pk and O are he peak inpu volage and he maximum urnon ime a he minimum line inpu volage, respecively. Using equaion (), he peak inpu curren is obained by:. pk pk 1.min ( )(. ) f O O L m s () ep. ensing Resisor and n P elecion ince FL77 adops TRUECURRET Calculaion mehod o regulae consan oupu curren ( O ), as defined in equaion (1). The oupu curren is proporional o urn raio n ps beween he primary and secondary windings of he ransformer and inversely proporional o sensing resisor (R ). The FL77 also implemens cyclebycycle curren limiaion by deecing C o proec sysem from oupu shor or overload. Therefore, C level o handle raed sysem power wihou he curren limiaion should be considered. is ypical o se he cyclebycycle limi level Rev /17/1 6

7 A9750 (ypical: 0.67 ) a 0~0% higher han C peak volage ( C.pk ) a fullload condiion. MOFET peak curren ( W.pk ) is convered ino C,pk as: C. pk W. pk R (9) According o Equaion (1), he ransformer urn raio is deermined by he sensing resisor and nominal oupu curren as: n ps R (10) O where10.5 is a consan. 1 D C (11) (Design Example) Once C,pk is se as 0.5, he sensing resisor value is obained as: R n ps C. pk W. PK ep. n A elecion When DD volage is, FL77 sops swiching operaion due o overvolage proecion (OP). o n A can be deermined as follows: n DD OP A (1) O. OP O. OP. where (n A = A / ) is he urns raio he of secondary o auxiliary of ransformer. Therefore, O.OP can be se by changing he n A value. (Design Example) Once oupu overvolage level is se as 0, n A is obained as: n A link capacior, auxiliary winding volage canno be clamped o refleced oupu volage due o he small L m curren, which induces volage sensing error. Then, frequency decreases rapidly a he zerocrossing poin of line volage, which can cause flicker. To mainain consan frequency over he whole sinusoidal line volage, FL77 has blanking o disable sampling of volage a less han a paricular line volage by sensing he auxiliary winding. Considering he maximum swiching frequency a raed power and blanking level, R 1 and R are obained as: R R ( ) n. O F A max (1) max r R 1. (14) where.max is he value o se he maximum swiching frequency for consan oupu curren in raed power and F is secondary diode forward volage. 1. bnk n bnk AP R (. ) bnk. bnk R where.bnk and n AP are he blanking level of inpu volage and he urn raio of auxiliary o primary, respecively. The n AP can be calculaed as he raio of n A o n P..bnk and.bnk are decided inernally a 1 µa and (Design Example) The volage divider nework is deermined as: R (4 0.7) Once.bnk level is se o 50, R is obained as. R k ( ) 7.06 Then R 1 is deermined o be kω. (15) ep 4. Resisor elecion (R 1 and R ) The firs consideraion for R 1 and R selecion is ha is.5 a he end of diode curren conducion ime o operae a maximum swiching frequency a raed power. The second consideraion is blanking, as explained below. The oupu volage is deeced by auxiliary winding and a resisive divider conneced o he pin, as shown in Figure 7. However, in a singlesage flyback wihou DC is recommended o place a bypass capacior of 10 ~ 0 pf closely beween he pin and he GD pin o bypass he swiching noise and keep he accuracy of he sensing for CC regulaion. The value of he capacior affecs consancurren regulaion. f a high value of capacior is seleced, he discharge ime D becomes longer and he oupu curren is lower, compared o small capacior. Rev /17/1 7

8 A9750 ep 5. Design he Transformer The number of primary urns is deermined by Faraday s law. p,min is fixed by he peak value of he minimum line inpu volage across he primary winding and he maximum on ime. The minimum number of urns for he ransformer primary side o avoid he core sauraion is given by: p min.min. pk B sa A e O, (16) where A e is he crosssecional area of he core in m and B sa is he sauraion flux densiy in Tesla. ince he sauraion flux densiy decreases as he emperaure rises, he highemperaure characerisics should be considered when i is used in an enclosed case. (Design Example) An RM8 core is seleced for he ransformer and he minimum number of urns for he ransformer primary side o avoid he core sauraion is given by: p, min 54. 5T Considering he olerance of he ransformer and high ambien emperaure, P should be seleced wih a margin abou 5% ~ 10% o avoid core sauraion: p T Once he urn number of he primary side ( P ) is deermined as 60 T, he urn number of he secondary side ( ) is obained by: T Once he urn number of he secondary side ( ) is deermined as 0 T, he auxiliary winding urns ( A ) is obained by: A T A is deermined o be 15 T. ep 6. Calculae he olage and Curren of he wiching Devices Primaryide MOFET: The volage sress of he MOFET was discussed when deermining he ransformer urns raio. Assuming he drain volage overshoo is he same as he refleced oupu volage, he maximum drain volage is given as: O RO.max RO = ( O F ) P / D in DCM Figure 15. Drain olage of MOFET ( ) P D (max).max. pk o F O (17) where in.max.pk is he maximum line peak volage. The rms curren ( W.rms ) hough he MOFET is given as: f 6 O W. rms pk (18) (Design Example) Assuming ha drain volage overshoo is he same as he refleced oupu volage, he maximum drain volage across he MOFET is calculaed as: 60 D (max) 74 (4 0.7) 5 0 The rms curren hough he MOFET is W. rms A 6 econdaryide Diode: The maximum reverse volage and rms curren of he recifier diode are obained as: D O in. max. pk (19) P in. min. pk P D. rms W. rms (0) RO (Design Example) The diode volage and curren are obained as: 0 D D A rms Rev /17/1 8

9 A9750 ep 7. Design RCD nubber in Primary ide When he power MOFET is urned off, here is a highvolage spike on he drain due o he ransformer leakage inducance. This excessive volage on he MOFET may lead o an avalanche breakdown and evenually failure of he device. Therefore, i is necessary o use an addiional nework o clamp he volage. The RCD snubber circui and is waveform are shown in Figure 16 and Figure 17, respecively. The RCD snubber nework absorbs he curren in he leakage inducance by urning on he snubber diode (D ) once he MOFET drain volage exceeds he cahode volage of snubber diode. n he analysis of snubber nework, i is assumed ha he snubber capacior is large enough ha is volage does no change significanly during one swiching cycle. The snubber capacior should be ceramic or a maerial ha offers low ER. Elecrolyic or analum capaciors are unaccepable for hese reasons..peak R D C L m n:1 D CO OUT nubber capacior volage a fullload condiion is given as: (1) RO O The power dissipaed in he snubber nework is obained as: P R 1 L lk PK RO f () where L lk is leakage inducance, is he snubber capacior volage a full load, and R is he snubber resisor. The leakage inducance is measured a he swiching frequency on he primary winding wih all oher windings shored. Then, he snubber resisor wih proper raed waage should be chosen based on he power loss. The maximum ripple of he snubber capacior volage is obained as: () C R f n general, 5 ~ 0% ripple of he seleced capacior volage is reasonable. n his snubber design, neiher he lossy discharge of he inducor nor sray capaciance is considered. L lk (Design Example) ince he volage overshoo of drain volage has been deermined o be he same as he refleced oupu volage, he snubber volage is: Gae D RO O 150 D Figure 16. nubber Circui O RO The leakage inducance is measured as 10 µh. Then he loss in snubber neworking is given as: P W 150 R 1. 84k To allow 7% ripple on he snubber volage (150 ): 150 C nF Figure 17. nubber Waveforms Rev /17/1 9

10 A9750 Lab oes 1. Before modifying or soldering/desordering he power supply, discharge he primary capaciors hrough he exernal bleeding resisor. Oherwise, he PWM C may be desroyed by exernal highvolage during he process. This device is sensiive o elecrosaic discharge (ED). To improve he yield, he producion line should be ED proeced as required by A ED 1.1, ED 1.4, ED 7.1, ED TM 1.1, and EO/ED 6.1 sandards.. n case of LEDshor condiion, DD volage charged a DD capacior should ouch DD off level rapidly o sop swiching. Therefore, DD capacior value is recommended under µf. Rev /17/1 10

11 A9750 chemaic of Design example Figure 18 shows he schemaic of he 16.8 W LED driver design example. RM8 core is used for he ransformer. Figure 19 shows he ransformer informaion. L LF1 BD1 R1 R RM8 Do1 o MO1 CF1 CF C1 R R1 C1 p s Co1 Co Ro1 4/0.7A F1 R D1 D1 R6 C C a CY1 U1 C5 7 COM DD 4 5 C Gae 8 GD 6 GD C 1 RG1 Q1 R4 R5 C4 RC1 RC Figure 18. chemaic of he FL77 17 W Design Example A(6 à5) P(1 à) (7 à8) P1(1 à1) Figure 19. Transformer Winding rucure o. Winding Pin ( F) Wire Turns Winding Mehod 1 P1 1 à 1 0.5φ 0 Ts olenoid Winding nsulaion: Polyeser Tape = 0.05 mm, Layer 7 à 8 0.5φ (TW) 0 Ts olenoid Winding 4 nsulaion: Polyeser Tape = 0.05 mm, Layer 5 P 1 à 0.5φ 0 Ts olenoid Winding 6 nsulaion: Polyeser Tape = 0.05 mm, Layer 7 A 6 à 5 0.5φ 15 Ts olenoid Winding 8 nsulaion: Polyeser Tape = 0.05 mm, Layer Pin pecificaion Remark nducance µh ± 10% 60 khz, 1 Leakage 1 6 µh 60 khz, 1 hor All Oupu Pins Rev /17/1 11

12 A9750 Bill of Maerials em o. Par Reference Par umber Qy. Descripion Manufacurer 1 BD1 DF A / 600 Bridge Diode Fairchild emiconducor CF1 MPX AC75 104K / AC75 XCapacior Carli CF MPX AC75 47K 1 47 / AC75 XCapacior Carli 4 C1 C106C10KDRACTU 1 10 / 1 k MD Capacior 16 Keme 5 CY1 CFzE47M10BW 1 47 / 50 YCapacior amwha 6 Co1, Co KMG 470 µf / µf / 5 Elecrolyic Capacior amyoung 7 C1 MPE 60104K / 60 MPE film Capacior ungho 8 C KMG µf / 50 1 µf / 5 Elecrolyic Capacior amyoung 9 C C0805C104K5RACTU / 50 MD Capacior 01 Keme 10 C4 C0805C00J5GACTU 1 00 / 50 MD Capacior 01 Keme 11 C5 C0805C5ZACTU 1 5 / 5 MD Capacior 01 Keme 1 D1 R1M / 1 A Ulra Fas recovery Diode 1 Do1 ED 1 00 / A, Fas Recifier 14 D / 1 A, General Purpose Recifier Fairchild emiconducor Fairchild emiconducor Fairchild emiconducor 15 F1 51A 1 50 / 1 A Fuse Bussmann 16 LF1 R1040KT mh nducor, 10Ø Bosung 17 MO1 C 471 D07A 1 Meal Oxide arisor amwha 18 Q1 FDD560Z / 4 A, Channel MOFET Fairchild emiconducor 19 RG1, R6 RC106JR0710L 10 Ω MD Resisor 16 Yageo 0 R1, R RC106JR07100KL 100 kω MD Resisor 16 Yageo 1 Rcs1, Rcs RC106JR071RL 1 Ω MD Resisor 16 Yageo Rcs RC106JR07R4L 1.4 Ω MD Resisor 16 Yageo Ro1 RC106JR070KL 1 0 KΩ MD Resisor 16 Yageo 4 R4 RC106JR07150KL KΩ MD Resisor 16 Yageo 5 R1, R, R RC106JR0768KL 68 KΩ MD Resisor 16 Yageo 6 R5 RC106JR074KL 1 4 KΩ MD Resisor 16 Yageo 7 T1 RM8 Core 1 1Pin, Transformer TDK 8 U1 FL77M_F116 1 Main PR Conroller Fairchild emiconducor Rev /17/1 1

13 A9750 Relaed Daashees FL77 ingleage PFC PrimaryideRegulaion Offline LED Driver Reference Designs hp:// DCLAMER FARCHLD EMCODUCTOR REERE THE RGHT TO MAKE CHAGE WTHOUT FURTHER OTCE TO AY PRODUCT HERE TO MPROE RELABLTY, FUCTO, OR DEG. FARCHLD DOE OT AUME AY LABLTY ARG OUT OF THE APPLCATO OR UE OF AY PRODUCT OR CRCUT DECRBED HERE; ETHER DOE T COEY AY LCEE UDER T PATET RGHT, OR THE RGHT OF OTHER. LFE UPPORT POLCY FARCHLD PRODUCT ARE OT AUTHORZED FOR UE A CRTCAL COMPOET LFE UPPORT DECE OR YTEM WTHOUT THE EXPRE WRTTE APPROAL OF THE PREDET OF FARCHLD EMCODUCTOR CORPORATO. As used herein: 1. Life suppor devices or sysems are devices or sysems which, (a) are inended for surgical implan ino he body, or (b) suppor or susain life, or (c) whose failure o perform when properly used in accordance wih insrucions for use provided in he labeling, can be reasonably expeced o resul in significan injury o he user.. A criical componen is any componen of a life suppor device or sysem whose failure o perform can be reasonably expeced o cause he failure of he life suppor device or sysem, or o affec is safey or effeciveness. Rev /17/1 1