Version 2.1, 6 May 2011

Transcription

1 Version 2.1, 6 May 2011 Off-Line SMPS Curren Mode Conroller wih inegraed 650V CoolMOS and Sarup cell (frequency jier Mode) in FullPak Power Managemen & Supply N e v e r s o p h i n k i n g.

2 Revision Hisory: Daashee Previous Version: 2.0 Page Subjecs (major changes since las revision) 32 Revised ypo in ouline dimension drawing For quesions on echnology, delivery and prices please conac he Infineon Technologies Offices in Germany or he Infineon Technologies Companies and Represenaives worldwide: see our webpage a hp:// CoolMOS, CoolSET are rademarks of Infineon Technologies AG. Ediion Published by Infineon Technologies AG, Munich, Germany, 2008 Infineon Technologies AG. All Righs Reserved. Legal disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac your neares Infineon Technologies Office ( Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac your neares Infineon Technologies Office. Infineon Technologies Componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.

3 Off-Line SMPS Curren Mode Conroller wih inegraed 650V CoolMOS and Sarup cell (frequency jier Mode) in FullPak Produc Highlighs TO220 FullPak wih low Rdson MOSFET for high power applicaion Acive Burs Mode o reach he lowes Sandby Power Requiremens < 100mW Auo Resar proecion for overload, overemperaure, overvolage Exernal auo-resar enable funcion Buil-in sof sar and blanking window Exendable blanking Window for high load jumps Buil-in frequency jier and sof driving for low EMI Green Mould Compound Pb-free lead plaing; RoHS complian Feaures 650V avalanche rugged CoolMOS wih buil-in Sarup Cell Acive Burs Mode for lowes Sandby Power Fas load jump response in Acive Burs Mode 67kHz inernally fixed swiching frequency Auo Resar Proecion Mode for Overload, Open Loop, VCC Undervolage, Overemperaure & Overvolage Buil-in Sof Sar Buil-in blanking window wih exendable blanking ime for shor duraion high curren Exernal auo-resar enable pin Max Duy Cycle 75% Overall olerance of Curren Limiing < ±5% Inernal PWM Leading Edge Blanking BiCMOS echnology provide wide VCC range Buil-in Frequency jier and sof driving for low EMI CoolSET -F3R PG-TO220FS-6 PG-TO Descripion The CoolSET -F3R FullPak is he enhanced version of CoolSET -F3 and arges for he Off-Line Adapers and high power range SMPS in DVD R/W, DVD Combi, se op box, ec. I has a wide Vcc range o 25V by adoping he BiCMOS echnology. Wih he meri of Acive Burs Mode, i can achieve he lowes Sandby Power Requiremens (<100mW) a no load and V in = 270VAC. Since he conroller is always acive during he Acive Burs Mode, i is an immediae response on load jumps and leads o <1% volage ripple volage a oupu. In case of proecion for Overemperaure, Overvolage, Open loop and Overload condiions, i would ener Auo Resar Mode. Thanks for he inernal precise peak curren limiaion, i can provide accurae informaion o opimize he dimension of he ransformer and he oupu diode. The buil-in blanking window can provide sufficien buffer ime before enering he Auo Resar Mode. In case of longer blanking ime, a simply addiion of capacior o BA pin can serve he purpose. Furhermore, he buil-in frequency jier funcion can effecively reduce he EMI noise and furher reduce he scale of inpu filer. The componen couns can furher be reduced wih he various buil-in funcions such as sof sar, blanking ime and frequency jier. Typical Applicaion VAC CBulk Snubber Converer DC Oupu - VCC CVCC Drain Power Managemen Sarup Cell GND PWM Conroller Curren Mode Precise Low Tolerance Peak Curren Limiaion Conrol Uni AciveBurs Mode Auo Resar Mode CoolMOS CoolSET -F3R ( Jier ) CS FB BA RSense Type Package V DS F OSC R DSon 1) 230VAC ±15% PG-TO V 67kHz ) VAC 120W 2) 1) T j =25 C 2) Calculaed maximum inpu power in an open frame design a T a =50 C, T j =125 C and R hsa (exernal heasink) = 2.7K/W. Refer o inpu power curve for oher T a Version May 2011

4 Table of Conens Page 1 Pin Configuraion and Funcionaliy Pin Configuraion wih PG-TO Pin Funcionaliy Represenaive Blockdiagram Funcional Descripion Inroducion Power Managemen Improved Curren Mode PWM-OP PWM-Comparaor Sarup Phase PWM Secion Oscillaor PWM-Lach FF Gae Driver Curren Limiing Leading Edge Blanking Propagaion Delay Compensaion Conrol Uni Basic and Exendable Blanking Mode Acive Burs Mode Enering Acive Burs Mode Working in Acive Burs Mode Leaving Acive Burs Mode Proecion Modes Auo Resar mode wih exended blanking ime Auo Resar wihou exended blanking ime Elecrical Characerisics Absolue Maximum Raings Operaing Range Characerisics Supply Secion Inernal Volage Reference PWM Secion Sof Sar ime Conrol Uni Curren Limiing CoolMOS Secion Typical Conroller Performance Characerisics Version May 2011

5 Table of Conens Page 6 Typical CoolMOS Performance Characerisics Inpu Power Curve Ouline Dimension Marking Schemaic for recommended PCB layou Version May 2011

6 1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion wih PG-TO Pin Symbol Funcion 1 Drain 650V 1) CoolMos Drain 2 CS Curren Sense/ 650V 1) CoolMOS Source 3 BA exended Blanking & exernal Auo Resar enable 4 VCC Conroller Supply Volage 5 GND Conroller Ground 6 FB Feedback 1) a T j =110 C Package PG-TO CoolSET -F3R Pin Configuraion and Funcionaliy 1.2 Pin Funcionaliy Drain (Drain of inegraed CoolMOS ) Pin Drain is he connecion o he Drain of he inernal CoolMOS and he HV of he sarup cell. CS (Curren Sense) The Curren Sense pin senses he volage developed on he series resisor insered in he source of he inegraed CoolMOS. If CS volage reaches he inernal hreshold of he Curren Limi Comparaor, he Driver oupu is immediaely swiched off. Furhermore he curren informaion is provided for he PWM- Comparaor o realize he Curren Mode. BA (exended Blanking & Auo-resar enable) The BA pin combines he funcions of exendable blanking ime for over load proecion and he exernal auo-resar enable. The exendable blanking ime funcion is o exend he buil-in 20 ms blanking ime by adding an exernal capacior a BA o ground. The exernal auo-resar enable funcion is an exernal access o sop he gae swiching and force he IC o ener auo-resar mode. I is riggered by pulling down he BA pin o less han 0.33V. VCC (Power Supply) The VCC pin is he posiive supply of he IC. The operaing range is beween 10.5V and 25V. 1 Drain CS BA VCC GND FB GND (Ground) The GND pin is he ground of he conroller. FB (Feedback) The informaion abou he regulaion is provided by he FB Pin o he inernal Proecion Uni and o he inernal PWM-Comparaor o conrol he duy cycle. The FB- Signal is he only conrol signal in case of ligh load a he Acive Burs Mode. Figure 1 Pin Configuraion PG-TO (fron view) Version May 2011

7 Represenaive Blockdiagram 2 Represenaive Blockdiagram Figure 2 Represenaive Blockdiagram Version May 2011

8 Funcional Descripion 3 Funcional Descripion All values which are used in he funcional descripion are ypical values. For calculaing he wors cases he min/max values which can be found in secion 4 Elecrical Characerisics have o be considered. 3.1 Inroducion CoolSET -F3R FullPak is he furher developmen of he CoolSET -F3 for high power applicaion. The paricular enhanced feaures are buil-in feaures for sof sar, blanking window and frequency jier. I also provides he flexibiliy o increase he blanking window by simply adding capaciance in BA pin. However, he proven ousanding feaures in CoolSET -F3 are remained. The inelligen Acive Burs Mode a Sandby Mode can effecively obain he lowes Sandby Power a minimum load and no load condiion. Afer enering he burs mode, here is sill a full conrol of he power conversion by he secondary side via he same opocoupler ha is used for he normal PWM conrol. The response on load jumps is opimized. The volage ripple on V ou is minimized. V ou is on well conrolled in his mode. The usually exernal conneced RC-filer in he feedback line afer he opocoupler is inegraed in he IC o reduce he exernal par coun. Furhermore a high volage Sarup Cell is inegraed ino he IC which is swiched off once he Undervolage Lockou on-hreshold of 18V is exceeded. This Sarup Cell is par of he inegraed CoolMOS. The exernal sarup resisor is no longer necessary as his Sarup Cell is conneced o he Drain. Power losses are herefore reduced. This increases he efficiency under ligh load condiions drasically. This version is adoping he BiCMOS echnology and i can increase design flexibiliy as he Vcc volage range is increased o 25V. For his full package version, he sof sar is a buil-in funcion. I is se a 20ms. Then i can save exernal componen couns. There are 2 modes of blanking ime for high load jumps; he basic mode and he exendable mode. The blanking ime for he basic mode is pre-se a 20ms while he exendable mode will increase he blanking ime a basic mode by adding exernal capacior a he BA pin. During his ime window he overload deecion is disabled. Wih his concep no furher exernal componens are necessary o adjus he blanking window. In order o increase he robusness and safey of he sysem, he IC provides Auo Resar proecion mode. The Auo Resar Mode reduces he average power conversion o a minimum under unsafe operaing condiions. This is necessary for a prolonged faul condiion which could oherwise lead o a desrucion of he SMPS over ime. Once he malfuncion is removed, normal operaion is auomaically recovered afer he nex Sar Up Phase. The inernal precise peak curren limiaion reduces he coss for he ransformer and he secondary diode. The influence of he change in he inpu volage on he power limiaion can be avoided ogeher wih he inegraed Propagaion Delay Compensaion. Therefore he maximum power is nearly independen on he inpu volage which is required for wide range SMPS. There is no need for an exra over-sizing of he SMPS, e.g. he ransformer or he secondary diode. Furhermore, his full package version implemens he frequency jier mode o he swiching clock such ha he EMI noise will be effecively reduced. 3.2 Power Managemen Drain Figure 3 Power Managemen Inernal Bias Power-Down Rese Sof Sar block Sarup Cell Power Managemen Undervolage Lockou 18V 10.5V Volage Reference Auo Resar Mode Acive Burs Mode CoolMOS VCC 5.0V The Undervolage Lockou moniors he exernal supply volage V VCC. When he SMPS is plugged o he main line he inernal Sarup Cell is biased and sars o charge he exernal capacior C VCC which is conneced o he VCC pin. This VCC charge curren is conrolled o 0.9mA by he Sarup Cell. When he V VCC exceeds he on-hreshold V CCon =18V he bias circui are swiched on. Then he Sarup Cell is swiched off by he Undervolage Lockou and herefore no power Version May 2011

9 Funcional Descripion losses presen due o he connecion of he Sarup Cell o he Drain volage. To avoid unconrolled ringing a swich-on a hyseresis sar up volage is implemened. The swich-off of he conroller can only ake place afer Acive Mode was enered and V VCC falls below 10.5V. The maximum curren consumpion before he conroller is acivaed is abou 150mA. When V VCC falls below he off-hreshold V CCoff =10.5V, he bias circui is swiched off and he sof sar couner is rese. Thus i is ensured ha a every sarup cycle he sof sar sars a zero. The inernal bias circui is swiched off if Auo Resar Mode is enered. The curren consumpion is hen reduced o 250mA. Once he malfuncion condiion is removed, his block will hen urn back on. The recovery from Auo Resar Mode does no require re-cycling he AC line. When Acive Burs Mode is enered, he inernal Bias is swiched off mos of he ime in order o reduce he curren consumpion below 500mA. 3.3 Improved Curren Mode FB Figure 4 Sof-Sar Comparaor 0.68V C8 PWM OP x3.3 Improved Curren Mode Curren Mode PWM-Lach Curren Mode means he duy cycle is conrolled by he slope of he primary curren. This is done by comparing he FB signal wih he amplified curren sense signal. R S CS Q Q Driver Amplified Curren Signal FB 0.68V Driver Figure 5 on Pulse Widh Modulaion In case he amplified curren sense signal exceeds he FB signal he on-ime on of he driver is finished by reseing he PWM-Lach (see Figure 5). The primary curren is sensed by he exernal series resisor R Sense insered in he source of he inegraed CoolMOS. By means of Curren Mode regulaion, he secondary oupu volage is insensiive o he line variaions. The curren waveform slope will change wih he line variaion, which conrols he duy cycle. The exernal R Sense allows an individual adjusmen of he maximum source curren of he inegraed CoolMOS. To improve he Curren Mode during ligh load condiions he amplified curren ramp of he PWM-OP is superimposed on a volage ramp, which is buil by he swich T2, he volage source V1 and a resisor R1 (see Figure 6). Every ime he oscillaor shus down for maximum duy cycle limiaion he swich T2 is closed by V OSC. When he oscillaor riggers he Gae Driver, T2 is opened so ha he volage ramp can sar. In case of ligh load he amplified curren ramp is oo small o ensure a sable regulaion. In ha case he Volage Ramp is a well defined signal for he comparison wih he FB-signal. The duy cycle is hen conrolled by he slope of he Volage Ramp. By means of he ime delay circui which is riggered by he invered V OSC signal, he Gae Driver is swiched-off unil i reaches approximaely 156ns delay ime (see Figure 7). I allows he duy cycle o be reduced coninuously ill 0% by decreasing V FB below ha hreshold. Version May 2011

10 Funcional Descripion FB Sof-Sar Comparaor Oscillaor V OSC T 2 R 1 Volage Ramp PWM Comparaor C8 ime delay circui (156ns) 0.68V 10k V 1 PWM-Lach Gae Driver X3.3 PWM OP PWM-OP The inpu of he PWM-OP is applied over he inernal leading edge blanking o he exernal sense resisor R Sense conneced o pin CS. R Sense convers he source curren ino a sense volage. The sense volage is amplified wih a gain of 3.3 by PWM OP. The oupu of he PWM-OP is conneced o he volage source V 1. The volage ramp wih he superimposed amplified curren signal is fed ino he posiive inpus of he PWM- Comparaor C8 and he Sof-Sar-Comparaor (see Figure 6) PWM-Comparaor The PWM-Comparaor compares he sensed curren signal of he inegraed CoolMOS wih he feedback signal V FB (see Figure 8). V FB is creaed by an exernal opocoupler or exernal ransisor in combinaion wih he inernal pull-up resisor R FB and provides he load informaion of he feedback circuiry. When he amplified curren signal of he inegraed CoolMOS exceeds he signal V FB he PWM-Comparaor swiches off he Gae Driver. Figure 6 V OSC Improved Curren Mode max. Duy Cycle R FB FB 5V Sof-Sar Comparaor PWM-Lach C8 PWM Comparaor Volage Ramp 0.68V FB Opocoupler 0.68V PWM OP X3.3 CS Gae Driver 156ns ime delay Improved Curren Mode Figure 8 PWM Conrolling Figure 7 Ligh Load Condiions Version May 2011

11 Funcional Descripion 3.4 Sarup Phase S of S ar couner When he V VCC exceeds he on-hreshold volage, he IC sars he Sof Sar mode (see Figure 10). The funcion is realized by an inernal Sof Sar resisor, an curren sink and a couner. And he ampliude of he curren sink is conrolled by he couner (see Figure 11). Sof Sar finish S ofs C 7 S of S ar S of S ar S of-s ar C om paraor & G ae D river SofS 5V R SofS G V P W M O P x3.3 C S Sof Sar Couner 32I 8I 4I 2I I Figure 9 Sof Sar In he Sarup Phase, he IC provides a Sof Sar period o conrol he primary curren by means of a duy cycle limiaion. The Sof Sar funcion is a buil-in funcion and i is conrolled by an inernal couner.. Figure 11 Sof Sar Circui Afer he IC is swiched on, he V SOFTS volage is conrolled such ha he volage is increased sepwisely (32 seps) wih he increase of he couns. The Sof Sar couner would send a signal o he curren sink conrol in every 600us such ha he curren sink decrease gradually and he duy raio of he gae drive increases gradually. The Sof Sar will be finished in 20ms ( Sof-Sar ) afer he IC is swiched on. A he end of he Sof Sar period, he curren sink is swiched off. V SofS V SOFTS32 Sof-Sar V SofS V SofS2 V SofS1 Gae Driver Figure 10 Sof Sar Phase Figure 12 Gae drive signal under Sof-Sar Phase Version May 2011

12 Funcional Descripion Wihin he sof sar period, he duy cycle is increasing from zero o maximum gradually (see Figure 12). In addiion o Sar-Up, Sof-Sar is also acivaed a each resar aemp during Auo Resar. 3.5 PWM Secion Oscillaor 0.75 PWM Secion V SOFTS32 V SofS Sof-Sar Duy Cycle max Clock Frequency Jier V FB 4.5V V OUT Sof Sar Block Sof Sar Comparaor PWM Comparaor 1 G8 FF1 S R Q Gae Driver & G9 V OUT Sar-Up Curren Limiing CoolMOS Gae Figure 13 Sar Up Phase The Sar-Up ime Sar-Up before he converer oupu volage V OUT is seled, mus be shorer han he Sof- Sar Phase Sof-Sar (see Figure 13). By means of Sof-Sar here is an effecive minimizaion of curren and volage sresses on he inegraed CoolMOS, he clamp circui and he oupu overshoo and i helps o preven sauraion of he ransformer during Sar-Up. Figure 14 PWM Secion Block Oscillaor The oscillaor generaes a fixed frequency of 67KHz wih frequency jiering of ±4% (which is ±2.7KHz) a a jiering period of 4ms. A capacior, a curren source and curren sink which deermine he frequency are inegraed. The charging and discharging curren of he implemened oscillaor capacior are inernally rimmed, in order o achieve a very accurae swiching frequency. The raio of conrolled charge o discharge curren is adjused o reach a maximum duy cycle limiaion of D max =0.75. Once he Sof Sar period is over and when he IC goes ino normal operaing mode, he swiching frequency of he clock is varied by he conrol signal from he Sof Sar block. Then he swiching frequency is varied in range of 67KHz ± 2.7KHz a period of 4ms PWM-Lach FF1 The oupu of he oscillaor block provides coninuous pulse o he PWM-Lach which urns on/off he inernal CoolMOS. Afer he PWM-Lach is se, i is rese by he PWM comparaor, he Sof Sar comparaor or he Curren -Limi comparaor. When i is in rese mode, he oupu of he driver is shu down immediaely. Version May 2011

13 Funcional Descripion Gae Driver VCC 3.6 Curren Limiing PWM Lach FF1 Curren Limiing PWM-Lach 1 Gae Propagaion-Delay Compensaion Gae Driver Figure 15 Gae Driver CoolMOS The driver-sage is opimized o minimize EMI and o provide high circui efficiency. This is done by reducing he swich on slope when exceeding he inernal CoolMOS hreshold. This is achieved by a slope conrol of he rising edge a he driver s oupu (see Figure 9). PWM-OP & G10 Acive Burs Mode C10 C12 V csh 0.26V 10k D1 Leading Edge Blanking 220ns 1pF (inernal) V Gae 5V Figure 16 Gae Rising Slope ca. = 130ns Thus he leading swich on spike is minimized. Furhermore he driver circui is designed o eliminae cross conducion of he oupu sage. During power up, when VCC is below he undervolage lockou hreshold V VCCoff, he oupu of he Gae Driver is se o low in order o disable power ransfer o he secondary side. Figure 17 CS Curren Limiing Block There is a cycle by cycle peak curren limiing operaion realized by he Curren-Limi comparaor C10. The source curren of he inegraed CoolMOS is sensed via an exernal sense resisor R Sense. By means of R Sense he source curren is ransformed o a sense volage V Sense which is fed ino he pin CS. If he volage V Sense exceeds he inernal hreshold volage V csh, he comparaor C10 immediaely urns off he gae drive by reseing he PWM Lach FF1. A Propagaion Delay Compensaion is added o suppor he immediae shu down of he inegraed CoolMOS wih very shor propagaion delay. Thus he influence of he AC inpu volage on he maximum oupu power can be reduced o minimal. In order o preven he curren limi from disorions caused by leading edge spikes, a Leading Edge Blanking is inegraed in he curren sense pah for he comparaors C10, C12 and he PWM-OP. The oupu of comparaor C12 is acivaed by he Gae G10 if Acive Burs Mode is enered. When i is acivaed, he curren limiing is reduced o 0.26V. This volage level deermines he maximum power level in Acive Burs Mode. Version May 2011

14 Funcional Descripion Leading Edge Blanking V Sense V csh LEB = 220ns For example, I peak = 0.5A wih R Sense = 2. The curren sense hreshold is se o a saic volage level V csh =1V wihou Propagaion Delay Compensaion. A curren ramp of di/d = 0.4A/µs, or dv Sense /d = 0.8V/µs, and a propagaion delay ime of Propagaion Delay =180ns leads o an I peak overshoo of 14.4%. Wih he propagaion delay compensaion, he overshoo is only around 2% (see Figure 20). wih compensaion wihou compensaion Figure 18 Leading Edge Blanking Whenever he inernal CoolMOS is swiched on, a leading edge spike is generaed due o he primaryside capaciances and reverse recovery ime of he secondary-side recifier. This spike can cause he gae drive o swich off uninenionally. In order o avoid a premaure erminaion of he swiching pulse, his spike is blanked ou wih a ime consan of LEB = 220ns Propagaion Delay Compensaion In case of overcurren deecion, here is always propagaion delay o swich off he inernal CoolMOS. An overshoo of he peak curren I peak is induced o he delay, which depends on he raio of di/d of he peak curren (see Figure 19). I peak2 I peak1 I Limi I Sense Signal2 I Overshoo2 Signal1 Propagaion Delay I Overshoo1 V Sense V 1,3 1,25 1,2 1,15 1,1 1,05 1 0,95 Figure 20 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 Overcurren Shudown The Propagaion Delay Compensaion is realized by means of a dynamic hreshold volage V csh (see Figure 21). In case of a seeper slope he swich off of he driver is earlier o compensae he delay. V OSC V csh V Sense max. Duy Cycle dv Sense d off ime Propagaion Delay V s Figure 19 Curren Limiing The overshoo of Signal2 is larger han of Signal1 due o he seeper rising waveform. This change in he slope is depending on he AC inpu volage. Propagaion Delay Compensaion is inegraed o reduce he overshoo due o di/d of he rising primary curren. Thus he propagaion delay ime beween exceeding he curren sense hreshold V csh and he swiching off of he inegraed CoolMOS is compensaed over emperaure wihin a wide range. Curren Limiing is hen very accurae. Figure 21 Signal1 Dynamic Volage Threshold V csh 3.7 Conrol Uni Signal2 The Conrol Uni conains he funcions for Acive Burs Mode and Auo Resar Mode. The Acive Burs Mode and he Auo Resar Mode boh have 20ms inernal Blanking Time. For he Auo Resar Mode, a furher exendable Blanking Time is achieved by adding Version May 2011

15 Funcional Descripion exernal capacior a BA pin. By means of his Blanking Time, he IC avoids enering ino hese wo modes accidenally. Furhermore hose buffer ime for he overload deecion is very useful for he applicaion ha works in low curren bu requires a shor duraion of high curren occasionally Basic and Exendable Blanking Mode BA # C BK I BK S1 0.9V 1 G2 5.0V In order o make he sarup properly, he maximum C BK capacior is resriced o less han 0.65uF. The Acive Burs Mode has basic blanking mode only while he Auo Resar Mode has boh he basic and he exendable blanking mode Acive Burs Mode The IC eners Acive Burs Mode under low load condiions. Wih he Acive Burs Mode, he efficiency increases significanly a ligh load condiions while sill mainaining a low ripple on V OUT and a fas response on load jumps. During Acive Burs Mode, he IC is conrolled by he FB signal. Since he IC is always acive, i can be a very fas response o he quick change a he FB signal. The Sar up Cell is kep OFF in order o minimize he power loss. 4.0V 4.5V C3 C4 20ms Blanking Time & G5 Spike Blanking 30us Auo Resar Mode 4.5V C4 20 ms Blanking Time Inernal Bias Curren Limiing & G10 FB 1.22V C5 20ms Blanking Time & G6 Acive Burs Mode FB 1.22V C5 & G6 Acive Burs Mode Conrol Uni Figure 22 Basic and Exendable Blanking Mode There are 2 kinds of Blanking mode; basic mode and he exendable mode. The basic mode is jus an inernal pre-se 20ms blanking ime while he exendable mode has exra blanking ime by connecing an exernal capacior o he BA pin in addiion o he pre-se 20ms blanking ime. For he exendable mode, he gae G5 is blocked even hough he 20ms blanking ime is reached if an exernal capacior C BK is added o BA pin. While he 20ms blanking ime is passed, he swich S1 is opened by G2. Then he 0.9V clamped volage a BA pin is charged o 4.0V hrough he inernal I BK consan curren. Then G5 is enabled by comparaor C3. Afer he 30us spike blanking ime, he Auo Resar Mode is acivaed. For example, if C BK = 0.22uF, I BK = 13.5uA Blanking ime = 20ms + C BK x ( ) / I BK = 70ms Figure V 3.1V C6a C6b Conrol Uni Acive Burs Mode The Acive Burs Mode is locaed in he Conrol Uni. Figure 23 shows he relaed componens Enering Acive Burs Mode The FB signal is kep monioring by he comparaor C5. During normal operaion, he inernal blanking ime couner is rese o 0. When FB signal falls below 1.22V, i sars o coun. When he couner reach 20ms and FB signal is sill below 1.22V, he sysem eners he Acive Burs Mode. This ime window prevens a sudden enering ino he Acive Burs Mode due o large load jumps. & G11 Version May 2011

16 Funcional Descripion Afer enering Acive Burs Mode, a burs flag is se and he inernal bias is swiched off in order o reduce he curren consumpion of he IC o approx. 500uA. I needs he applicaion o enforce he VCC volage above he Undervolage Lockou level of 10.5V such ha he Sarup Cell will no be swiched on accidenally. Or oherwise he power loss will increase drasically. The minimum VCC level during Acive Burs Mode depends on he load condiion and he applicaion. The lowes VCC level is reached a no load condiion Working in Acive Burs Mode Afer enering he Acive Burs Mode, he FB volage rises as V OUT sars o decrease, which is due o he inacive PWM secion. The comparaor C6a moniors he FB signal. If he volage level is larger han 3.6V, he inernal circui will be acivaed; he Inernal Bias circui resumes and sars o provide swiching pulse. In Acive Burs Mode he gae G10 is released and he curren limi is reduced o 0.26V. In one hand, i can reduce he conducion loss and he oher hand, i can reduce he audible noise. If he load a V OUT is sill kep unchanged, he FB signal will drop o 3.1V. A his level he C6b deacivaes he inernal circui again by swiching off he inernal Bias. The gae G11 is acive again as he burs flag is se afer enering Acive Burs Mode. In Acive Burs Mode, he FB volage is changing like a saw ooh beween 3.1V and 3.6V (see figure 17). V FB 4.5V 3.6V 3.1V 1.22V Blanking Timer V CS 1.0V 0.26V V VCC Enering Acive Burs Mode 20ms Blanking Time Curren limi level during Acive Burs Mode Leaving Acive Burs Mode Leaving Acive Burs Mode The FB volage will increase immediaely if here is a high load jump. This is observed by he comparaor C4. As he curren limi is appr. 26% during Acive Burs Mode, a cerain load jump is needed so ha he FB signal can exceed 4.5V. A ha ime he comparaor C4 reses he Acive Burs Mode conrol which in urn blocks he comparaor C12 by he gae G10. The maximum curren can hen be resumed o sabilize V OUT. 10.0V I VCC 2.9mA 500uA V OUT Max. Ripple < 1% Figure 24 Signals in Acive Burs Mode Version May 2011

17 Funcional Descripion Proecion Modes The IC provides Auo Resar Mode as he proecion feaure. Auo Resar mode can preven he SMPS from desrucive saes. The following able shows he relaionship beween possible sysem failures and he chosen proecion modes. VCC Overvolage Overemperaure Overload Open Loop VCC Undervolage Shor Opocoupler Exernal auo resar enable Auo Resar Mode Auo Resar Mode Auo Resar Mode Auo Resar Mode Auo Resar Mode Auo Resar Mode Auo Resar Mode Before enering he Auo Resar proecion mode, some of he proecions can have exended blanking ime o delay he proecion and some needs o fas reac and will go sraigh o he proecion. Overload and open loop proecion are he one can have exended blanking ime while Vcc Overvolage, Over emperaure, Vcc Undervolage, shor opo-coupler and exernal auo resar enable will go o proecion righ away. Afer he sysem eners he Auo-resar mode, he IC will be off. Since here is no more swiching, he Vcc volage will drop. When i his he Vcc urn off hreshold, he sar up cell will urn on and he Vcc is charged by he sarup cell curren o Vcc urn on hreshold. The IC is on and he sarup cell will urn off. A his sage, i will ener he sarup phase (sof sar) wih swiching cycles. Afer he Sar Up Phase, he faul condiion is checked. If he faul condiion persiss, he IC will go o auo resar mode again. If, oherwise, he faul is removed, normal operaion is resumed Auo Resar mode wih exended blanking ime BA # C BK I BK Figure V 4.5V FB S1 0.9V C3 C4 1 G2 5.0V 20ms Blanking Time Auo Resar Mode In case of Overload or Open Loop, he FB exceeds 4.5V which will be observed by comparaor C4. Then he inernal blanking couner sars o coun. When i reaches 20ms, he swich S1 is released. Then he clamped volage 0.9V a V BA can increase. When here is no exernal capacior C BK conneced, he V BA will reach 4.0V immediaely. When boh he inpu signals a AND gae G5 is posiive, he Auo Resar Mode will be acivaed afer he exra spike blanking ime of 30us is elapsed. However, when an exra blanking ime is needed, i can be achieved by adding an exernal capacior, C BK. A consan curren source of I BK will sar o charge he capacior C BK from 0.9V o 4.0V afer he swich S1 is released. The charging ime from 0.9V o 4.0V are he exendable blanking ime. If C BK is 0.22uF and I BK is 13.5uA, he exendable blanking ime is around 50ms and he oal blanking ime is 70ms. In combining he FB and blanking ime, here is a blanking window generaed which prevens he sysem o ener Auo Resar Mode due o large load jumps. & G5 Spike Blanking 30us Auo Resar Mode Conrol Uni Version May 2011

18 Funcional Descripion Auo Resar wihou exended blanking ime Auo-resar Enable Signal T AE BA 0.33V 25.5V VCC C9 C2 1ms couner 120us Blanking Time UVLO Sop gae drive AuoResar ModeRese V VCC <10.5V AuoResar mode a rigger signal o he base of he exernally added ransisor, T AE a he BA pin. When he funcion is enabled, he gae drive swiching will be sopped and hen he IC will ener auo-resar mode if he signal persiss. To ensure his auo-resar funcion will no be mis-riggered during sar up, a 1ms delay ime is implemened o blank he unsable signal. VCC undervolage is he Vcc volage drop below Vcc urn off hreshold. Then he IC will urn off and he sar up cell will urn on auomaically. And his leads o Auo Resar Mode. Shor Opocoupler also leads o VCC undervolage. When he FB pin is pulled low, here is no swiching pulse. Then he Vcc will drop o Vcc urn off hreshold. And i leads o Auo Resar Mode. VCC 20.7V sofs_period C1 & G1 Spike Blanking 30us FB 4.5V C4 Thermal Shudown Volage Reference T j >130 C Conrol Uni Figure 26 Auo Resar mode There are 2 modes of V CC overvolage proecion; one is during sof sar and he oher is a all condiions. The firs one is V VCC volage is > 20.7V and FB is > 4.5V and during sof_sar period and he IC eners Auo Resar Mode. The VCC volage is observed by comparaor C1. The faul condiions are o deec he abnormal operaing during sar up such as open loop during ligh load sar up, ec. The logic can eliminae he possible of enering Auo Resar mode if here is a small volage overshoos of V VCC during normal operaing. The 2nd one is V VCC >25.5V and las for 120us and he IC eners Auo Resar Mode. This 25.5V Vcc OVP proecion is inacivaed during burs mode. The Thermal Shudown block moniors he juncion emperaure of he IC. Afer deecing a juncion emperaure higher han 130 C, he Auo Resar Mode is enered. In case he pre-defined auo-resar feaures are no sufficien, here is a cusomer defined exernal Auoresar Enable feaure. This funcion can be riggered by pulling down he BA pin o < 0.33V. I can simply add Version May 2011

19 Elecrical Characerisics 4 Elecrical Characerisics Noe: All volages are measured wih respec o ground (Pin 5). The volage levels are valid if oher raings are no violaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 4 (VCC) is discharged before assembling he applicaion circui.t a =25 C unless oherwise specified. Parameer Symbol Limi Values Uni Remarks Swiching drain curren, pulse widh p limied by max. T j =150 C Pulse drain curren, pulse widh p limied by max. T j =150 C Avalanche energy, repeiive AR limied by max. T j =150 C 1) min. max. I s A I D_Puls - 13 A E AR mj I D =3A Avalanche curren, repeiive AR limied I AR - 3 A by max. T j =150 C 1) VCC Supply Volage V VCC V FB Volage V FB V BA Volage V BA V CS Volage V CS V Juncion Temperaure T j C Conroller & CoolMOS Sorage Temperaure T S C Thermal Resisance Juncion -Ambien Thermal Resisance Juncion -case Soldering emperaure, wavesoldering only allowed a leads R hja - 82 K/W R hjc K/W T sold C 1.6mm (0.063 in.) from case for 10s Power dissipaion, T c =25 C P o - 28 W Refer o Figure 57 ESD Capabiliy (incl. Drain Pin) V ESD - 2 kv Human body model 2) Mouning orque 60 Ncm M2.5 screws 1) Repeiive avalanche causes addiional power losses ha can be calculaed as P AV =E AR *f 2) According o EIA/JESD22-A114-B (discharging a 100pF capacior hrough a 1.5kW series resisor) Version May 2011

20 Elecrical Characerisics 4.2 Operaing Range Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Parameer Symbol Limi Values Uni Remarks min. max. VCC Supply Volage V VCC V VCCoff 25 V Max. value limied due o Vcc OVP Juncion Temperaure of Conroller T jcon C Max value limied due o hermal shu down of conroller Juncion Temperaure of T jcoolmos C CoolMOS 4.3 Characerisics Supply Secion Noe: The elecrical characerisics involve he spread of values wihin he specified supply volage and juncion emperaure range T J from 25 C o 125 C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of V CC = 18 V is assumed. Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sar Up Curren I VCCsar ma V VCC =17V VCC Charge Curren I VCCcharge ma V VCC = 0V I VCCcharge ma V VCC = 1V I VCCcharge ma V VCC =17V Leakage Curren of I SarLeak ma V Drain = 600V Sar Up Cell and CoolMOS a T j =100 C 1) Supply Curren wih Inacive Gae I VCCsup ma Supply Curren wih Acive Gae I VCCsup ma I FB = 0A Supply Curren in Auo Resar Mode wih Inacive Gae Supply Curren in Acive Burs Mode wih Inacive Gae I VCCresar ma I FB = 0A I VCCburs ma V FB = 2.5V I VCCburs ma V VCC = 11.5V,V FB = 2.5V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hyseresis V VCCon V VCCoff V VCChys V V V 1) The parameer is no subjeced o producion es - verified by design/characerizaion Version May 2011

21 Elecrical Characerisics Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V REF V measured a pin FB I FB = PWM Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Fixed Oscillaor Frequency f OSC khz f OSC khz T j = 25 C Frequency Jiering Range f jier - ±2.7 - khz T j = 25 C Frequency Jiering period T jier ms T j = 25 C Max. Duy Cycle D max Min. Duy Cycle D min V FB < 0.3V PWM-OP Gain A V Volage Ramp Offse V Offse-Ramp V V FB Operaing Range Min Level V FBmin V V FB Operaing Range Max level V FBmax V CS=1V, limied by Comparaor C4 1) FB Pull-Up Resisor R FB kw 1) The parameer is no subjeced o producion es - verified by design/characerizaion Sof Sar ime Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sof Sar ime SS ms V FB > 4.0V Version May 2011

22 Elecrical Characerisics Conrol Uni Parameer Symbol Limi Values Uni Tes Condiion Clamped V BA volage during Normal Operaing Mode Blanking ime volage limi for Comparaor C3 Over Load & Open Loop Deecion Limi for Comparaor C4 Acive Burs Mode Level for Comparaor C5 Acive Burs Mode Level for Comparaor C6a Acive Burs Mode Level for Comparaor C6b Overvolage Deecion Limi for Comparaor C1 min. yp. max. V BAclmp V V FB = 4V V BKC V V FBC V V FBC V V FBC6a V Afer Acive Burs Mode is enered V FBC6b V Afer Acive Burs Mode is enered V VCCOVP V V FB = 5V Overvolage Deecion Limi for Comparaor C2 V VCCOVP V Auo-resar Enable level a BA pin for Comparaor C9 V AE V Charging curren a BA pin I BK ma Charge sars afer he buil-in 20ms blanking ime elapsed Thermal Shudown 1) T jsd C Conroller Buil-in Blanking Time for Overload Proecion or ener Acive Burs Mode Inhibi Time for Auo-Resar enable funcion during sar up Spike Blanking Time before Auo Resar Proecion BK ms wihou exernal capacior a BA pin IHAE ms Coun when VCC>18V Spike ms 1) The parameer is no subjeced o producion es - verified by design/characerizaion Noe: The rend of all he volage levels in he Conrol Uni is he same regarding he deviaion excep V VCCOVP and V VCCPD Version May 2011

23 Elecrical Characerisics Curren Limiing Parameer Symbol Limi Values Uni Tes Condiion Peak Curren Limiaion (incl. Propagaion Delay) Peak Curren Limiaion during Acive Burs Mode min. yp. max. V csh V dv sense / d = 0.6V/ms (see Figure 13) V CS V Leading Edge Blanking LEB ns CS Inpu Bias Curren I CSbias ma V CS =0V CoolMOS Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Drain Source Breakdown Volage V (BR)DSS V T j = 110 C 1) (Refer o Figure 65 for oher V (BR)DSS in differen T j ) V GS =0V, I D =0.25mA Drain Source Avalanche Breakdown Volage Drain Source On-Resisance R DSon Effecive oupu capaciance, energy relaed V (BR)DS V V GS =0V, I D =3A Rise Time rise ) 1) The parameer is no subjeced o producion es - verified by design/characerizaion 2) Measured in a Typical Flyback Converer Applicaion W W W T j = 25 C T j =125 C 1) T j =150 C 1) a I D = 2.6A C o(er) pf V DS = 0V o 480V 1) - ns Fall Time fall ) - ns Version May 2011

24 Typical Conroller Performance Characerisics 5 Typical Conroller Performance Characerisics Sar Up Curren I VCCsar [µa] PI A23 Vcc Charge Curren I VCCcharge3 [ma] PI A23 Figure 27 Sar Up Curren I VCCsar Figure 30 VCC Charge Curren I VCCcharge Vcc Charge Curren I VCCcharge1 [ma] Figure 28 VCC Charge Curren I VCCcharge1 PI A23 Vcc Supply Curren I VCCsup1 [ma] Figure 31 VCC Supply Curren I VCCsup1 PI A23 Vcc Charge Curren I VCCcharge2 [ma] Figure 29 VCC Charge Curren I VCCcharge2 PI A23 Vcc Supply Curren I VCCsup2 [ma] Figure 32 VCC Supply Curren I VCCsup2 PI A12_ Version May 2011

25 Typical Conroller Performance Characerisics Vcc Supply Curren I VCCresar [ua] PI A23 Vcc Turn-Off Threshold V VCCoff [V] PI A23 Figure 33 VCC Supply Curren I VCCresar Figure 36 VCC Turn-Off Threshold V VCCoff Vcc Supply Curren I VCCburs [ua] Figure 34 VCC Supply Curren I VCCburs PI A23 Reference Volage V REF [V] Figure 37 Reference Volage V REF PI A23 Vcc Turn-On hreshold V VCCon [V] Figure 35 VCC Turn-On Threshold V VCCon PI A23 Oscillaor Frequency f osc1 [khz] Figure 38 Oscillaor Frequency f OSC1 PI A23 Version May 2011

26 Typical Conroller Performance Characerisics Frequency Jier Range f jier [+/-khz] Figure 39 Frequency Jiering Range f jier PI A23 Volage Ramp Offse V Offse-Ramp [V] Figure 42 Volage Ramp Offse V Offse-Ramp PI A23 Max. Duy Cycle D max Figure 40 Max. Duy Cycle D max PI A23 Feedback Pull-Up resisor R FB [kohm] Figure 43 Feedback Pull-Up resisor R FB PI A23 PWM OP Gain A V Figure 41 PWM-OP Gain A V PI A23 Clamped VBA Volage V BAclmp [V] Figure 44 Clamped V BA volage V BAclmp PI A23 Version May 2011

27 Typical Conroller Performance Characerisics Blanking ime volage limi V BKC3 [V] Figure 45 Blanking ime volage limi V BKC3 PI A23 Acive Burs Model Leve V FBC6a [V] Figure 48 Acive Burs Mode Level V FBC6a PI A23 Over Load deecion limi V FBC4 [V] Figure 46 Over Load Deecion Limi V FBC4 PI A23 Acive Burs Mode Level V FBC6b [V] Figure 49 Acive Burs Mode Level V FBC6b PI A23 Acive Burs mode Level V FBC5 [V] Figure 47 Acive Burs Mode Level V FBC5 PI A23 Overvolage Deecion Limi V VCCovp1 [V] Figure 50 Overvolage Deecion Limi V VCCOVP1 PI A23 Version May 2011

28 Typical Conroller Performance Characerisics Overvolage Deecion Level V VCCOVP2 [V] Figure 51 Over Load Deecion Limi V VCCOVP2 PI A23 Peak Curren Limiaion V CSh [V] Figure 54 Peak Curren Limiaion V csh PI A23 Auo-resar Enable Level V AE [V] Figure 52 Auo-resar Enable Level V AE PI A23 Peak Curren Limiaion V CS2 [V] Figure 55 Peak Curren Limiaion V CS2 PI A23 Charging Curren a BA pin I BK [µa] Figure 53 Charging Curren a BA pin I BK PI A23 Leading Edge Blanking LEB [ns] Figure 56 Leading Edge Blanking LEB PI A23 Version May 2011

29 Typical CoolMOS Performance Characerisics 6 Typical CoolMOS Performance Characerisics Figure 57 Power dissipaion; P o =f(t C ) Figure 60 Typ. oupu characerisics; I D =f(v DS ),T j =25 C, parameer : V CC limied by on-sae resisance Figure 58 Safe operaion area; I D =f(v DS ), parameer : D=0, T C =25 C Figure 61 Typ. oupu characerisics; I D =f(v DS ),T j =150 C, parameer : V CC Figure 59 Transien hermal impedance; Z hjc =f( p ),parameer: D= p /T Figure 62 Typ. drain-source on-sae resisance; R DS(on) =f(i D ); T j =150 C, parameer : V CC Version May 2011

30 Typical CoolMOS Performance Characerisics Figure 63 Drain-source on-sae resisance; R DS(on) =f(t j ); I D =2.6A;, V cc >10.5V Figure 66 Typ. capaciances; C=f(V DS ),V GS =0V,f=1MHz Figure 64 Avalanche energy; E AS =f(t j ),I D =1.7A,V DD =50V Figure 67 Typ. Coss sored energy; E oss =f(v DS ) Figure 65 Drain-source breakdown volage; V BR(DSS) =f(t j ), I D =0.25mA Version May 2011

31 Inpu Power Curve 7 Inpu Power Curve Two inpu power curves giving he ypical inpu power versus ambien emperaure are showed below; Vin=85Vac~265Vac (Figure 68) and Vin=230Vac+/-15% (Figure 69). The curves are derived based on a ypical disconinuous mode flyback model which considers eiher 50% maximum duy raio or 100V maximum secondary o primary refleced volage (higher prioriy). The calculaion is based on R hsa =2.7K/W as heasink and R hcs =1.1K/W as hermal grease hermal resisance. The inpu power already includes he power loss a inpu common mode choke, bridge recifier and he CoolMOS. The device sauraion curren (I T j =125 C) is also considered. To esimae he oupu power of he device, i is simply muliplying he inpu power a a paricular operaing ambien emperaure wih he esimaed efficiency for he applicaion. For example, a wide range inpu volage (Figure 68), operaing emperaure is 50 C, esimaed efficiency is 80%, hen he esimaed oupu power is 96W (120W * 80%) Inpu power (85~265Vac) [W] PI-003-_85Vac Ambien Temperaure [ C] Figure 68 Inpu power curve Vin=85~265Vac; P in =f(t a ) Inpu power (230Vac) [W] PI-004-_230Vac Ambien Temperaure [ C] Figure 69 Inpu power curve Vin=230Vac+/-15%; P in =f(t a ) Version May 2011

32 Ouline Dimension 8 Ouline Dimension PG-TO (PB-free Plaing FullPak Package Ouline) Figure 70 PG-TO (PB-free Plaing FullPak Package) Dimensions in mm Version May 2011

33 Marking 9 Marking Marking Figure 71 Marking for Version May 2011

34 Schemaic for recommended PCB layou 10 Schemaic for recommended PCB layou Figure 72 Schemaic for recommended PCB layou General guideline for PCB layou design using F3/F3R CoolSET (refer o Figure 72): 1. Sar Ground a bulk capacior ground, C11: Sar Ground means all primary DC grounds should be conneced o he ground of bulk capacior C11 separaely in one poin. I can reduce he swiching noise going ino he sensiive pins of he CoolSET device effecively. The primary DC grounds include he followings. a. DC ground of he primary auxiliary winding in power ransformer, TR1, and ground of C16 and Z11. b. DC ground of he curren sense resisor, R12 c. DC ground of he CoolSET device, GND pin of IC11; he signal grounds from C13, C14, C15 and collecor of IC12 should be conneced o he GND pin of IC11 and hen sar connec o he bulk capacior ground. d. DC ground from bridge recifier, BR1 e. DC ground from he bridging Y-capacior, C4 2. High volage races clearance: High volage races should keep enough spacing o he nearby races. Oherwise, arcing would incur. a. 400V races (posiive rail of bulk capacior C11) o nearby race: > 2.0mm b. 600V races (drain volage of CoolSET IC11) o nearby race: > 2.5mm 3. Filer capacior close o he conroller ground: Filer capaciors, C13, C14 and C15 should be placed as close o he conroller ground and he conroller pin as possible so as o reduce he swiching noise coupled ino he conroller. Guideline for PCB layou design when >3KV lighning surge es applied (refer o Figure 72): 1. Add spark gap Spark gap is a pair of saw-ooh like copper plae facing each oher which can discharge he accumulaed charge during surge es hrough he sharp poin of he saw-ooh plae. a. Spark Gap 3 and Spark Gap 4, inpu common mode choke, L1: Gap separaion is around 1.5mm (no safey concern) Version May 2011

35 Schemaic for recommended PCB layou b. Spark Gap 1 and Spark Gap 2, Live / Neural o GROUND: These 2 Spark Gaps can be used when he lighning surge requiremen is >6KV. 230Vac inpu volage applicaion, he gap separaion is around 5.5mm 115Vac inpu volage applicaion, he gap separaion is around 3mm 2. Add Y-capacior (C2 and C3) in he Live and Neural o ground even hough i is a 2-pin inpu 3. Add negaive pulse clamping diode, D11 o he Curren sense resisor, R12: The negaive pulse clamping diode can reduce he negaive pulse going ino he CS pin of he CoolSET and reduce he abnormal behavior of he CoolSET. The diode can be a fas speed diode such as IN4148. The principle behind is o drain he high surge volage from Live/Neural o Ground wihou passing hrough he sensiive componens such as he primary conroller, IC11. Version May 2011

36 Toal Qualiy Managemen Qualiä ha für uns eine umfassende Bedeuung. Wir wollen allen Ihren Ansprüchen in der besmöglichen Weise gerech werden. Es geh uns also nich nur um die Produkqualiä unsere Ansrengungen gelen gleichermaßen der Lieferqualiä und Logisik, dem Service und Suppor sowie allen sonsigen Beraungs- und Bereuungsleisungen. Dazu gehör eine besimme Geiseshalung unserer Miarbeier. Toal Qualiy im Denken und Handeln gegenüber Kollegen, Lieferanen und Ihnen, unserem Kunden. Unsere Leilinie is jede Aufgabe mi Null Fehlern zu lösen in offener Sichweise auch über den eigenen Arbeisplaz hinaus und uns sändig zu verbessern. Unernehmenswei orienieren wir uns dabei auch an op (Time Opimized Processes), um Ihnen durch größere Schnelligkei den enscheidenden Webewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leisung durch umfassende Qualiä zu beweisen. Wir werden Sie überzeugen. Qualiy akes on an allencompassing significance a Semiconducor Group. For us i means living up o each and every one of your demands in he bes possible way. So we are no only concerned wih produc qualiy. We direc our effors equally a qualiy of supply and logisics, service and suppor, as well as all he oher ways in which we advise and aend o you. Par of his is he very special aiude of our saff. Toal Qualiy in hough and deed, owards co-workers, suppliers and you, our cusomer. Our guideline is do everyhing wih zero defecs, in an open manner ha is demonsraed beyond your immediae workplace, and o consanly improve. Throughou he corporaion we also hink in erms of Time Opimized Processes (op), greaer speed on our par o give you ha decisive compeiive edge. Give us he chance o prove he bes of performance hrough he bes of qualiy you will be convinced. h p : / / w w w. i n f i n e o n. c o m Published by Infineon Technologies AG