AN1207. Switch Mode Power Supply (SMPS) Topologies (Part II) REQUIREMENTS AND RULES INTRODUCTION CONTENTS. Microchip Technology Inc.

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1 Swich Mode Power Supply (SMPS) opologies (Par II) Auhor: INRODUCION his applicai noe is he secd of a wo-par series Swich Mode Power Supply (SMPS) opologies. he firs applicai noe in his series AN Swich Mode Power Supply (SMPS) opologies (Par I) explains he basics of differen SMPS opologies while guiding he reader in selecing an appropriae opology for a given applicai. Par II of his series expands he previous maerial in Par I and presens he basic ools needed o design a power cverer. All of he opologies inroduced in Par I are covered and afer a brief overview of he basic funcialiy of each equais o design real sysems are presened and analyzed. Before cinuing i is recommended ha you read and become familiar wih Par I of his series. CONENS Anio Bersani Microchip echnology Inc. his applicai noe cains he following major secis: Requiremens and Rules... 1 Buck Cverer... 2 Boos Cverer Forward Cverer wo-swich Forward Cverer Half-Bridge Cverer Push-Pull Cverer Full-Bridge Cverer Flyback Cverer Volage and Curren opologies Cclusi References Source Code REQUIREMENS AND RULES he following requiremens and rules were used o deermine he various compen values used in he design of a power cverer. he general design requiremens are lised as follows: Nominal inpu volage (VDC) Minimum inpu volage (VDC min) Maximum inpu volage (VDC max) Oupu volage (VOU) Nominal average oupu curren (IO av nom) Nominal minimum oupu curren (IO av min) Maximum ripple volage (VR max) In addii a few comm rules were used for compen seleci: MOSFEs (or swiches) mus be able o: - Wihsand he maximum volage - Wihsand he maximum curren - Operae efficienly and correcly a he frequency of he PWM - Operae in he SOA (dependan dissipai) Diodes mus be able o: - Wihsand he maximum reverse volage - Wihsand he average curren Arrows are used in he circui schemaics o represen volages. he volage polariy is no direcly refleced by he arrow iself (meaning if he volage reverses he arrow is no reversed bu ha he value of he volage is negaive) Microchip echnology Inc. DS01207B-page 1

2 BUCK CONVERER he Buck Cverer cvers a high inpu volage ino a lower oupu volage. I is preferred over linear regulaors for is higher efficiency. opology Equais Figure 1 shows he basic opology of a Buck Cverer. he Q1 swich is operaed wih a fixed frequency and variable duy cycle signal. FIGURE 2: VDC Q1 BUCK CONVERER OPOLOGY: OERIOD D1 LO VL CO VOU FIGURE 1: VDC Q1 BUCK CONVERER OPOLOGY Accordingly volage VI is a square-wave s(). he Fourier series of such a signal is shown in Equai 1. EQUAION 1: his means ha he square-wave can be represened as a sum of a DC value and a number of sine waves a differen increasing (muliple) frequencies. If his signal is processed hrough a low-pass filer (Equai 2) he resuling oupu (DC value ly) is received. EQUAION 2: VI D1 A LoCo low-pass filer exracs from he square-wave is DC value and aenuaes he fundamenal and harmics o a desired level. Q1 CLOSED (OERIOD) In his cfigurai he circui is redrawn as shown in Figure 2. he diode is reverse-biased so ha i becomes an open circui. LO VL s () A-- τ + Σsin CO VOU waves_wih_frequency_muliple_of_he_square_wave_frequency where: τ he duy cycle he period A he square-wave ampliude s f () A-- τ cs Based Figure 2 he volage he inducor is as shown in Equai 3. EQUAION 3: V L V DC V Q V OU he inducor curren (having a csan ime derivaive value) is a ramp: ( V DC V Q V OU ) i L () i L ( 0) L O A ime ON equals: ( V DC V Q V OU ) i L ( ON ) i L ( 0) ON Where ON is he durai of he ime inerval when he swich Q1 is closed. Q1 OPEN (OFF PERIOD) As shown in Figure 3 when he swich Q1 opens he inducor will ry o keep he curren flowing as before. FIGURE 3: VDC Q1 BUCK CONVERER OPOLOGY: OFF PERIOD D1 As a resul he volage a he D1 LO Q1 inerseci will abruply ry o become very negaive o suppor he cinuous flow of curren in he same direci (see Figure 4). LO VL L O CO VOU DS01207B-page Microchip echnology Inc.

3 FIGURE 4: VL INDUCOR BEHAVIOR IL During ON he inducor is soring energy ino is magneic field (VL > 0). INPU/OUPU RELAIONSHIP AND DUY CYCLE Wha has been described unil now is called Cinuous mode. o undersand wha i is and is imporance refer o Figure 5(G) which represens he inducor curren. As previously seen here is a ramp-up during ON and a ramp-down during OFF. he average curren can be compued easily using Equai 6. VL During OFF he inducor is releasing energy previously sored (VL < 0). EQUAION 6: I 2 + I I Lav Equai 4 shows he resuling inducor volage while Equai 5 shows he curren. EQUAION 4: IL V L V OU V D he average inducor curren is also he curren flowing o he oupu so he oupu average curren is equal o Equai 7. EQUAION 7: I 2 + I I Oav EQUAION 5: V OU V D i L () i L ( ON ) L O 2009 Microchip echnology Inc. DS01207B-page 3

4 FIGURE 5: BUCK CONVERER WAVEFORMS Q1 Command (A) VDC + VD VQ1 (B) I2 I1 IQ1 (C) VD1 (D) (-VDC + VQ ) I2 I1 ID1 (E) VDC - VOU VL A (F) B -VOU I2 I1 IL (G) ON OFF (A) Command signal and MOSFE gae (B) Volage and MOSFE (C) Curren flowing ino MOSFE (D) Volage D1 diode (E) Curren in D1 diode (F) Volage LO inducor (G) Curren in LO inducor DS01207B-page Microchip echnology Inc.

5 Supposing he oupu load RO (cneced in parallel o he oupu capacior CO) changes by increasing his change has he effec of reducing he average oupu curren. As shown in Figure 6 curren moves from line A for he nominal load o line B for a larger load. Wha should be noed is ha he slopes of he wo ramps boh during ON and OFF do no change because hey ly depend VDC VOU and L and hey have no been changed. As a csequence increasing he load resuls in RO becoming greaer. Since VO equals csan (he crol loop explained earlier handles his) and RO increases he curren diminishes. FIGURE 6: VL INDUCOR CURREN A DIFFEREN LOADS ON OFF Increasing load (reducing IO av) A B C D CONINUOUS MODE Operaing in he Cinuous mode is so named since he curren in he inducor never sops flowing (goes o zero). As shown in Figure 6 if he load cinues o increase (reducing IO av) a some ime he inducor curren plo will ouch he x-axis (line C). his means he iniial and final curren (a he beginning and he end of he swiching period) in he inducor is zero. A his poin he inducor curren eners wha is csidered as Criical mode. If he load is furher increased he curren during he down-ramp will reach zero before he end of he period (line D) which is known as Discinuous mode. Noe: In Discinuous mode he ly way o furher decrease he inducor curren is o reduce he ON ime (ON). One key poin is ha he inducor curren a he end of he OFF period mus equal he inducor curren a he beginning of he ON period meaning he ne change in curren in e period mus be zero. his mus be rue a Seady sae when all ransiens have finished and he circui behavior is no lger changing. ON Using he value of IL(ON) derived from Equai 3 and Equai 5 creaes he relaiship shown in Equai 8. EQUAION 8: ΔI L V DC V Q V OU ( ) ( ON V OU + V ) D OFF Neglecing VD and VQ Equai 8 can be solved for VOU as shown in Equai 9. EQUAION 9: V OU V DC D where D / (duy cycle) or V OU D V DC he maximum duy cycle is achieved when he inpu volage is a is minimum as shown in Equai 10. EQUAION 10: D max V OU V DC min herefore D mus obviously be beween 0 and Microchip echnology Inc. DS01207B-page 5

6 DISCONINUOUS MODE In Discinuous mode he inducor curren goes o zero before he period ends. he inducor (oupu) average curren (IO av min) ha deermines he edge beween Cinuous and Discinuous mode can be easily deermined as shown Figure 7. FIGURE 7: INDUCOR CURREN A HE EDGE OF DISCONINUOUS MODE IL IL peak I2 IO limi I1 ON OFF Based Figure 7 he inducor curren limi is equal o Equai 11. EQUAION 11: 1 1 I O limi --I L peak --( I I 1 ) 1 --I 2 2 From his poin he behavior of he Buck Cverer changes radically. If he load cinues o increase he ly possibiliy he sysem has o reduce he curren is o reduce he duy cycle (Figure 6). However his means ha a linear relaiship as shown in Equai 9 no lger exiss beween inpu and oupu. he relaiship beween VDC VOU and D can be obained wih some addiial effor as shown in Equai 12. EQUAION 12: V OU D V DC I O I O limi V OU V DC Figure 8 illusraes his relaiship. 1 DS01207B-page Microchip echnology Inc.

7 FIGURE 8: DUY CYCLE IN CONINUOUS AND DISCONINUOUS REGIONS D 1 VDC/VOU 1.25 (A) VDC/VOU 2 Discinuous regi Cinuous regi VDC/VOU IO/IO limi As shown in Figure 8 saring from he cinuous regi and moving alg line (A) where D 0.5 as so he boundary beween cinuous and discinuous regis (doed line) is crossed o keep he same oupu volage (VDC/VOU 2) D changes according o he nlinear relai in Equai 12. Design Equais and Compen Seleci his seci deermines he equais ha enable he design of a Cinuous mode Buck Cverer. INDUCOR he average minimum curren (IO av min) is se as he average oupu curren a he boundary of Discinuous mode (Figure 7). his way for any curren larger han IO av min he sysem will operae in Cinuous mode. Usually i is a percenage of IO av nom where a comm value is 10% as shown in Equai 13. EQUAION 13: 1 ( V DC nom V OOU ) 0.1I o av nom --I L ON O I o av min I O limi Solving Equai 13 wih respec o LO resuls in Equai 14. EQUAION 14: L O 5 ( V DC nom V )V OU OU V DC nom F PWM I O av nom where FPWM is he PWM frequency (FPWM 1/) Power Losses In he Inducor Power losses in he inducor are represened by Equai 15. EQUAION 15: P LOSS inducor I O av nom ( ) 2 ESR where ESR is he equivalen inducor resisance 2009 Microchip echnology Inc. DS01207B-page 7

8 OUPU CAPACIOR he curren ripple generaes an oupu volage ripple having wo compens as shown in Figure 9. Power Losses in he Capacior Power losses dissipaed in he capacior are shown in Equai 19. FIGURE 9: MODEL OF HE OUPU CAPACIOR CO CO RESR (ESR) LESL (ESL) EQUAION 19: DIODE Referring o Figure 5(E) he curren flowing hrough he diode during OFF is he inducor curren. I is easy hen o compue he average diode curren using Equai 20. EQUAION 20: 2 P LOSS capacior ΔI L R ESR he firs compen of he ripple volage (VR) is caused by he effec series resisance (ESR) of he oupu capacior. his resisance is shown in Figure 9 as RESR. he secd compen VRCO comes from he volage drop caused by he curren flowing hrough he capacior which resuls in Equai 16. EQUAION 16: V R ESR he wo cribuis are no in phase; however csidering he wors case if hey are summed in phase his resuls in e swiching period as shown in Equai 17. EQUAION 17: R ESR ( I 2 I 1 ) R ESR ΔI L where (I 2 - I 1 ) is he ripple curren flowing in he inducor and o he oupu (a he edge of Discinuous mode which is: ΔI L 2 I O limi) and V R CO i C O C ()d ΔV R oal R ESR ΔI L D + ΔI L C O F PWM he maximum reverse volage he diode has o wihsand is during ON (see Figure 5(D)) as shown in Equai 21. EQUAION 21: Power Dissipai Compuai in he Diode Because volage he diode is n-zero (VR) bu he curren is zero dissipai during ON is equal o Equai 22. EQUAION 22: Dissipai during OFF is equal o Equai 23. EQUAION 23: P D OFF I D av I O av nom ( 1 D) V R max V DC max + V Q P D ON 0 V f I O av nom V f I O av nom ( 1 D) OFF By rearranging erms he required capacior value needed o guaranee he specified oupu volage ripple is shown in Equai 18. EQUAION 18: C O ΔI L D V R oal F PWM [ Δ R ESR ΔI L ] MOSFE he maximum volage he swich (see Figure 5(B)) during OFF is shown in Equai 24. EQUAION 24: V Q max V DC max + V D DS01207B-page Microchip echnology Inc.

9 he average curren (Figure 5(C)) during ON is shown in Equai 25. EQUAION 25: MOSFE Power Losses Compuai Saic Dissipai During ON he average curren flowing in Q1 is IO av nom D and he volage is V Vf he swich forward volage which resuls in Equai 26. his value is small since VF is relaively small. EQUAION 26: P Q1 saic ON I Q av I O av nom D V f I O av nom DV I f O av nom ON his same loss can be expressed using he RDS(ON) of he MOSFE aking care o deermine from he compen daa shee he value of RDS(ON) a he expeced junci emperaure (RDS(ON) grows wih emperaure). his erm can be wrien as shown in Equai 27. During OFF he volage Q1 is VDC + VD (Figure 5(B)) bu he curren is zero. As shown in Equai 28 here is no cribui o he dissipaed power. EQUAION 28: P Q1 saic OFF 0 Swiching Dissipai Figure 10 illusraes wha occurs during swiching. here are wo evens o csider: urn- (Q1 closes) and urn-off (Q1 opens). In boh cases volage and curren do no change abruply bu have a linear behavior. he represenai in Figure 10 is he wors-case possibiliy where a urn he volage VQ1 remains csan a VDC while he curren is ramping up from zero o is maximum value. Only a his momen does he volage sar falling o is minimum value of VF. In realiy he wo ramps will somehow overlap; however since his is he wors case his depiced siuai is csidered he curren swiching even. herefore a urn- he power is equal o Equai 29. EQUAION 27: P Q1 saic ON DI O av nom ( ) 2 R DS ( ON ) highemp FIGURE 10: MOSFE SWICHING LOSS COMPUAION WAVEFORMS VQ1 IQ1 VF VR CR ON CF OFF urn- urn-off EQUAION 29: P Q1 swiching urn CR 1 1 I -- V Q1 I Q1 d -- O av nom V DC d -- I V DC O av nom V DC I O av nom CR V DC I O av nom VF + d CR VF 0 VF 2009 Microchip echnology Inc. DS01207B-page 9

10 If CR is equal o Equai 30 he resul of Equai 29 can be simplified as shown in Equai 31. EQUAION 30: CR VF SW EQUAION 31: V DC I O av nom P Q1 swiching urn SW A urn-off he swiching loss can be calculaed using Equai 32. EQUAION 32: P Q1 swiching urn off VR V Q1 I Q1 d -- I V DC 1 I O av d -- O av nom V + V nom DC d DC I O av nom VR V DC I O av nom CF VR CF 0 CF 2 Again if VR is equal o Equai 33 his compuai resuls in Equai 34. EQUAION 33: VR CF SW EQUAION 34: V DC I O av nom P Q1 swiching urn off SW he oal dissipai in he MOSFE is shown in Equai 35. EQUAION 35: + + P Q1 oal P Q1 saic ON P Q1 swiching urn P Q1 swiching urn off DV f I O av nom + 2V DC I O av nom SW DS01207B-page Microchip echnology Inc.

11 Buck Cverer Design Example his seci shows how he equais previously discussed are o be used in he design process of a Buck Cverer. In addii he ypical design requiremens and how hey influence he design are also discussed. DESIGN REQUIREMENS. he design requiremens are: Inpu volage: VDC 12V ±30% Oupu volage: VOU 5V IO nominal IO av nom 2A IO limi 0.1 IO av nom 0.2A (I2 - I1) ΔIL 2 IO limi 0.4A Swiching frequency 200 khz Oupu ripple volage 50 mv Inpu ripple volage 200 mv DESIGROCESS Duy Cycle Compuai he cverer is supposed o operae in Cinuous mode so ha Equai 9 holds and: Dnominal VOU/VDC 5/ In addii he maximum and minimum available inpu volages will be compued: Minimum inpu volage 8.5V Maximum inpu volage 15.5V Inducor According o Equai 14 he nominal value of he inducor (Cinuous mode) is equal o Equai 36. EQUAION 36: 5( V DC V OU ) L o V OU I O av nom V DC F PWM ( 12 5) μH K he inducor required o place he sysem in Cinuous mode wih he maximum inpu volage is shown in Equai 37. EQUAION 37: V DC V OU V OU μH K L O M 0.2I O av nom V DC F PWM 2009 Microchip echnology Inc. DS01207B-page 11

12 he required inducor wih he minimum inpu volage is shown in Equai 38. EQUAION 38: An inducor of a leas 42 µh will preven he cverer from going discinuous over he full inpu volage range. In fac if he smalles inducor L 26 µh is seleced he maximum inpu volage (VDC 15.5V) would resul in a curren ripple of I2 - I1 0.85A. Cversely he inducor L 42 µh wih an inpu volage of 8.5V gives a curren ripple of 0.17A. his means ha any inducor greaer han 42 µh will fi. Oupu Capaciance Equai 39 is supposing o selec a capaciance having ESR 30 mω. EQUAION 39: V DC V OU V OU μH K L O m 0.2I O av nom V DC F PWM C ΔI L D F PWM [ V RIPPLE R ESR ΔI L ] 200K[ μF 0.4 ] Inpu Capacior Using he same approach o compue he oupu capaciance he inpu capaciance is hen calculaed using Equai 40. EQUAION 40: C ΔI L D F PWM [ V RIPPLE R ESR ΔI L ] 200K[ μF 0.4] Free-Wheeling Diode Seleci Based Equai 21 (see also Figure 5(D)) he maximum reverse volage he diode during ON is hen calculaed as shown in Equai 41. EQUAION 41: V R max V DC max + V Q 15.5V According o Equai 20 he average curren in he diode is calculaed as shown in Equai 42. EQUAION 42: I D av I O av nom ( 1 D) 2 ( ) 1.16A DS01207B-page Microchip echnology Inc.

13 MOSFE seleci he key parameers for he seleci of he MOSFE are he average curren and he maximum volage (referring o Equai 24 and Equai 25). he resuling calculais are shown in Equai 43 and Equai 44. EQUAION 43: V Q max V DC max + V D 15.5V EQUAION 44: I Q av I O av nom D A he power dissipaed in he MOSFE can be compued wih Equai 35 which resuls in Equai 45 where ypical values of VF 1V and sw 100 ns are used. EQUAION 45: P LOSS max SW DV f I O av nom 2V DC I O av nom ns V 2A V 2A W 5μs 2009 Microchip echnology Inc. DS01207B-page 13

14 BOOS CONVERER A Boos Cverer cvers a lower inpu volage o a higher oupu volage. opology Equais Figure 11 shows he essenial opology of a Boos Cverer. Q1 OPEN (OFF PERIOD) When he swich opens (Figure 13) and since he inducor curren canno change abruply he volage mus change polariy. Curren hen begins flowing hrough he diode which becomes forward-biased. FIGURE 13: BOOS CONVERER OPOLOGY: OFF PERIOD FIGURE 11: VL L1 VDC BOOS CONVERER OPOLOGY Q1 D1 VOU CO RO VOU VL VD L1 D1 VOU VDC Q1 CO RO he resuling inducor volage is shown in Equai 48. EQUAION 48: Q1 CLOSED (OERIOD) In his cfigurai he circui is redrawn as shown in Figure 12. FIGURE 12: VDC VL L1 BOOS CONVERER OPOLOGY: OERIOD he resuling volage he inducor is shown in Equai 46. EQUAION 46: Based he inducor equai (Equai 46) he curren resuls are shown in Equai 47. EQUAION 47: Q1 D1 V L V DC V Q VOU CO ( V DC V Q ) I L () I L ( 0) L 1 RO VOU he curren flowing ino he inducor during OFF which is ramping down is compued using Equai 49. EQUAION 49: V L V DC V D V OU < 0 V D V OU I L () I ( ON ) OPERAING MODES V DC Like he Buck Cverer he Boos Cverer can also be operaed in Cinuous and Discinuous modes. he difference beween he wo modes is in he inducor curren. In Cinuous mode i never goes o zero whereas in Discinuous mode he falling inducor curren in he OFF period reaches zero before he sar of he following PWM period. As in he case of he Buck Cverer he Boos Cverer can be used in boh modes. In eiher case he crol loop mus be csidered. A solui for e mode does no necessarily work well wih he oher. Cinuous Operaing Mode As usual he wo areas below he inducor volage during ON and OFF mus be equal. his means ha he curren a he beginning of he PWM period equals he curren a he end (Seady sae cdii) of he PWM period. Using Equai 47 and Equai 49 he relai shown in Equai 50 can be made. L 1 DS01207B-page Microchip echnology Inc.

15 EQUAION 50: V OU where D is he duy cycle of he PWM signal. V DC D I is imporan o noe ha his is a nlinear relaiship (Figure 14) unlike he Buck ransfer funci. If a lossless circui is assumed PO PDC VOIO VDCIDC resuling in Equai 51. EQUAION 52: he power delivered o he load by he inpu during OFF is shown in Equai 53. EQUAION 53: P L where Ip is he inducor peak curren L 1 I 2 P EQUAION 51: P DC I P F V DC I O ( 1 D) I DC Discinuous Operaing Mode o find he I/O relaiship a differen approach is used where energy is csidered which differs from he approach used for Buck Cverers. he oal power (P) delivered o he load comes from he cribui of he magneic field in he inducor and during OFF from he inpu volage VDC. he power delivered from he inducor (assuming 100% efficiency) is shown in Equai 52. where F as indicaed in Figure 15(G) is he pori of he OFF period from ON o when he inducor curren reaches zero. he oal power delivered o he load is he sum of Equai 52 and Equai 53. he peak curren is derived from Equai 47. If ON + F k he resuls are ha of Equai 54. EQUAION 54: kr V OU V O ON DC L 1 where RO is he oupu load resisor FIGURE 14: VO/VDC Series D% 2009 Microchip echnology Inc. DS01207B-page 15

16 FIGURE 15: BOOS CONVERER WAVEFORMS (DISCONINUOUS MODE) ON OFF Q1 Command VD + VOU (A) VQ1 (B) IQ1 (C) VD1 (A) (D) -VOU + VQ ID1 (E) VDC VL (F) (B) VDC - VOU IL (G) F (A) Command signal Q1 MOSFE gae (B) Volage Q1 MOSFE (C) Curren flowing ino Q1 MOSFE (D) Volage D1 diode (E) Curren in D1 diode (F) Volage LO inducor (G) Curren in LO inducor DS01207B-page Microchip echnology Inc.

17 Design Equais and Compen Seleci As previously discussed in Cinuous mode he inpu/oupu relaiship is equal o Equai 50. In Discinuous mode his relaiship is equal o Equai 54. he maximum ON ime will correspd o he minimum inpu volage VDC. he duy cycle can be chosen so ha in Equai 54 ON + F k < wih 0 < k < 1. Combining Equai 47 and Equai 49 and using he previous definii for ON + F gives an equai for ON max as shown in Equai 55. he resuling maximum duy cycle is shown in Equai 56. EQUAION 55: EQUAION 56: INDUCOR. ON max I is possible o compue he inducor L1 using Equai 54. he maximum ON minimum VDC and minimum RO are assumed which resuls in Equai 57. EQUAION 57: OUPU CAPACIOR k( V OU V DC min ) V OU kv ( OU V DC min ) D max L 1 kr O min V OU D max VDC min 2 2F PWM V OU he oupu capacior mus be able o supply he oupu curren during ON wihou having a volage drop greaer han he maximum allowed oupu ripple. Since he capacior is large i is possible o approximae he expenial discharge wih a linear behavior. he curren drawn from he capacior is he average oupu curren (IO av nom) and he charge los during ON is equal o Equai 58. herefore he volage drop is equal o Equai 59. EQUAION 59: A simplified represenai is shown in Equai 60. EQUAION 60: DIODE During ON he diode D1 is open wih he maximum reverse volage as shown in Equai 61. EQUAION 61: he average curren in D1 during OFF is shown in Equai 62. EQUAION 62: MOSFE I O av nom ON V DROP he average curren represened in Figure 13 is shown in Equai 63. EQUAION 63: he maximum volage represened in Figure 12 is shown in Equai 64. EQUAION 64: < V C RIPPLE I O av nom ON V RIPPLE C > V R max V OU + V Q F I D av I O av nom ON I Q1 av I O av nom V Q max V OU + V D EQUAION 58: Q ON I O av nom ON 2009 Microchip echnology Inc. DS01207B-page 17

18 FORWARD CONVERER he opology of a Forward Cverer shown in Figure 16 can be csidered a direc derivaive of he Push-Pull Cverer where e of he swiches is replaced by a diode. As a csequence he cos is usually lower which makes his opology very comm. FIGURE 16: FORWARD CONVERER OPOLOGY D1 VR NR VA A D2 B VB LO NP NS VS D3 VL CO RO VOU VDC VP Q1 opology Equais Referring o he seci Forward Cverers in AN1114 (see Inroduci ) he behavior of he sysem can be quickly summarized. he swich is driven by a waveform whose duy cycle mus be less han 50% as shown in Figure 17. FIGURE 17: Q1 MOSFE COMMAND SIGNAL IMING OFF Q1 Command ON R DS01207B-page Microchip echnology Inc.

19 Q1 ON (INERVAL 0 - ON) For his cfigurai he circui is redrawn as shown in Figure 18. FIGURE 18: FORWARD CONVERER OPOLOGY: INERVAL 0 - ON D1 V R NR VA A D2 B V B LO NP NS V S D3 VL CO RO VOU VDC VP Q1 Inpu Circui Behavior he inpu volage is direcly cneced o he winding NP and csequenly he do end of his winding is posiive respec o he n-do end. Similarly he do end of NR has a higher volage han he n-do end. Diode D1 is reverse-biased and no curren flows ino he winding NR. he volage he winding NP is shown in Equai 65. EQUAION 65: he volage winding NR is shown in Equai 66. EQUAION 66: V R V P N R V DC V Q V P ( V DC V Q ) N R he magneizing curren flowing ino he NP windings and he swich Q1 circui (curren ha would be flowing ino he ransformer if he secdary winding were open) is equal o Equai 67. he oal curren flowing ino NP is he sum of he magneizing curren and he oupu curren refleced o he primary hrough he ransformer. Oupu Circui Behavior Because of he volage polariy he primary windings he do end of he secdary winding is posiive compared o is n-do end. Csequenly D2 is forward-biased while D3 is reverse-biased. he secdary winding volage is shown in Equai 69. EQUAION 69: V S he volage o he righ of he recifying diode D2 is shown in Equai 70. EQUAION 70: ( V DC V Q ) V B V S V D ( V DC V ) V Q D EQUAION 67: I M () V P L M V DC V Q L M he volage he oupu inducor is shown in Equai 71. EQUAION 71: A posiive-slope ramp whose maximum value is reached a ON is shown in Equai 68. V L ( V DC V ) V Q D V OU EQUAION 68: I M ( ON ) V DC V Q L M ON he curren flowing hrough he oupu inducor and hrough D2 is shown in Equai Microchip echnology Inc. DS01207B-page 19

20 EQUAION 72: ( V N DC V Q ) V D V OU P I L () I L ( 0) A his poin he oal curren flowing ino he primary can be compued. I has wo cribuis: he magneizing curren (see Equai 67) and he load curren refleced back ino he primary as shown in Equai 73. EQUAION 73: I P oal L O ( V V DC V Q N DC V Q ) V D V OU I L ( 0) P L M L O Q1 OFF [INERVAL ON - (ON + R)] Based his cfigurai he circui is redrawn as shown in Figure 19. FIGURE 19: FORWARD CONVERER OPOLOGY: INERVAL ON - (ON + R) D1 VR NR VA A D2 B VB LO NP NS VS D3 VL CO RO VOU VDC VP Q1 DS01207B-page Microchip echnology Inc.

21 Inpu Circui Behavior Before he swich Q1 was opened he magneizing curren was flowing in NP. When he swich opens i reverses all he volages o cinue he flow. he do end of NR becomes negaive in respec o he n-do end and a similar behavior is experienced by he winding NP. Because of he polariy NR diode D1 becomes forward-biased and keeps he volage a he do end of NR e diode drop below ground. Magneizing curren can now flow hrough NR and diode D1 ino he power supply VDC as shown in Figure 19. he volage VR NR is shown in Equai 74. EQUAION 74: he volage NP is shown in Equai 75. EQUAION 75: When ON he curren in he rese winding equals he magneizing curren IM muliplied by he windings rai as shown in Equai 76. EQUAION 76: V R ( V DC + V D ) < 0 V P off N R ( V DC + V D ) < 0 Oupu Circui Behavior As previously menied he magneizing curren reverses all volages when he swich Q1 urns off. As a resul he do end of he secdary winding is more negaive han he n-do end and diode D2 becomes reverse-biased. he secdary volage is shown in Equai 77. EQUAION 77: o keep he curren flowing ino inducor LO is volage reverses so ha he lef end of he inducor is more negaive han he righ end and i would cinuously decrease; however he freewheeling diode D3 becoming forward-biased and ses VB o a diode volage drop below ground. he volage he inducor is now equal o Equai 78. EQUAION 78: Csequenly he inducor curren will decrease according o Equai 79: EQUAION 79: V S off N R V L ( V DC + V D ) V OU V D I R N R I M V OU + V D I L () I ( ON ) L O During R his curren has a down-slope and reaches zero when ON + R. his curren is he same curren ha is flowing ino he free-wheeling diode D Microchip echnology Inc. DS01207B-page 21

22 Q1 OFF [INERVAL (ON + R ) O ] In his cfigurai he circui is redrawn as shown in Figure 20. FIGURE 20: FORWARD CONVERER OPOLOGY: INERVAL (ON + R) - D1 VR NR VA A D2 B VB LO NP NS VS D3 VL CO RO VOU VDC VP Q1 Inpu Circui Behavior As so as he magneizing curren reaches zero (a ON + R) all of he energy ha had been sored ino he ransformer when ON has been released and diode D1 opens. Csequenly he volage drop NR becomes zero and he volages a boh he do end and he n-do end of NR equal VDC. he volage drop NP equally becomes zero so ha now he volage applied o he swich is VDC. Oupu Circui Behavior Nohing changes compared o he previous ime inerval. Design Equais and Compen Seleci INPU/OUPU RELAIONSHIP AND DUY CYCLE A he oupu a seady sae he curren in he inducor LO a 0 mus equal he curren a. Expressing he inducor volage as a funci of he inducor curren based Equai 72 and Equai 78 resuls in Equai 80 which in urn solves Equai 81. EQUAION 80: ( V N DC V Q ) V D V OU P ON L O V OU + V D L O OFF EQUAION 81: V OU he magneizing curren a ime 0 and ON + R is zero (a Seady sae). herefore ΔIM during ON mus equal ΔIM during R which is represened by Equai 82 (refer o Equai 65 and Equai 75). EQUAION 82: V DC L M he circui is now running a he maximum duy cycle when R equals OFF which means he full OFF period is needed o nullify he magneizing curren. In his case in Equai 82 R is replaced wih is maximum heoreical value OFF so ha ON max as shown in Equai 83 is derived from Equai 84. EQUAION 83: EQUAION 84: ( V DC V )D V Q D N R L M N P ON V DC R ON R ON max N R OFF ON max N R 1 D max heoreical N R N R ( ON max ) In he case of NR NP Dmax heoreical 0.5. DS01207B-page Microchip echnology Inc.

23 RANSFORMER: PRIMARY he core of he ransformer during operai moves in he firs quadran of he hyseresis curve. he change in flux according o he Faraday law as shown in Equai 85 is proporial o he produc of he applied volage VP and he ime x during which his volage is presen. EQUAION 85: In general ON + R k; he maximum value for ON is chosen as ON max k/2 when NP NR. As indicaed in Figure 21 he maximum value of ON is also dependen he rai NP/NR. Based he characerisics of he ransformer core ΔB is defined. From Equai 85 he primary number of urns can be deermined csidering he minimum value of VDC and csequenly he maximum duy cycle as shown in Equai 86. V P X EQUAION 86: ΔB A core D max where he unis are esla for ΔB and m 2 for A F ( core PWM A core ΔB V DC V min Q ) During ON his produc equals (VDCON) while during R he produc is NPVDC(R)/NR based Equai 65 and Equai 75 neglecing VQ and VD. In Figure 22(F) he produc (VDCON) equals area A1 while VDCNPR/NR equals area A2. I is preferable o have a ne ΔB 0 so ha in he hyseresis plane he operaing poin a he end of he PWM period has come back o he iniial poin. his guaranees ha he sysem will never drif oward saurai. he poin is ha he cdii can easily be fulfilled wih differen values of he raio NP/NR by selecing a differen number of urns he wo windings (see Figure 21). his provides an addiial degree of freedom in he design of he sysem. Replacing NP in Equai 81 and neglecing VD resuls in Equai 87. EQUAION 87: V OU F PWM A core ΔB NR can be deermined by csidering he behavior described in Figure Microchip echnology Inc. DS01207B-page 23

24 FIGURE 21: FORWARD CONVERER: VOLAGE ON HE MOSFE FOR DIFFEREN VALUES OF PRIMARY AND RESE WINDING URNS /2 /2 N 1 P VDC N R A2 NP NR VDC A1 R ON N 1 P VDC > 2V N R DC A2 NP > NR VDC A1 ON R N 1 P VDC < 2V N R DC VDC A2 NP < NR A1 R ON DS01207B-page Microchip echnology Inc.

25 FIGURE 22: FORWARD CONVERER WAVEFORMS (NP NR): PRIMARY SIDE ON R Q1 Command VDC VQ ON ON + R (A) VP (B) IM (C) VR (D) IR ID1 (E) VDC N R VDC VQ1 A1 A2 (F) IP IQ mr (G) (A) Command signal Q1 MOSFE gae (B) Volage VP primary winding NP (C) Magneizing curren IM (D) Volage VR rese winding NR (E) Rese winding curren equal o diode D1 curren (F) Volage Q1 MOSFE (G) Primary winding curren equal o Q1 MOSFE curren 2009 Microchip echnology Inc. DS01207B-page 25

26 RANSFORMER: PRIMARY WIRE SIZE As shown in Figure 22(G) he oal curren flowing ino he primary has wo cribuis: he magneizing curren (Equai 67) and he load curren (Equai 72) refleced back ino he primary resuling in Equai 88. EQUAION 88: ( V V DC V Q N DC V Q ) V D V OU P I P oal L M L O he primary wire size can hen be compued by firs referring o Figure 22(G) and hen replacing he real curren waveform wih a pulse having a square shaped waveform wih he same widh and whose ampliude is he value in he middle of he ramp (IQ mr). he curren is expressed as a funci of known (design requiremens) daa. Noe ha in hese compuais magneizing curren is negleced since he ransformer is designed o make i abou e-enh of he load refleced curren. herefore he inpu power PI equals Equai 89. EQUAION 89: P I he oupu power is shown in Equai 90. EQUAION 90: Solving Equai 90 resuls in Equai 91. EQUAION 91: his is he equivalen curren flowing in he primary wires when ON is a is maximum allowed value. he rms value is compued in Equai 92. EQUAION 92: V DC min I Q mr D max P O ηp I ηv DC min where η is he cverer efficiency I Q rms I Q mr I Q mr D max 1 P I Q mr -- O V DC min D max η P O 1 D max η V DC min D max D max RANSFORMER: SECONDARY WIRE SIZE As shown in Figure 24(C) he secdary curren equals he inducor curren (IO av) during ON. Again as for he primary curren he acual curren waveform is replaced wih a curren pulse having a square shaped wave form whose ampliude equals he mid-ramp inducor curren in he up-slope IO av nom. herefore he secdary average curren is equal o Equai 93. EQUAION 93: he rms value is compued as Equai 94. EQUAION 94: RANSFORMER: RESE WINDING WIRE SIZE he rese winding is no involved in carrying any curren refleced back ino he primary from he secdary. he ly curren i has o carry is he magneizing curren which is ploed in Figure 22(C). he magneizing peak curren compued in Equai 67 is shown in Equai 95. EQUAION 95: I Sav I O av nom I Srms I O av nom D max ON V DCmin ( ) V Q I M pk L M he rms value is he peak value muliplied by he square roo of he duy cycle and divided by radix 3 as shown in Equai 96. he correc AWG (wire size) can be deermined accordingly. DS01207B-page Microchip echnology Inc.

27 EQUAION 96: ( ) ON 3 V DC min V Q I M rms L M D max MOSFE During OFF he volage he Q swich is equal o Equai 97. EQUAION 97: V Q off 1 N R VDC A ON a spike due o leakage curren appears. I can safely be esimaed o be 30% of he peak value as shown in Equai 98. EQUAION 98: V Q off max N R V DC max he average curren flowing hrough he swich has been compued in Equai 92. DIODES able 1 summarizes he values of average curren and volage he diodes have o cope wih. ABLE 1: Diode D1 DIODE CURREN AND VOLAGE Cfigurai 0 - ON ON - (ON + R) (ON + R) - V D max 1 N R V DC max V F V D max V DC max D2 V F V D max N R V DC max V D max 0 D3 Legend: V D max VF is he diode forward volage. V DC max V F V F 2009 Microchip echnology Inc. DS01207B-page 27

28 OUPU FILER INDUCOR As in all oher opologies wih an LC low-pass filer a he oupu he inducor is seleced o no operae he sysem in Discinuous mode. he inducor is calculaed jus a he edge beween Cinuous and Discinuous mode (i.e. Criical mode) where he inducor curren sars from zero a he beginning of he PWM period and reurns o zero before he PWM period ends. In his cdii he average curren equals 0.5 he peak curren (or curren ripple) as shown in Figure 23. FIGURE 23: INDUCOR CURREN: PEAK CURREN RIPPLE CURREN AMPLIUDE AND OUPU CURREN A HE EDGE OF DISCONINUOUS MODE I Inducor IO PN IO av min IRIPPLE ON ON + R In Criical mode he minimum accepable oupu curren (defined by design requiremens) is made coinciden wih he average curren as shown in Equai 99. EQUAION 99: Using Equai 72 o compue IO ripple resuls in Equai 100. EQUAION 100: L O OUPU CAPACIOR I O ripple I O av min V DC min V OU D 2F PWM I max O av min he oupu volage ripple is mainly due o he capacior ESR. he inducor curren ripple flowing hrough i deermines a volage drop. herefore a capacior wih an ESR equal o Equai 101 mus be seleced. EQUAION 101: he capacior value iself can hen be compued wih Equai 102 which describes he value of he volage ripple aking ino accoun all compens. EQUAION 102: Neglecing ESL since i is normally very small (a leas for PWM frequencies less han 400 khz) resuls in Equai 103. EQUAION 103: V OU ripple I O ripple ESR < where I O ripple is compued as in Equai 98 V ripple C O D max ESL F I ripple ESR PWM F PWM C I O ripple D max D max F PWM ( V OU ripple I O ripple ESR) DS01207B-page Microchip echnology Inc.

29 FIGURE 24: FORWARD CONVERER WAVEFORMS: SECONDARY SIDE ON R Q1 Command (A) OFF VS (B) IO av IS ID2 (C) VB VD3 (D) VD2 (E) VL (F) IL (G) ID3 (H) (A) Command signal Q1 MOSFE gae (B) Volage VS secdary winding NS (C) Secdary winding curren equal o diode D2 curren (D) Volage a node B (E) Volage diode D2 (F) Volage LO inducor (G) Curren in LO inducor (H) Curren in diode D Microchip echnology Inc. DS01207B-page 29

30 WO-SWICH FORWARD CONVERER Clearly derived from he single-ended opology (Forward Cverer) his circui has significan advanages over single-ended forward cverers. A schemaic of his opology is shown in Figure 25. FIGURE 25: WO-SWICH FORWARD CONVERER OPOLOGY Q1 D3 VB VL VDC D2 D1 NP NS VS D4 LO CO VOU Q2 opology Equais Referring o he seci wo-swich Forward Cverers in AN1114 (see Inroduci ) he basic equais are reviewed firs followed by he seleci of circui compens. Boh swiches Q1 and Q2 are simulaneously driven by a square wave signal wih a duy cycle less han 0.5 as shown in Figure 26. FIGURE 26: SIGNAL DRIVING SWICHES Q1 AND Q2 R Q1 Command Q2 Command ON DS01207B-page Microchip echnology Inc.

31 Q1 ON Q2 ON (INERVAL 0 - ON) In his cfigurai he circui is redrawn as shown in Figure 27. FIGURE 27: WO-SWICH FORWARD CONVERER OPOLOGY: INERVAL 0 - ON IPRIMARY Q1 D3 VB VL VDC D2 D1 NP NS VS D4 LO CO VOU Q2 Inpu Circui Behavior he ransformer is cneced beween VDC and ground; he do end is more posiive han he n-do end and he magneizing curren is flowing hrough i. Boh diodes a he primary are reverse-biased and do no cribue o he operai. he volage he primary is equal o Equai 104. EQUAION 104: he secdary volage is equal o Equai 106. EQUAION 106: V S ( V DC 2V Q ) Equai 107 shows he volage he inducor. EQUAION 107: V P V DC 2V Q V L ( V DC 2V Q ) V D V OU he magneizing curren in he ransformer has a posiive slope increase as shown in Figure 30(C): EQUAION 105: I M () ( ) V DC 2V Q L M he oal curren in he primary is his magneizing curren plus he secdary curren refleced by he ransformer back o he primary. Oupu Circui Behavior Similar o he primary he secdary winding experiences a volage ha is higher a he do end compared o he n-do end. herefore diode D3 is forwardbiased and cducing he curren o he inducor while diode D4 is reversed-biased. As shown in Equai 108 he curren in he inducor has a linearly growing behavior (see also Figure 31(E)). EQUAION 108: ( V N DC 2V Q ) V D V OU P I L () I L ( 0) A his poin he oal curren in he primary windings can be compued as he sum of he magneizing curren and he secdary curren refleced back ino he primary (see Figure 30(F)) as shown in Equai 109. L O EQUAION 109: I P oal () I L ( 0) ( V ( ) N S N DC 2V Q ) V D V OU P V DC 2V Q L M L O 2009 Microchip echnology Inc. DS01207B-page 31

32 Q1 OFF Q2 OFF (INERVAL ON O (ON + R)) When boh swiches urn off he magneizing curren in NP reverses all he volages in he sysem. A he primary he n-do end par of he inducor becomes more posiive han he do end (see Figure 28). Boh diodes are forward-biased which provides a pah for he leakage curren from he n-do end of he primary hrough D2 ino he posiive of VDC ou of is negaive wire hrough diode D1 and back again o he ransformer. FIGURE 28: WO-SWICH FORWARD CONVERER OPOLOGY: INERVAL ON - (ON + R) Q1 D3 V B VL VDC D2 D1 VP NP NS VS D4 LO CO VOU Q2 he volage he primary is equal o Equai 110. EQUAION 110: V P off he magneizing curren can be expressed as Equai 111. EQUAION 111: ( V DC + 2V D ) I M () ( ) V DC + 2V D L M he magneizing curren reaches zero (ha is all he energy sored ino he ransformer primary during ON has been delivered back o he VDC inpu) a ime ON +R being (ON + R) <. Oupu Circui Behavior Because of he change in polariy of he volages due o he magneizing curren he polariy of he induced secdary volage is such ha he n-do end of he winding is more posiive han he do end. In he meanwhile he volage he oupu inducor changes polariy as well and is lef side ries o go very negaive bu is clamped o a diode volage drop below ground by diode D4 which is forward-biased. D3 he crary becomes reverse-biased. he inducor curren has is pah hrough diode D4 and ino he load and he oupu capacior. Equai 112 shows he secdary volage. EQUAION 112: V S Equai 113 shows he inducor volage. EQUAION 113: Equai 114 shows he curren. EQUAION 114: N S ( V DC + 2V D ) V L I L () V OU V D ( ) V OU + V D L O DS01207B-page Microchip echnology Inc.

33 Q1 OFF Q2 OFF (INERVAL (ON + R) O ) As seen previously from (ON + R) o here is no more energy in he ransformer primary he magneizing curren is zero and csequenly he wo diodes D1 and D2 are no cducing any more as hey are reverse-biased. In his cfigurai he circui is redrawn as shown in Figure 29. Volage VP and VS are boh zero and volage he swich will be less han VDC. Nohing changes a he secdary. FIGURE 29: WO-SWICH FORWARD CONVERER OPOLOGY: INERVAL (ON + R) - Q1 D3 V B VL VDC D2 D1 VP NP NS VS D4 LO CO VOU Q2 Design Equais and Compen Seleci INPU/OUPU RELAIONSHIP AND DUY CYCLE he inpu/oupu relaiship is shown in Equai 115 and is obained by equaing Equai 108 wih Equai 114 where ON and OFF respecively. EQUAION 115: V OU ( V DC 2V )D V Q D EQUAION 117: D max heoreical 0.5 Of course he real duy cycle will be somewha smaller han he maximum heoreical value o ake ino accoun olerances in he compuais. RANSFORMER: PRIMARY he number of primary urns is deermined from he Faraday equai shown in Equai 118 which resuls in Equai 119. Neglecing VD and VQ he duy cycle can be deermined as shown in Equai 116. EQUAION 116: EQUAION 118: ΔB V P ON A core V OU V DC D EQUAION 119: he maximum heoreical duy cycle (Equai 117) can be obained equaing he wo magneizing currens (Equai 105 and Equai 111) csidering ha R can be a maximum R OFF. ( V DC min 2V Q )D max F PWM A core ΔB 2009 Microchip echnology Inc. DS01207B-page 33

34 RANSFORMER: PRIMARY WIRE SIZE he curren flowing hrough he ransformer can be compued replacing he curren in Figure 30(F) wih an equivalen waveform having a csan ampliude (IP mr) correspding o he mid-ramp value. Csidering he relaiship of Equai 120 (beween he inpu power) and Equai 121 (he oupu power) his resuls in Equai 122. herefore he rms value is hen equal o Equai 123. EQUAION 120: RANSFORMER: SECONDARY WIRE SIZE By referring o Figure 31(C) he curren flowing ino he secdary winding can be deermined and he ramp a sep curren waveform can be approximaed wih a csan ampliude signal being he ampliude IO av nom. Based hese he correspding rms value is equal o Equai 125. EQUAION 125: I SECONDARY rms I O ar nom D max P O ηp I MOSFE EQUAION 121: he maximum volage he swiches mus be able o wihsand during OFF is shown in Equai 126. P I V DC min I P mr D max EQUAION 126: EQUAION 122: EQUAION 123: P O I P mr ηv DC min D max I P rms I P mr D max he maximum curren during ON is shown in Equai 127 which is he same curren flowing ino he ransformer. EQUAION 127: V Q max V DC max P O I P mr ηv DC min D max RANSFORMER: SECONDARY he number of urns are deermined by Equai 115 and Equai 119 and resuls in Equai 124. EQUAION 124: V OU F PWM A core ΔB DS01207B-page Microchip echnology Inc.

35 FIGURE 30: WO-SWICH FORWARD CONVERER WAVEFORMS: PRIMARY SIDE R Q1 Command Q2 Command ON (A) VP (B) IM (C) VDC VQ1 VQ2 (D) VD1 VD2 (E) IP mr IP (F) (A) Command signal Q1 and Q2 MOSFE gaes (B) Volage VP primary winding NP (C) Magneizing curren IM (D) Volage Q1 and Q2 MOSFES (E) Volage diodes D1 and D2 (F) oal primary curren IP (magneizing curren and load curren refleced back o he primary side of he ransformer) 2009 Microchip echnology Inc. DS01207B-page 35

36 FIGURE 31: WO-SWICH FORWARD CONVERER WAVEFORMS: SECONDARY SIDE R Q1 Command Q2 Command ON ON + R (A) VS (B) IS (C) VL (D) IO av nom IL (E) IO av nom ID3 (F) VD4 (G) ID4 (H) (A) Command signal Q1 and Q2 MOSFE gaes (B) Volage VS secdary winding NS (C) Curren flowing ino he secdary winding NS (D) Volage inducor LO (E) Curren in inducor LO (F) Curren flowing in diode D3 (G) Volage diode D4 (H) Curren in diode D4 DS01207B-page Microchip echnology Inc.

37 DIODES able 2 provides calculais for deermining diode volage. ABLE 2: Diode D1 V R DIODE VOLAGE Cfigurai 0 - ON ON -> (ON + R) (ON + R) -> V DC max + V Q V F V V DC max R D2 D3 V R V DC max + V Q V F V V DC max R V F VR ( V DC max + 2V D ) + V V D F 2 D4 V R ( V DC max 2V Q ) + V D V F V F Legend: VF is he diode forward volage. able 3 provides calculais for deermining average diode curren. ABLE 3: Diode D1 D2 D3 D4 DIODE CURREN Cfigurai 0 - ON ON -> (ON + R) (ON + R) -> 0 0 P O ηv DC min D max P O ηv DC min D max I O av nom I O av nom I O av nom 2009 Microchip echnology Inc. DS01207B-page 37

38 OUPU INDUCANCE he oupu inducor is compued so ha he oupu inducor is a he edge of he Discinuous mode when he oupu curren is he minimum required (IO av min). Using he same approach used for he Forward Cverer (see Figure 26 and Equais 99 and 100) from Equai 108 and Equai 128 (neglecing he volage drops he MOSFES and diodes) resuls in Equai 129. EQUAION 128: I O ripple I O av min EQUAION 129: L O OUPU CAPACIANCE V DC min V O Dmax F PWM I O av min he capaciance should presen he lowes possible impedance a he frequency of he curren ripple o achieve he lowes oupu volage ripple. he volage ripple is deermined by he ESR of he oupu capacior and by he volage drop CO due o he curren flowing hrough i (see Equai 130). EQUAION 130: ESR I O ripple I O ripple V OU ripple 1 C O D F PWM he oupu capacior value can be deermined from Equai 131. DS01207B-page Microchip echnology Inc.

39 HALF-BRIDGE CONVERER Design Equais Figure 32 presens he schemaic of a Half-Bridge Cverer. Please refer o he seci Half-Bridge Cverers in AN1114 (see Inroduci ) for a deailed descripi of he operai of he sysem. he waveforms (wo pulses wih adjusable widh and a 180 phase delay) used o drive he gaes of he wo Q ransisors are represened in Figure 33. Some margin is needed afer he falling edge of e pulse before he rising edge of he oher. hese ime inervals are called R. If no implemened a shor circui exiss and he swiches will be desroyed by he very high curren flowing hrough he pah from VDC o ground. Iniially CB is replaced wih a shor circui. FIGURE 32: HALF-BRIDGE CONVERER OPOLOGY VDC/2 C1 Q1 D1 NP NS D3 VB VL LO VDC VDC/2 C2 CB Q2 NS D4 CO RO VOU D2 FIGURE 33: Q1 AND Q2 COMMAND SIGNALS R R Signal Driving Q1 1ON Signal Driving Q2 2ON 2009 Microchip echnology Inc. DS01207B-page 39

40 Q1 ON Q2 OFF In his cfigurai he circui is redrawn as shown in Figure 34. FIGURE 34: HALF-BRIDGE CONVERER OPOLOGY: Q1 ON Q2 OFF VDC/2 C1 Q1 D1 NP NS D3 VB VL LO VDC VP VS D4 CO RO VOU VDC/2 C2 Q2 D2 Inpu Circui Behavior he volage capacior C1 develops a volage he primary circui where he do end is more posiive han he n-do end. Equai 132 shows he volage a he primary. EQUAION 132: V P Equai 133 shows he magneizing curren. EQUAION 133: V DC V 2 Q1 I M () V DC V 2 Q L M Oupu Circui Behavior Because of he volage polariy he primary he doend edge of he secdary is more posiive han he n-do end. Diode D4 is hen reverse-biased and D3 is forward-biased. Equai 134 shows he volage a he secdary. EQUAION 134: V S Equai 135 shows he volage he inducor. EQUAION 135: V L V DC V 2 Q V DC V 2 Q1 V D3 V OU > 0 Equai 137 shows he curren. EQUAION 136: V DC V 2 Q1 V D3 V OU I L () I L ( 0) L O DS01207B-page Microchip echnology Inc.

41 Q1 OFF Q2 ON In his cfigurai he circui is redrawn as shown in Figure 35. FIGURE 35: HALF-BRIDGE CONVERER OPOLOGY: Q1 OFF Q2 ON VDC/2 C1 Q1 D1 NP NS D3 VB VL LO VDC VS D4 CO RO VOU VDC/2 C2 Q2 D2 Inpu Circui Behavior In his insance he do end of he primary winding has a volage ha is more negaive han he n-do end. Equai 137 shows he primary winding volage. EQUAION 137: Oupu Circui Behavior As wih he primary he do end of he secdary winding has a volage more negaive han he ndo end. As a csequence D3 in open and D4 is forward-biased. Equai 139 shows he secdary volage. V P V DC V 2 Q Equai 138 shows he magneizing curren. EQUAION 139: V S V 2 Q V DC EQUAION 138: I M () V DC V 2 Q L M Equai 140 shows he inducor volage. EQUAION 140: V L V DC V 2 Q V D V OU Equai 141 shows he curren. EQUAION 141: V DC V 2 Q VD V OU I L () I L ( ON ) L O 2009 Microchip echnology Inc. DS01207B-page 41

42 Q1 OFF Q2 OFF (PERIOD R) In his cfigurai he circui is redrawn as shown in Figure 36. FIGURE 36: HALF-BRIDGE CONVERER OPOLOGY: Q1 OFF Q2 OFF VDC/2 C1 Q1 D1 NP NS D3 VB VL LO VDC VS D4 CO RO VOU VDC/2 C2 Q2 D2 Inpu Circui Behavior In his insance he curren pah in he primary side when Q1 urns off (Figure 37) and when Q2 urns off (Figure 38). FIGURE 37: HALF-BRIDGE CONVERER: CURREN PAH IN HE PRIMARY SIDE WHEN Q1 URNS OFF Oupu Circui Behavior When boh swiches are off he volage he wo secdary windings are such ha boh D1 and D2 are forward-biased and are cducing. he curren is spli equally beween hem so ha each of hem is cducing e half of he curren flowing ino he inducor. he resuling curren waveforms are shown in Figure 40. Equai 142 shows he inducor volage. EQUAION 142: VDC/2 C1 Q1 D5 NP V L V OU VDC VDC/2 C2 Q2 D6 < 0 Equai 143 shows he curren flowing hrough i. EQUAION 143: I L () V OU L O FIGURE 38: HALF-BRIDGE CONVERER: CURREN PAH IN HE PRIMARY SIDE WHEN Q2 URNS OFF D5 VDC/2 C1 Q1 VDC > 0 VDC/2 C2 Q2 D6 DS01207B-page Microchip echnology Inc.

43 FIGURE 39: HALF-BRIDGE CONVERER WAVEFORMS: PRIMARY SIDE Q1 Command (A) Q2 Command (B) VDC/2 VP (C) -VDC/2 VDC VDC/2 VQ1 (D) IP mr IQ1 (E) VDC VDC/2 VQ2 (F) IP mr IQ2 (G) ON R ON R (A) Command signal Q1 MOSFE gae (B) Command signal Q2 MOSFE gae (C) Volage VP primary winding NP (D) Volage Q1 MOSFE (F) Curren flowing in Q1 MOSFE (G) Volage Q2 MOSFE (H) Curren flowing in Q2 MOSFE 2009 Microchip echnology Inc. DS01207B-page 43

44 FIGURE 40: HALF-BRIDGE CONVERER WAVEFORMS: SECONDARY SIDE Q1 Command (A) Q2 Command (B) NP/NS VDC/2 VS -NS/NP VDC/2 NS/NP VDC VD3 (C) (D) ID3 (E) VD4 (F) ID4 (G) VL (H) IO av nom IL (I) (A) Command signal Q1 MOSFE gae (B) Command signal Q2 MOSFE gae (C) Volage V S secdary winding NS (D) Volage diode D3 (E) Curren flowing in diode D3 (F) Volage diode D4 (G) Curren flowing in diode D4 (H) Volage inducor LO (I) Curren in inducor LO DS01207B-page Microchip echnology Inc.

45 Design Equais and Compen Seleci INPU/OUPU RELAIONSHIP AND DUY CYCLE A he Seady sae he increase in inducor curren during ON mus equal is decrease during R (neglecing he forward drop he diode) as shown in Equai 144. EQUAION 144: Equai 147 shows he inpu power. EQUAION 147: Equai 148 shows he oupu power. EQUAION 148: P I V DC I 2 P mr 2D P O ηp I V OU V DC D where η is he efficiency where D ON and ( ON + R ) -- 2 Operaing hese wo equais resuls in Equai 149. Csequenly knowing ha here are wo pulses in he PWM period he maximum heoreical duy cycle is Dmax heoreical 0.5. Of course o avoid he shoohrough in he wo swiches he maximum duy cycle correspding o he minimum inpu volage will be less. RANSFORMER: PRIMARY As so as he ransformer core has been defined he primary urns number can be compued from Faraday s law as shown in Equai 145 resuling in Equai 146. EQUAION 149: P O I P mr ηv DC min D max Equai 150 shows he rms value. EQUAION 150: I P rms I P mr D max EQUAION 145: RANSFORMER: SECONDARY NUMBER OF URNS WIRE SIZE ΔB V P ON A core he secdary urns number shown in Equai 151 can be obained from Equai 144 and Equai 146. EQUAION 146: EQUAION 151: V DC min D max F PWM A core ΔB V OU F PWM A core ΔB RANSFORMER: PRIMARY WIRE SIZE Curren flowing in he primary windings is ploed in Figure 39(E and G). I is he sum of he magneizing curren flowing ino he primary windings and he secdary load curren refleced back by he ransformer urn raio. o make compuais simpler he real curren waveforms can be replaced wih he mid-ramp value (IP mr) and deermine is value csidering he inpu (PI) and oupu (PO) power. he average oupu curren shown as IO av nom in Figure 40(I) is he average oupu curren he cverer is designed for. he rms secdary curren (IS) resuls in Equai 152. EQUAION 152: I Srms I O av nom D max 2009 Microchip echnology Inc. DS01207B-page 45

46 SWICHES Referring o seci Half-Bridge Cverers in AN1114 (see Inroduci ) e of he main advanages of he Half-Bridge Cverer opology is ha he swiches mus wihsand a maximum volage ha is VDC compared o 2 VDC as in push-pull opologies. During ON and R he Q1 and Q2 swiches are subjec o a maximum volage of VQ max VDC max. he maximum curren flowing hrough he swiches has already been compued in Equai 150. OUPU INDUCANCE he inducor is seleced in such a way as o preven he oupu inducor curren from becoming discinuous. he compuais are performed a he edge beween cinuous and discinuous operai when he oupu sars from zero a he beginning of he ON period and goes back o zero a he end of he R period. In oher words he inducor curren peak (which is also he curren ripple DI) is wice he oupu average curren (see Equai 153). EQUAION 153: I O ripple 2I O a( v min) Equai 154 shows he resuls. EQUAION 154: N VDC min V P 2 OU ON L O OUPU CAPACIOR he oupu volage ripple is mainly due o he ESR which resuls in Equai 155. EQUAION 155: ESR I O ripple I O ripple V OU ripple As previously seen in oher opologies he oupu capacior value can be deermined from he relai shown in Equai 156. EQUAION 156: C O CAPACIOR CB Capacior CB (see Figure 32) is used o block he DC compen of he curren flowing ino he ransformer o avoid core saurai. Small differences beween C1 and C2 creae an unbalance of he volage a he poin beween hem and causes he core o walk alg he hyseresis loop o saurai. he presence of he small capacior causes a droop in he primary volage. he volage during ON will decay almos linearly wih ime. Assuming ΔVD is he maximum accepable droop volage which resuls in Equai 157. EQUAION 157: 1 C O I O ripple D max D F PWM F PWM ( V OU ripple I O ripple ESR) L O N VDC min V P 2 OU D 2F PWM I max O av min C B I P mr > ON Δ V D DS01207B-page Microchip echnology Inc.

47 PUSH-PULL CONVERER he Push-Pull Cverer uses a ransformer o isolae he inpu from he oupu circui. opology Equais Figure 41 shows he schemaic of a Push-Pull Cverer. Refer o AN1114 (see Inroduci ) for a deailed descripi of he sysem operai. he waveforms (wo pulses wih adjusable widh and wih a 180 phase delay) used o drive he gaes of he wo Q ransisors are shown in Figure 42. is he period of he waveform wih wo pulses in e Q1 and he secd e Q2. his means ha he duy cycle mus be less han 0.5 o preven overlap of he wo pulses. Some margin is needed afer he falling edge of e pulse before he rising edge of he oher. hese ime inervals are called R. FIGURE 41: PUSH-PULL CONVERER OPOLOGY D2 VA VL VDC VDC NP VP1 NP VP2 NS VS1 VS2 D1 LO CO RO VOU Q1 Q2 FIGURE 42: SIGNALS DRIVING Q1 AND Q2 MOSFE GAES R R Signal Driving Q1 1ON Signal Driving Q2 2ON 2009 Microchip echnology Inc. DS01207B-page 47

48 Q1 ON Q2 OFF In his cfigurai he circui is redrawn as shown in Figure 43. FIGURE 43: PUSH-PULL CONVERER: Q1 ON Q2 OFF VL D2 VA VDC VDC NP VP1 NP VP2 NS VS1 NS VS2 D1 LO CO RO VOU Q1 Q2 Inpu Circui Behavior he inpu volage VDC gives place o a volage he primary winding where he n-do ends are more posiive han he do-ends. Equai 158 shows he volage a he primary. EQUAION 158: his same volage is presen he lower primary winding (supposing NP1 NP2) so ha he oal volage Q2 swich is equal o Equai 159. EQUAION 159: V P ( V DC V Q1 ) Oupu Circui Behavior Because of he volage polariy he primary he do ends of he secdary is more negaive ha he ndo end. Diode D2 is hen reverse-biased and D1 is forward-biased. Equai 161 shows he volage a he secdary. EQUAION 161: V S Equai 162 shows he volage he inducor. EQUAION 162: N S ( V DC V Q1 ) V Q2 off 2V DC V Q1 V L ( V DC V ) V Q1 D1 V OU > 0 Equai 160 shows he magneizing curren. EQUAION 160: I M () V DC + V Q L M Equai 163 shows he curren. EQUAION 163: N ( V DC V ) Q1 V D1 V OU P I L () I L ( 0) L O DS01207B-page Microchip echnology Inc.

49 Q1 OFF Q2 ON In his cfigurai he circui is redrawn as shown in Figure 44. FIGURE 44: PUSH-PULL CONVERER: Q1 OFF Q2 ON VL D2 VB VDC VDC NP VP1 NP VP2 NS VS1 NS VS2 D1 LO CO RO VOU Q1 Q2 Inpu Circui Behavior In his insance he do end of he primary windings has a volage more posiive han he n-do end. Equai 164 shows he primary winding volage. EQUAION 164: V P V DC V Q2 Oupu Circui Behavior As wih he primary he do end of he secdary windings has a volage more posiive han he ndo end. As a csequence D1 is open and D2 is forward-biased. Equai 166 shows he secdary volage. EQUAION 166: Equai 165 shows he magneizing curren. V S ( V DC V Q2 ) EQUAION 165: I M () V DC V Q L M Equai 167 shows he inducor volage. EQUAION 167: V L ( V DC V ) V Q2 D2 V OU > 0 Equai 168 shows he curren. EQUAION 168: N ( V DC V ) Q2 V D2 V OU P I L () I L ( 0) L O 2009 Microchip echnology Inc. DS01207B-page 49

50 Q1 OFF Q2 OFF (PERIOD R) In his cfigurai he circui is redrawn as shown in Figure 45. FIGURE 45: PUSH-PULL CONVERER: Q1 OFF Q2 OFF VL D2 VA VDC VDC NP VP1 NP VP2 NS VS1 NS VS2 D1 LO CO RO VOU Q1 Q2 Inpu Circui Behavior Equai 169 shows he volage each swich. EQUAION 169: Oupu Circui Behavior When boh swiches are off since he curren in he inducor cinues o flow in he same direci as before he volage he wo secdary windings are such ha: Vs2 -Vs1 and D1 and D2 are forwardbiased and are cducing. hey spli he curren equally so ha each of hem is cducing e half of he curren flowing ino he inducor. he resuling curren waveforms are ploed in Figure 47(G and H) for he wo secdary windings currens. Equai 170 shows he inducor volage. EQUAION 170: V L Based Equai 170 he curren flowing hrough he inducor LO is equal o Equai 171. EQUAION 171: V Q V DC V OU V D + V S1 where V S1 is IL imes he resisance of he windings (almos zero). V OU V D I L () I L () L O Design Equais and Compen Seleci INPU/OUPU RELAIONSHIP AND DUY CYCLE A he Seady sae he increase in inducor curren during ON mus equal is decrease during R. Using Equai 168 and Equai 171 (neglecing he forward drop he diode) and since (ON + R) /2 resuls in Equai 172. EQUAION 172: where D V OU ON Csequenly knowing here are wo pulses in he PWM period he maximum heoreical duy cycle can be Dmax 0.5. Saring from he inpu/oupu relaiship shown in Equai 173 he feedback crol loop keeps he oupu volage VOU csan agains changes in he inpu volage VDC and if VDC decreases ON will increase o compensae. EQUAION 173: V OU ( V DC V Q1 )D ( V DC V Q1 ) ON herefore for he sysem design a maximum duy cycle (Dmax) can be defined ha correspds o he minimum inpu volage (VDC min) and if less han he maximum heoreical is equal o Equai 174. EQUAION 174: D max V OU V DC min DS01207B-page Microchip echnology Inc.

51 RANSFORMER: PRIMARY NUMBER OF URNS As clearly saed in he Push-Pull Cverer seci in AN1114 (see Inroduci ) he operaing poin of he core ransformer moves beween poins ha are in he firs and hird quadran of he hyseresis loop. Once he maximum allowable ΔB has been defined (based PWM frequency and geomerical dimensis of he core and bobbins) using he Faraday equai shown in Equai 158 and Equai 175 resuls in he number of primary urns as shown in Equai 176. EQUAION 175: RANSFORMER: PRIMARY WIRE SIZE Curren flowing in he primary windings and ino he swiches are ploed in Figure 46(G and H). o simplify compuais he real curren waveforms can be replaced wih he mid-ramp value (IP mr) and deermine is value csidering he inpu (PI) and oupu (PO) power. he inpu power is shown in Equai 177. EQUAION 177: P I where D is he duy cycle V DCmin ( ) I P mr 2D max ΔB V P ON A core he oupu power is shown in Equai 178. EQUAION 178: EQUAION 176: P O ηp I D ( V DC min V Q ) A core F PWM ΔB max whereη is he efficiency Operaing hese wo equais resuls in Equai 179. EQUAION 179: P O I P mr ηV DC min D max he rms value is shown in Equai 180. EQUAION 180: I P rms I P mr D max 2009 Microchip echnology Inc. DS01207B-page 51

52 FIGURE 46: PUSH-PULL CONVERER WAVEFORMS: PRIMARY SIDE Q1 Command (A) Q2 Command (B) VP1 (C) VP2 (D) VQ1 (E) 2VDC VDC VQ2 (F) IP mr IQ1 (G) IP mr IQ2 (H) (A) Command signal Q1 MOSFE gae (B) Command signal Q2 MOSFE gae (C) Volage VP1 primary winding NP (upper half) (D) Volage VP2 primary winding NP (lower half) (E) Volage Q1 MOSFE (F) Volage Q2 MOSFE (G) Curren flowing in Q1 MOSFE (H) Curren flowing in Q2 MOSFE DS01207B-page Microchip echnology Inc.

53 RANSFORMER: SECONDARY NUMBER OF URNS Once he primary number of urns has been defined NS can be deermined using Equai 173 and Equai 176 as shown in Equai 181. EQUAION 181: MOSFES In Equai 159 (repeaed in Equai 184) he volage he swich mus be able o wihsand (csidering he maximum inpu volage) wice he maximum inpu volage. EQUAION 184: V OU 2A core F PWM ΔB 10 8 V Q2 off 2V DC max V Q1 RANSFORMER: SECONDARY WIRE SIZE As previously seen he secdary curren waveform is quie complex (refer o Figure 47(G and H). However o simplify compuais a cribui o he curren ly during ON is csidered. he average curren shown as IO av nom is he average oupu curren he cverer is designed for. he rms secdary curren (IS) resuls in Equai 182. EQUAION 182: DIODES I Srms I O av nom D max During ON (Q1 ON Q2 OFF) diode D2 is reversebiased. he maximum volage i can olerae is equal o Equai 183. he maximum volage he swiches have o wihsand mus also ake ino accoun he spike ha is generaed by leakage inducance he falling edges of he swich crol signal. he spike is generally esimaed o be 30% higher han he volage he swich. herefore a he end of he ON ime inerval he maximum volage is equal o Equai 185. EQUAION 185: V Q max 2.6V DC max he maximum curren flowing hrough he swiches has been already compued in Equai 179. he maximum VQ max and IP mr are now obained. herefore almos all ha is needed o make he bes device choice is known. All ha remains is o add he analysis of he power dissipaed in he swich which are swiching and DC losses. EQUAION 183: ( V DC max V Q1 ) + V D1 V R D2 he average curren flowing in D1 is he same curren ha is flowing ino he inducor and is value is IO av nom. During he oher ON period (Q1 OFF Q2 ON) hings are reversed; now D1 is reverse-biased and D2 is cducing. he same values as before apply Microchip echnology Inc. DS01207B-page 53

54 FIGURE 47: PUSH-PULL CONVERER WAVEFORMS: SECONDARY SIDE Q1 Command (A) Q2 Command (B) ID1 (C) ID2 (D) VL (E) IO av nom IL (F) IO av nom/2 IS (upper) (G) IO av nom/2 IS (lower) (H) (A) Command signal Q1 MOSFE gae (B) Command signal Q2 MOSFE gae (C) Curren flowing in diode D1 (D) Curren flowing in diode D2 (E) Volage inducor LO (F) Curren in inducor LO (G) Curren flowing in secdary winding (upper half) (H) Curren flowing in secdary winding (lower half) DS01207B-page Microchip echnology Inc.

55 Swiching Losses Figure 48 plos he curren and volage in he swich a he swiching insance. When he swich is urned he volage falls rapidly while he curren has a smooh up-slope since curren canno change abruply in an inducor. As seen in Figure 48 power dissipai is zero. hings are compleely differen when he swich is urned off. Boh he volage and he curren have a smooh slope (an up-slope he former a down-slope he laer) and here is a significan overlap and some n-zero power is dissipaed. FIGURE 48: PUSH-PULL CONVERER: SWICHES CURREN AND VOLAGE V 2VDC IP mr I SW SW Is value can be easily compued using Equai 186. EQUAION 186: 2V DC max SW P Q ac max I P mr where SW equals he rise and fall imes I P mr SW + 2V 2 DC max I 2 P mr SW V DC max he DC losses can hen be compued as shown in Equai 187. EQUAION 187: P Q dc max I P mr V Q D max he oal power dissipaed in he swich is hen equal o Equai 188. EQUAION 188: SW P Q oal max P Q ac + P Q dc 2I P mr V DC max I P mr V Q D max 2009 Microchip echnology Inc. DS01207B-page 55

56 OUPU INDUCOR he inducor is seleced in such a way as o preven he oupu inducor curren from becoming discinuous. he compuais are performed a he edge beween cinuous and discinuous operai meaning when he oupu curren sars from zero a he beginning of he ON period and goes back o zero a he end of he R period. In oher words he inducor curren peak which is also he curren ripple DL is wice he oupu average curren as shown in Equai 189. EQUAION 189: I O ripple 2I O av min ( V N DCmin ( ) V OU ) P ON L O Solving Equai 189 resuls in Equai 190. OUPU CAPACIOR As wih he Buck Cverer design he oupu volage ripple is mainly due o he ESR resuling in Equai 191. EQUAION 191: V OU ripple As seen in previous opologies he oupu capacior value can be deermined from he relaiship shown in Equai 192. EQUAION 192: C O ESR I O ripple I O ripple D max F PWM ( V OU ripple I O ripple ESR) EQUAION 190: L O V N DC min V OU P D 2F PWM I max O av min DS01207B-page Microchip echnology Inc.

57 FULL-BRIDGE CONVERER A Full-Bridge Cverer which is capable of managing higher power levels requires some addiial compens compared o he Half-Bridge Cverer. opology Equais he basic Full-Bridge Cverer opology is shown in Figure 49. ransisors Q1 Q4 and Q2 Q3 are always operaed ogeher driven by he waveform shown in Figure 50. Care mus be aken so ha Q1 Q2 or Q3 Q4 are no ON a he same ime; oherwise a low impedance pah is creaed from VDC o ground. his imposes a maximum value he ON inerval as is discussed in a laer seci. FIGURE 49: FULL-BRIDGE CONVERER OPOLOGY VQ1 Q1 D1 VQ3 Q3 D3 NP NS VD5 D5 LO VDC CI VP VS1 VS2 D6 VD6 CO VOU VQ2 Q2 D2 VQ4 Q4 D4 NS FIGURE 50: FULL-BRIDGE CONVERER WAVEFORM OFF ON ON OFF 2009 Microchip echnology Inc. DS01207B-page 57

58 Q2 ON Q3 ON; Q1 OFF Q4 OFF (INERVAL 0-ON) As shown in Figure 51 curren flows hrough Q3 he ransformer primary and Q2 back o he inpu. he do end of he ransformer is more posiive han he n-do end. FIGURE 51: FULL-BRIDGE OPOLOGY: Q2 AND Q3 ON VQ1 Q1 D1 VQ3 Q3 D3 NP NS VD5 D5 LO VDC CI VP VS1 VS2 D6 VD6 CO VOU VQ2 Q2 D2 VQ4 Q4 D4 NS Inpu Circui Behavior he volage he primary is shown in Equai 193. EQUAION 193: he secdary volage can be compued as shown in Equai 195. EQUAION 195: V P V DC V Q2 V Q3 V DC 2V Q V S V P ( V DC 2V Q ) he magneizing curren increases according o he law shown in Equai 194. Equai 196 shows he curren flowing ino he inducor. EQUAION 194: i M () V P L P V DC V Q L P EQUAION 196: V N DC V O P i L () i L ( 0) L O Oupu Circui Behavior As for he primary winding he do ends of he wo secdary windings are more posiive ha he wo n-do ends. his implies ha diode D5 is cducing while diode D6 is no cducing. he volage he oupu capacior LO is shown in Equai 197. EQUAION 197: V L V S1 V D5 V O ( V DC 2V ) V Q D5 V O V DC V O > 0 DS01207B-page Microchip echnology Inc.

59 Q1 ON Q4 ON; Q2 OFF Q3 OFF (INERVAL 0- ON ) As shown in Figure 52 curren flows hrough Q1 he ransformer and Q4 back o he inpu. he do end of he ransformer is now more negaive han he n-do end. FIGURE 52: FULL-BRIDGE CONVERER OPOLOGY: Q1 AND Q4 ON VQ1 Q1 D1 VQ3 Q3 D3 NP NS VD5 D5 LO VDC CI VP VS1 VS2 D6 VD6 CO VOU VQ2 Q2 D2 VQ4 Q4 D4 NS Inpu Circui Behavior he primary volage is shown in Equai 198. EQUAION 198: Oupu Circui Behavior In his insance as a he primary he do ends are more negaive han he n-do ends which resuls in Equai 200. V P V DC + V Q1 + V Q4 V DC + 2V Q EQUAION 200: he magneizing curren is shown in Equai 199. V S V P ( V DC 2V Q ) EQUAION 199: i M () V P L P V DC + 2V Q L P he oupu inducor volage is shown in Equai 201. EQUAION 201: V L ( V DC 2V Q ) V D6 V O he curren flowing hrough i is shown in Equai 202. EQUAION 202: V N DC V O P i L () i L ( 0) L O 2009 Microchip echnology Inc. DS01207B-page 59

60 Q2 AND Q3 HAVE JUS SWICHED OFF; Q1 AND Q4 ARE OFF When he swiches are open he magneizing curren cinues o flow reversing all volages. A he primary he do end becomes more negaive han he n-do end. he magneizing curren flows hrough D4 he ransformer and D1 as seen in Figure 53. he volage he primary is zero and as shown in Equai 203 he volage he secdary is: EQUAION 203: V S1 V S2 Csequenly boh diodes D5 and D6 are ON and he inducor curren is spli in half beween he wo diode pahs (see Figure 53 and Figure 54). he volage he inducor is shown in Equai 204. EQUAION 204: V L V S2 V O V D6 V O V D6 Since VS2 is very low is magniude is given by he volage drop he secdary winding resisance due o e half of he inducor curren flowing hrough i. Q2 AND Q3 HAVE JUS SWICHED OFF; Q1 AND Q4 ARE OFF he behavior is similar o he previous cdii. he curren pah in he primary is shown in Figure 54. FIGURE 53: FULL-BRIDGE OPOLOGY: Q2 AND Q3 HAVE JUS SWICHED OFF; Q1 AND Q4 ARE OFF (PRIMARY CURREN PAH) VQ1 Q1 D1 VQ3 Q3 D3 NP NS VD5 D5 LO VDC CI VP VS1 VS2 D6 VD6 CO VOU VQ2 Q2 D2 VQ4 Q4 D4 NS FIGURE 54: FULL-BRIDGE OPOLOGY: Q1 AND Q4 HAVE JUS SWICHED OFF; Q2 AND Q3 ARE OFF (PRIMARY CURREN PAH) VQ1 Q1 D1 VQ3 Q3 D3 NP NS VD5 D5 LO VDC CI VP VS1 VS2 D6 VD6 Co VOU VQ2 Q2 D2 VQ4 Q4 D4 NS DS01207B-page Microchip echnology Inc.

61 Design Equais and Compen Seleci INPU/OUPU RELAIONSHIP AND DUY CYCLE he produc of he primary volage muliplied by ON mus equal he produc of he volage muliplied by OFF. Compuing Equai 197 and Equai 204 resuls in Equai 205. EQUAION 205: V O o guaranee ha he wo swiches of a leg are never ON a he same ime ON is limied o be a a maximum percenage of as shown in Equai 206. EQUAION 206: he resuling maximum duy cycle is shown in Equai 207. EQUAION 207: ( V DC 2V Q ) V D D5 where D ON/ and he relaiship ON +OFF is used (see Figure 50) where δ equals 0.8 ON max δ D MAX ON max he primary winding urn can be compued from he equai ha relaes he core flux change (ΔB) he volage across he winding (VP) and he geomerical eniy (A e ) as shown in Equai 209. EQUAION 209: RANSFORMER: PRIMARY WIRE SIZE Since he design specificai POU is known he inpu power can be compued csidering a cverer efficiency of η as shown in Equai 210. EQUAION 210: Solving Equai 210 resuls in Equai 211. EQUAION 211: Wih some approximai and replacing he real curren waveform (ramp a sep) wih a csan value equal o IIN av resuls in Equai 212. EQUAION 212: V P max ON max V DC min D MAX ΔBA e ΔBF PWM A e P OU ηp IN ηv DC min I IN av δ where I IN av is he average inpu curren (see Figure 55 (EGIK)) and δ 0.8 P OU I INav ( ) ηv DC min δ I IN av rms I IN av D MAX RANSFORMER WINDING URN RAIO he maximum ON period will occur when he inpu volage is a is minimum. Using Equai 205 and Equai 206 resuls in Equai 207. EQUAION 208: N S ( V O + V D5 ) ON max ( V DC min 2V Q ) ON max Microchip echnology Inc. DS01207B-page 61

62 FIGURE 55: FULL-BRIDGE CONVERER OPOLOGY: INPU CIRCUI ON OFF Q2 and Q3 Command (A) ON OFF Q1 and Q4 Command (B) VP (C) VDC - VQ2 VQ1 (D) IQ1 VDC - VQ3 (E) VQ4 (F) IQ4 VDC - VQ1 (G) VQ2 (H) IIN AV IQ2 VDC - VQ4 (I) VQ3 IIN av (J) IQ3 (K) (A) Q2 and Q3 swich he command signal (B) Q1 and Q4 swich he command signal (C) Primary volage (D) Volage MOSFE Q1 (E) Curren flowing ino MOSFE Q1 (F) Volage MOSFE Q4 (G) Curren flowing ino MOSFE Q4 (H) Volage MOSFE Q2 (I) Curren flowing ino MOSFE Q2 (J) Volage MOSFE Q3 (K) Curren flowing ino MOSFE Q3 DS01207B-page Microchip echnology Inc.

63 RANSFORMER: SECONDARY NUMBER OF URNS WIRE SIZE he secdary number of urns can be compued from Equai 208 and Equai 209 (see also Figure 56(D and E)). o simplify he compuai of he secdary rms curren value we do no csider ha he cribui o he curren value during OFF is no calculaed (his is due o he relaively shor inerval and small value of he currens). he average value as he medium value during he ramp curren is csidered (see Figure 56(D and E)). Using he previous approximai resuls in Equai 213. EQUAION 213: I O av rms I O nom D MAX SWICHES During ON he maximum volage drop Q1 and Q4 are ha of Equai 214. EQUAION 214: and Similarly he maximum volage drop Q2 and Q3 are ha of Equai 215. EQUAION 215: V Q1 off max V DC max V Q2 V Q4 off max V DC max V Q3 V Q2 off max V DC max V Q1 and V Q3 off max V DC max V Q4 Equai 216 shows he maximum volage drop in Q2 and Q3 in more general erms. EQUAION 216: V Q off max V DC max V Q DIODES Equai 217 shows he volage drop diode D6 when Q2 and Q3 are ON. Similarly Equai 218 shows he maximum drop D5 when Q1 and Q4 are ON. EQUAION 217: V D6 off max V S1 V S2 V D ( V DC max 2V Q ) + V D5 EQUAION 218: V S1 V S2 V D ( V DC max 2V Q ) + V D6 V D5 off max 2009 Microchip echnology Inc. DS01207B-page 63

64 FIGURE 56: FULL-BRIDGE CONVERER OPOLOGY: OUPU CIRCUI ON OFF Q2 and Q3 Command (A) ON OFF Q1 and Q4 Command (B) VS1 (C) ID5 (D) ID6 (E) VL (F) IO av IL (G) (A) Q2 and Q3 swich he command signal (B) Q1 and Q4 swich he command signal (C) Secdary volage (D) Diode D5 curren (E) Diode D6 curren (F) Inducor volage G) Oupu inducor volage DS01207B-page Microchip echnology Inc.

65 OUPU INDUCOR he minimum inducor can be compued csidering he sysem a he edge of he discinuous mode as shown in Equai 219. EQUAION 219: I O peak I O av Solving Equai 219 resuls in Equai 220. EQUAION 220: ΔI O 2 V O L OFF O V O ( 1 D MAX ) L O I O av nom F PWM OUPU CAPACIOR he oupu capacior is seleced o ge he specified oupu ripple. he greaes cribui o volage ripple comes from he capacior ESR and he inducor curren ripple flowing hrough i deermines a volage drop. he capacior value iself can hen be compued using Equai 221 which describes he value of he volage ripple aking ino accoun all he compens. EQUAION 221: V RIPPLE D MAX ESL F I RIPPLE ESR PWM F PWM C O D MAX Neglecing ESL since i is normally very small resuls in Equai 222. EQUAION 222: C O I O ripple D MAX F PWM ( V O ripple I O ripple ESR) where V O ( 1 D MAX ) L O F PWM I O ripple 2009 Microchip echnology Inc. DS01207B-page 65

66 FLYBACK CONVERER As presened in AN1114 (see Inroduci ) Flyback Cverers are widely used in applicais where an isolaed cversi is required for low-power ranges (5W o 150W) and since high oupu volages can be quie easily obained because here is no inducor in he oupu seci. opology Equais - Discinuous Mode A Flyback Cverer can be easily used in eiher Cinuous or Discinuous mode. In Discinuous mode he oupu winding curren goes o zero before he end of he OFF period so ha all he sored energy is ransferred o he load. In Cinuous mode here is some residual energy sored in he ransformer a he end of he ON and OFF periods. Boh of hese modes will be analyzed saring wih he Discinuous mode. Figure 57 shows he basic flyback circui. he swich is driven by a signal like he e presened in Figure 58. FIGURE 57: BASIC FLYBACK CONVERER OPOLOGY VD1 NP NS VP VS D1 CO VOU VDC VQ1 Q1 FIGURE 58: SWICH Q1 COMMAND SIGNAL ON OFF DS01207B-page Microchip echnology Inc.

67 Q1 ON (INERVAL 0 ON) Figure 59 shows he opology for his circui. Inpu Circui Behavior Equai 223 shows he volage he primary when he swich is closed. EQUAION 223: he do end is more negaive han he n-do end. he ransformer behaves as an inducor accumulaing energy in is windings. he curren flowing in he primary is shown in Equai 224. EQUAION 224: I P V P V DC V Q1 V P L P V DC V Q1 L P he increasing curren saring from zero and wih a peak value reached a ON is equal o Equai 225. he sored energy can be easily compued using Equai 226. EQUAION 226: Oupu Circui Behavior he volage he secdary winding is shown in Equai 227. EQUAION 227: V S E N S L 2 P I P peak ( V DC V Q1 ) where he minus sign is due o he fac ha he do end is more negaive han he n-do end erminal. herefore he diode D1 is reverse-biased and no curren flows ino he oupu circui. he oupu curren is supplied by he oupu capacior CO. EQUAION 225: V DC V Q ON I P peak L P FIGURE 59: FLYBACK CONVERER OPOLOGY: INERVAL 0 - ON VD1 NP NS VP VS D1 CO VOU VDC VQ1 Q Microchip echnology Inc. DS01207B-page 67

68 Q1 OFF (INERVAL ON (ON + R)) he circui opology is shown in Figure 60. Inpu Circui Behavior Q1 is now open and curren can no lger flow in he primary winding. As described in AN1114 (see Inroduci ) some circuiry o dissipae he energy in he winding is required (snubber nework); however i will no be analyzed here. he volage he primary can be compued as Equai 228 in which VS is given by Equai 230 and he minus sign is due o he do cversi. EQUAION 228: V P Oupu Circui Behavior As described in AN1114 (see Inroduci ) all volages change sign so ha in he secdary he do end becomes more posiive ha he n-do end and he diode sars cducing curren. he curren ha was flowing ino he primary no lger flows because Q1 is now open and ransfers o he secdary as an iniial curren equal o Equai 229 wih a down slope so ha i reaches zero a ime ON + R V S EQUAION 229: I Speak he volage a he secdary is shown in Equai 230. EQUAION 230: Q1 OFF (INERVAL (ON +R) - ) As previously saed a ime ON + R he curren in he secdary has reached zero. o keep he sysem working in Discinuous mode some ime (F) mus be added as shown in Equai 232. EQUAION 231: I P peak V DC V Q ON V S V O + V D1 ON + R + F his is because he ON inerval depends he inpu volage VDC and he oupu load and if for insance VDC decreases or he oupu curren increases he ON durai mus be lger. F will be csequenly reduced bu will allow he sysem o be discinuous. L P FIGURE 60: FLYBACK CONVERER OPOLOGY: INERVAL ON - R VD1 NP NS VP VS D1 CO VOU VDC VQ1 Q1 DS01207B-page Microchip echnology Inc.

69 Design Equais and Compen Seleci INPU/OUPU RELAIONSHIP AND DUY CYCLE he inpu/oupu relaiship is compued csidering he power flow from inpu o oupu. From Equai 226 he power sored in he primary can be compued as shown in Equai 232. EQUAION 232: E P -- he relaiship beween inpu and oupu power is shown in Equai 233. EQUAION 233: By combining Equai 232 and Equai 233 he oupu volage as a funci of he inpu volage can be deermined as shown in Equai 234. EQUAION 234: Since he ON inerval is a funci of he inpu volage VDC he maximum ON (ON max) correspds o he minimum inpu volage (VDC min). Using hese values (VDC min is a design spec and ON max is usually se o some value so ha ON max + R 0.8) Equai 234 can be revised as shown in Equai 235. EQUAION 235: ( V DC V Q1 ) 2 2 ON L P P OU ηp IN ηrf V O V DC PWM ON L P EQUAION 236: V DC min V Q1 I P peak L P EQUAION 237: I S speak RANSFORMER WINDINGS URN RAIO o deermine he raio (NP/NS) we can have a look a he maximum volage he Q1 MOSFE has o be able o susain. Csidering Figure 57 he maximum volage he swich is equal o ha of Equai 238. EQUAION 238: he primary volage VP is calculaed using Equai 228 and Equai 230 which resuls in Equai 239. EQUAION 239: If a MOSFE is seleced wih a sufficienly high volage raing VQ1 off is csidered as a daum so ha in Equai 239 he ly unknown value is (NP/NS); herefore NP/NS is equal o ha of Equai 240. EQUAION 240: ON max V DC min V Q ON max L P V Q1 off max V DC max V P V Q1 off max V DC max + N P ( V O + V D1 ) V Q1 off max V DC max ( V O + V D1 ) V O V DC min ON max ηrf PWM L P wo oher equais primary peak curren (Equai 225) and secdary peak curren (Equai 229) can be revised o ake ino accoun he VDC min and ON max relaiship as shown in Equai 236 and Equai 237 respecively Microchip echnology Inc. DS01207B-page 69

70 MAXIMUM ALLOWABLE ON o deermine he maximum ON he fac ha he core should never saurae is csidered. his means he volage-ime inerval produc during energy sorage mus equal he volage-ime inerval produc during he delivery of energy o he load. In simpler erms area A1 mus equal area A2 as shown in Figure 61. Csidering ha ON max + R β wih β < 1 as shown in Equai 241 which afer compuai resuls in Equai 242. EQUAION 241: ON max + R β EQUAION 242: ON max ( V N O + V D1 )β S ( V Dc min V Q1 ) ( VO + V D1 ) F PWM RANSFORMER PRIMARY he value of he ransformer primary inducance can be easily compued using Equai 235 replacing ON max wih he compued value from Equai 242 where he design specificai POU max VO 2 /RO resuls in ha of Equai 243. EQUAION 243: L P 2 2 V DC min ON max RηF PWM 2 2V O 2 2 V DC min ON max ηf PWM 2P OU max DS01207B-page Microchip echnology Inc.

71 FIGURE 61: FLYBACK CONVERER OPOLOGY WAVEFORMS: DISCONINUOUS OPERAION ON + R ON R F Q1 command (A) VDC - VQ1 A1 VP (B) (NP/NS)(VO + VD1 ) IP peak IP (C) VO + VD1 A2 (D) (E) (A) Command volage Q1 MOSFE gae (B) Volage he primary winding of he ransformer (C) Curren flowing in he primary winding of he ransformer (D) Volage he secdary winding of he ransformer (E) Curren flowing in he secdary winding of he ransformer 2009 Microchip echnology Inc. DS01207B-page 71

72 RANSFORMER: PRIMARY WIRE SIZE As can be seen in Figure 61(C) he curren in he primary has a riangular shape wih a peak a ON. Based his he rms value can be compued as shown in Equai 244. EQUAION 244: I P peak I PRIMARY rms ON max F PWM In Equai 244 IP peak is calculaed from Equai 225 and ON max is calculaed from Equai 242 which resuls in ha of Equai 245. EQUAION 245: ON max V DC min V Q1 I P peak L P RANSFORMER: SECONDARY WIRE SIZE From Figure 61(E) he curren in he secdary similarly has a riangular shape. he rms value is hen calculaed using Equai 246. EQUAION 246: I Speak I SECONDARY rms 3 N P R F PWM I P peak R F PWM 3 OUPU DIODE he curren flowing hrough he oupu diode is he same curren flowing ino he secdary wih is peak value compued in Equai 228. he average curren can be compued as shown in Equai 247. EQUAION 247: 1 R I D1 av --I S peak OUPU CAPACIOR he oupu capacior can be compued csidering ha i has o supply he whole curren o he load during ON. he crieria o be used is ha he volage droop should be less han he accepable oupu volage ripple. Since he volage droop is equal o Equai 249 he capacior value can be compued as shown in Equai 250. EQUAION 249: he maximum reverse volage he diode during ON can be compued as shown in Equai 248. V DROOP I O max ON max C O EQUAION 248: V Q1 off max ( V DC max V Q1 ) V O EQUAION 250: C O I O max ON max V ACCEPABLE_RIPPLE DS01207B-page Microchip echnology Inc.

73 opology Equais Cinuous Mode In Cinuous mode applicais he basic circui does no change (refer o Figure 57); however he essenial difference is ha he curren (boh in he primary winding and he secdary winding) will no sar and reaches zero during he PWM period. his means ha some energy is sill sored in he sysem when he PWM period is over. he period is now made up of ON and OFF ly. he basic opology equais are exacly he same as before so hey are presened wihou repeaing all of he previous explanais. Q1 ON (INERVAL 0 ON ) Inpu Circui Behavior Equai 251 shows he volage he primary winding. EQUAION 251: he curren in he primary is shown in Equai 252. EQUAION 252: Equai 253 shows he peak curren a he end of ON. EQUAION 253: I P peak Oupu Circui Behavior he volage he secdary is shown in Equai 254. EQUAION 254: V P V DC V Q1 V DC V Q1 I P L P V DC V Q ON L P Oupu Circui Behavior Equai 256 shows he volage he ransformer secdary winding. EQUAION 256: he iniial curren (refleced from he primary) is shown in Equai 257. EQUAION 257: I Speak Design Equais and Compen Seleci INPU/OUPU RELAIONSHIP AND DUY CYCLE Looking a Figure 62(B) he areas A1 and A2 mus be equal so ha he iniial and final poins he ransformer core hyseresis curve coincide as shown in Equai 258. EQUAION 258: V S V O V D I P peak V DC V Q ON ( V DC V Q( 1 ) ) ON ( V O + V D( 1 ) ) OFF V O D he maximum ON/ value can be compued from Equai 258 o occur wih VDC min (where NP/NS is compued in Equai 260) which resuls in Equai D ( V DC V Q1 ) D ON L P V S ( V DC V Q1 ) EQUAION 259: Q1 OFF (INERVAL ON ) Inpu Circui Behavior he volage he primary is shown in Equai ON max ( V N O + V D1 ) S ( V DC min V Q1 ) ( V O + V D1 ) EQUAION 255: V P V S 2009 Microchip echnology Inc. DS01207B-page 73

74 FIGURE 62: FLYBACK CONVERER OPOLOGY WAVEFORMS: CONINUOUS OPERAION ON OFF Q1 command (A) VDC - VQ1 ON A1 VP (B) (NP/NS)(VO - VD1 ON) A2 IP peak IP av IP (C) VO - VD1 ON VS (D) (NS/NP)(VDC - VQ1 ON) IS peak IS (E) (A) Command volage Q1 MOSFE gae (B) Volage he primary winding of he ransformer (C) Curren flowing in he primary winding of he ransformer (D) Volage he secdary winding of he ransformer (E) Curren flowing in he secdary winding of he ransformer DS01207B-page Microchip echnology Inc.

75 RANSFORMER WINDINGS URN RAIO o deermine he raio (NP/NS) he maximum volage he Q1 MOSFE can susain mus be calculaed as shown in Equai 260. EQUAION 260: RANSFORMER: SECONDARY WIRE SIZE he oupu average curren (IO av) mus be deermined. o do so he oupu power (which is e of he design daa) is csidered as shown in Equai 263. EQUAION 263: N P V Q1 off max V DC max ( V O + V D1 ) I O av P OU ( V O + V D1 ) ON max RANSFORMER: PRIMARY WIRE SIZE Csidering a desired oupu power PO as shown in Equai 261 he rms value can be compued replacing he real curren (RAM a sep) wih a csan value equal o IP av. he rms value is hen equal o Equai 262. EQUAION 261: P OU ηp IN ηi P av ( V DC V Q1 ) ON max ( ) ON I P av P OU η V DC V Q1 Correspdingly he rms value is ha of Equai 264. EQUAION 264: I O rms I O av D MAX RANSFORMER: PRIMARY INDUCANCE he minimum LP inducance can be easily compued if he sysem a he edge of he Discinuous mode is csidered. his means ha he IP peak is exacly e half of he incremen in primary curren during ON. herefore he minimum average inpu curren is ha of Equai 265. EQUAION 262: I P rms I P av D MAX EQUAION 265: η( V DC min V Q1 ) ON max P OU I P av min ΔI P 2 V DC min V Q1 ( ) L ON max P Solving LP resuls in Equai 266. EQUAION 266: L P η( V DC min V Q1 )( V DC min V D1 ) ON max 2 F PWM OUPU CAPACIOR he oupu capacior is compued as in he Discinuous mode as shown in Equai 267. EQUAION 267: C O I O max ONmax ( ) V ACCEPABLE_RIPPLE 2009 Microchip echnology Inc. DS01207B-page 75

76 VOLAGE AND CURREN OPOLOGIES In his seci crol loops and volage and curren modes are analyzed. A Buck Cverer is used bu hese echniques are valid for any opology. In all opologies i has been seen ha an inpu/oupu relaiship can be easily obained. So lg as he desired inpu and oupu volages are known all ha remains is o compue he PWM duy cycle. In a perfec world his would be more han enough. Unforunaely in he real world hings behave differenly. he inpu volage can change he load can vary (i.e. swiching he oupu load On and Off) compens have heir olerances aging and emperaure drif and of course noise is always presen. As a resul performances can differ from expecais. o keep he behavior of he sysem under crol during unexpeced siuais a crol loop (hardware and/or firmware) mus be added o perform he operai of crolling he oupu volage. Crol loops allow he design of a circui where he oupu volage will vary as lile as possible when any envirmenal cdii changes. Moreover in some cases crol loops help in prevening dangerous operaial siuais. Curren crol loops can preven flux walking in he ransformers. In he following secis he volage and curren modes of operai will be described for each opology keeping he following wo basic quesis in mind: 1. Wha happens o he sysem oupu volage when he inpu volage suddenly changes? 2. Wha happens o he oupu volage when he load changes? Volage Loop Figure 63 presens he Buck Cverer previously sudied in deail wih some addiial circuiry. A couple of series resisors (R1 and R2) cneced o he oupu ake a reduced ampliude copy (VFB) of VOU. his volage is compared in he error amplifier (EA) wih a reference volage (VREF he volage value desired a he oupu). he oupu signal (VX) is used o rim he duy cycle of he PWM signal ha drives he swich. o undersand how he PWM block works he echnique ha is commly used in he analog implemenai of such sysems will be used iniially. his does no mean ha his is he ly possible implemenai. Laer how o digially implemen he same feaures wih a dspic DSC device is discussed. he analog versi is insead quie easy and inuiive and allows for a simple explanai of how hings work. he PWM block can be replaced by a comparaor ha compares he VX volage o a sawooh signal generaed by a local oscillaor (see Figure 64). Is frequency is he PWM frequency. FIGURE 63: BUCK CONVERER - BASIC VOLAGE LOOP LO R1 CO R0 R2 PWM VX EA VFB VREF DS01207B-page Microchip echnology Inc.

77 FIGURE 64: BUCK CONVERER - BASIC ANALOG VOLAGE LOOP LO R1 CO R0 R2 VCRL VX - EA + VFB VREF Noe: VX VREF VFB VS Sawooh Oscillaor Here is how he sysem works. he VFB volage represening he curren oupu volage is subraced in he error amplifier EA from he reference volage VREF. So a leas for now he funci of he EA block is jus o perform a subraci. Signal VX represens he error beween he desired volage and he real volage he sysem is generaing a ha insan in ime. he VX signal a Seady sae has a very slow moving average value. In he comparaor his signal is compared o he locally generaed sawooh as shown in Figure 65 which resuls in VCRL 1 if VS < VX or VCRL 0 if VS > VX. FIGURE 65: CONROL VOLAGE (VCRL) GENERAED BY COMPARISON BEWEEN ERROR VOLAGE (VX) AND HE SAWOOH WAVEFORM VS VOU decrease VX VOU increase VCRL Noe: VX VREF VFB Since VCRL is he PWM signal used o drive he swiches and is based he value of VX he duy cycle will eiher be small or large. he operai in he EA is such ha when he oupu volage increases he VX volage decreases so ha he PWM duy cycle is reduced and vice versa. he falling edge of VCRL moves according o he posii of VX relaive o VS Microchip echnology Inc. DS01207B-page 77

78 LINE REGULAION he quesi now is: how does his sysem reac when he inpu volage changes? In answering his quesi csider ha he ulimae goal is o keep he oupu as sable as possible agains any variai of he inpu. In addii a couple of basic equais derived previously mus be aken ino csiderai which describe he behavior of he Buck Cverer. Equai 268 shows he curren in he inducor during ON While during OFF he curren is equal o Equai 269. EQUAION 268: I L () EQUAION 269: I L off () ( ) V DC V OU L O V OU L O A Seady sae he curren value a 0 equals he curren value a. his is represened in Figure 66 in he even of a Cinuous operaing mode. he oupu average curren (IO av) (see Equai 270) is also ploed. EQUAION 270: I L peak I L ( 0) I L ( 0) I O av So wha happens if he inpu volage VDC increases? Since he up-slope of he inducor curren is proporial o VDC is slope will increase during ON. Wih some delay due o he LC low-pass filer he oupu volage will change (increase) and wih some addiial delay inroduced by he EA he VX signal will decrease. herefore he duy cycle of VCRL will hen be smaller (see Figure 65). his will reduce he ON ime reducing as a csequence VOU and so afer some ime he oupu will again be a he nominal value wih a shorer duy cycle. Noe ha ly he slope of IL during ON changes. he slope during OFF in he new Seady sae cdii mus be equal o he original e since he sysem is keeping VOU csan. Figure 67 presens he inducor curren before he change in VDC (dashed line) and afer he ransiens have seled down in a new Seady sae (solid line). he iniial and final curren values (a 0 and ) are lower bu a he same ime he peak (poin B) is higher. he average curren (IO av) has no changed as i was expeced since he average oupu volage has no changed. Of course poin B correspds o a shorer period (ON). FIGURE 66: INDUCOR CURREN IN CONINUOUS MODE IL IL peak IO av IL(O) IL() O ON DS01207B-page Microchip echnology Inc.

79 FIGURE 67: VOLAGE MODE CONROL - LINE REGULAION IL B A IO av Iniial Final ON ON 2009 Microchip echnology Inc. DS01207B-page 79

80 LOAD REGULAION he quesi now is: wha happens if he load changes? For example if he RO value changes by diminishing a he very beginning (because of delays in he sysem) he oupu curren will remain as before. his means ha he oupu volage will decrease ly slighly. As a csequence referring again o Figure 64 and Figure 65 he VX signal will be higher and he duy cycle will increase. he behavior of he sysem can be analyzed using Figure 68 which again represens he inducor currens before (dashed line) and afer (solid line) he load change. his ime boh slopes during ON and OFF will remain he same since he inpu volage has no changed and he oupu volage is kep csan by he loop iself. A he beginning since VX increases he duy cycle will increase moving from he original poin A o poin B. his means ha he curren a he end of he PWM period (poin M curren a ) will be a bi larger han he iniial curren (poin H curren a 0). he effec is ha a he end of each PWM period he curren sep is greaer han zero as shown in Equai 271. EQUAION 271: ΔI L () I L ( ) I L ( 0) When he ransien ends he loop has managed o bring he oupu volage VOU back o is nominal value and csequenly he duy cycle is back o is iniial value (here was no change in inpu volage VDC). his means ha in Figure 68 poin B has moved o poin C in he new Seady sae. he oupu average curren has correspdingly increased from IO av iniial o IO av final as i was supposed o do since he load RO has diminished. FIGURE 68: VOLAGE MODE CONROL - LOAD REGULAION C B A IO av final IO av iniial H M ΔIL() ON DS01207B-page Microchip echnology Inc.

81 ADVANAGES AND DISADVANAGES OF VOLAGE MODE As is clearly seen from he previous explanai he implemenai of a volage mode crol is quie sraighforward. he mechanisms of line and load regulai are also quie easy o undersand. his is cerainly e of he main advanages of his approach. Moreover large ampliude signals are usually being deal wih which is a benefi because of heir good noise margin. he key disadvanage of his mode is he delay which is always added in reacing o any change of operaing cdiis. A change in VDC is ly deeced because of is influence he oupu volage so ha from he original even (change in VDC) deeci makes i necessary o wai for he group delay of he low-pass filer. Moreover ce he change in oupu is deeced an addiial delay is inroduced by he EA. All of hese delays mus be aken ino accoun; oherwise a sysem is buil ha is no funcial. A change in he load is immediaely deeced bu again here is a delay inroduced by he EA before he counermeasure can be effecive he swich iming. Curren Mode he curren mode has been inroduced o solve he disadvanages of he volage crol and specifically o reduce he reaci ime of he sysem. I also has some very specific advanages when needing o keep he curren flowing ino an inducor/ransformer winding under crol. A ypical example applicai where he curren mode is efficienly used is a PFC which is a circui whose ask is o force he curren drawn from he AC volage source o be sinusoidal. In his case he curren mode crol direcly operaes he variable (curren) of ineres. As seen in Figure 69 a curren mode implemenai has in realiy wo loops: e exernal crolling he oupu volage (like he e sudied in he previous paragraph) and he secd e (inernal) crolling he inducor curren. he basic idea of he curren mode is o direcly mior he quaniy ha is more direcly respsible for he power cversi. Moreover crolling he curren allows o have a much faser respse ime. Referring o Figure 69 he EA as before miors he oupu volage. Is oupu is used as a reference signal o a secd amplifier ha compares he peak curren flowing ino he inducor o he reference signal from he previous sage. Remember ha when swich Q is closed he inducor curren has a posiive slope waveform (Figure 70). A he beginning of he PWM period (0) he PWM oupu is se acive and he inducor curren cinues o grow unil he curren reaches he value of VX. When hey mach (0 + ON) he PWM signal is rese and remains low unil he nex PWM period sars. his sysem keeps he peak inducor curren under crol. However his is no he ly possible approach as will be seen laer. FIGURE 69: CURREN MODE CONROL LOOP Q Imeas PWM CA VX VFB VREF 2009 Microchip echnology Inc. DS01207B-page 81

82 FIGURE 70: INDUCOR CURREN VX ON he key poin is ha in he Buck Cverer he inducor curren is also he oupu curren so ha crolling i has he direc crol of he quaniy of relevance (VOU). As previously seen in oher sysems for insance in a PFC he inducor curren is he inpu curren and i should be shaped in a sinusoidal way. In his cfigurai he exernally generaed sawooh signal ha was used in he volage mode crol is replaced by he inducor curren signal and is peak value is crolled (limied). he sysem is relaively simple bu also has a couple of drawbacks: I is preferred o be able o crol he average oupu curren no he peak curren (his is because he oupu volage is proporial o he average curren no he peak curren) here are some sabiliy issues LINE REGULAION Wha happens when being in Seady sae he inpu volage changes? How does he sysem respd? his behavior can be bes undersood by looking a Figure 71 (dashed lines represen he original Seady sae). For example as so as VDC changes by increasing he slope of he inducor curren changes (see Equai 268). In his case i will increase. Meanwhile he oupu has no ye changed because of he delay of he oupu LOCO filer. Csequenly VFB has no changed and VX is he same as before. he loop is sill imposing he same inducor peak curren as before. his means ha he up-slope curren signal will cross he VX signal before in poin B compared o he Seady sae poin A (he ransien behavior of he inducor curren is shown wih line from poin L o poin B). he duy cycle is reduced as i should be because of he increased inpu volage. he final new Seady sae cdii is poin C sill he VX line (he peak curren is always he same) having seeper up-slope and he same down-slope. he imporan hing is ha he reaci o he inpu volage change is immediae wihou having o wai for he change o propagae alg he loop. In oher words he sysem respse is much faser. FIGURE 71: PEAK CURREN MODE CONROL - LINE REGULAION B C A VXO IO av iniial IO av final L H M K ON iniial ON final ON during ransien DS01207B-page Microchip echnology Inc.

83 PROBLEMS As seen in Figure 71 while he inpu volage regulai works fine (an increase in VDC brings abou a reduci of he duy cycle) here is a drawback as seen in Equai 272. his is due o he fac ha he peak volage is being kep csan while he oupu volage VOU is proporial o he average inducor volage. EQUAION 272: V OU av R O I O av However as observed in Figure 71 he new cdii is such ha he inducor curren iniial and final values (poins H and K) are lower han before (L and M). his means ha he final average inducor (oupu) curren is lower as shown in Equai 273. EQUAION 273: I O av final < I O av iniial A lower curren will develop a lower oupu volage which will be deeced by he exernal volage loop. In urn i will ry o increase he average (and peak) curren. Bu he inernal loop ries o keep he peak curren csan. An oscillaory effec akes place and cinues for some ime. Anoher suble problem of he peak curren mode is ha he sysem is unsable for duy cycles greaer han 0.5 which can be seen in Figure 72 and Figure 73. FIGURE 72: PEAK CURREN MODE CONROL - D > 0.5 D > 0.5 ΔII ΔIF ΔIF > ΔII FIGURE 73: CURREN MODE CONROL - SLOPE COMPENSAION Down slope Down slope VX Inducor curren 2009 Microchip echnology Inc. DS01207B-page 83

84 As seen in Figure 72 when D < 0.5 a seady sae if for any reas here is a peribai in he inducor curren a he end of he PWM period he ampliude of he peribai is reduced (ΔIF < ΔII) so ha afer a number of PWM cycles he sysem will be back a he iniial cdii. On he crary if he duy cycle is greaer han 0.5 (Figure 73) he same curren peribai will be larger a he end of he period and will grow indefiniely giving rise o an oscillaory behavior (ΔIF > ΔII). Wihou going ino oo many deails boh problems can be easily correced replacing he csan VX peak curren limi wih a down slope signal ha equals VX a he beginning of each period and which has a down slope proporial o half he curren slope during OFF (Figure 73). Load Compensai Wha happens when he oupu load changes? For example if he oupu load changes by decreasing he oupu volage will momenarily decrease and csequenly he VX signal will be higher o compensae for i (see Figure 74). he up slope signal will hen las lger and will cross VX a poin B insead of he original poin A and he duy cycle will correspdingly increase. his will cause he inducor curren level o be higher a he end of he PWM period compared o is value a he beginning (ΔIF is exremely exaggeraed in Figure 74 for clariy). his unbalance will remain while he average curren increases o he new equilibrium value. A his poin he duy cycle is back o is iniial value (no changes in inpu volage VDC) and he sysem has reached a new seady sae. FIGURE 74: PEAK CURREN MODE CONROL - LOAD COMPENSAION A B VX during ransien VX a seady sae ΔIF O ON during ransien ON a seady sae DS01207B-page Microchip echnology Inc.

85 Oher Curren Mode echniques he curren mode previously described wih some deail is no he ly e available. he mos obvious echnique is e where he loop keeps he average (no he peak) oupu curren csan. his is good since he oupu volage is proporial o he average oupu curren. In analog he circuiry is a bi more complex since some kind of low-pass filer mus be added o he curren loop error amplifier. On he crary from a digial poin of view he echnique is very easy since he average value of he curren can be direcly sampled and cvered by he ADC if he sampling rigger is a half he period of he duy cycle. A special regiser in he dspic DSC device allows he cversi o sar operai exacly a his poin (see Figure 75). A secd possibiliy is o implemen he so-called hysereic crol where he curren value can change beween wo values which can be eiher fixed or dynamically compued by he dspic DSC device iself. In his case he inernal comparaors and heir hreshold se by DACs allow implemen of he sysem wihou any inerveni from he CPU (see Figure 76). As seen in Figure 76 as so as he decreasing inducor curren reaches hreshold e he curren limi even in he dspic DSC device akes place and associaed wih i is he forcing high of he pin. As a csequence curren sars rising. As so as i reaches he secd hreshold he faul even akes place and he oupu pin is rese curren decreases and so. he frequency of he generaed PWM is no csan bu i will change as a funci of line and load (remember ha he up slope is proporial o VIN and he down slope is proporial o VOU). FIGURE 75: ADC RIGGER GENERAED BY PWM PERIPHERAL PWM Signal Inducor Curren rigger o ADC o sar cversi SEVCMP Regiser PWM ime Base Couner FIGURE 76: HYSEREIC CONROL IMPLEMENAION WIH A dspic DSC DEVICE dspic DSC DAC1 H1 CL Se Oupu PWMxH CPU PWM IPP DAC2 H2 Faul Rese PWMxL H2 Inducor Curren H Microchip echnology Inc. DS01207B-page 85

86 he inernal comparaors can also be used o implemen a csan ime or a csan off ime (see Figure 77 and Figure 78) where he mach beween he increasing inducor curren and a prese hreshold (DAC oupu) reses he PWM imer ha crols he PWM period. he wo crol modes are essenially he same he ly difference being ha he direc or invered PWM oupu is csidered. FIGURE 77: CONSAN ON IME WAVEFORM Exernal Rese Nominal Period i PWM ime Base Couner ON ON FIGURE 78: CONSAN OFF IME WAVEFORM Exernal Rese Nominal Period i PWM ime Base Couner OFF OFF DS01207B-page Microchip echnology Inc.

87 Crol heory Up o his poin feedback loops have been csidered where he oupu VOU is compared o a reference value and he error signal is used o change some specific feaure (i.e. he duy cycle) of he power modulaor. his is a closed loop sysem and mus be analyzed wih crol heory ools. he problem here is ha he sysem could become unsable if eiher he curren or volage loop is used. In he general circui like he e in Figure 63 and Figure 69 he behavior of any block excluding EA and CA can be known or compued. he design challenge is hen o selec he EA (and CA) ransfer funci o be sure he sysem is sable. Before analyzing he Buck Cverer circui from a crol heory perspecive some basic relaiships mus be formulaed. FEEDBACK LOOPS Figure 79 presens a general crol loop where G(s) and H(s) are he ransfer funcis of he wo blocks (Laplace ransforms of he impulse respses). x() is he inpu signal o he sysem; y() is he oupu; y() is also fed back o he inpu hrough H(s) block whose oupu r() is subraced from he inpu x() o form he error signal e(). Equai 276 shows he produc of he wo erms G(s) and H(s) which is called open loop gain (GOL(s)). EQUAION 276: Figure 80 represens G(s) H(s) GOL(s) and GCL(s). Remember ha he plo is in log scale so ha muliplicais correspd o sums and divisis correspd o subracis. FIGURE 80: G OL ( s) Gs ( )Hs ( ) CONROL LOOP FUNCIONS G(s) GOL(s) fco 1/H(s) f GCL(s) FIGURE 79: CONROL LOOP Some mahemaics o undersand he plo are provided in Equai 277. x() + e() + G(s) - r() Wih compuai as shown by Equai 274 he inpu/oupu relaiship can be derived which is called closed loop gain (GCL(s)). EQUAION 274: GCL(s) can be simplified using Equai 275. EQUAION 275: G CL ( s) G CL ( s) H(s) Gs ( ) Gs ( )Hs ( ) if Gs ( ) >>1 Hs ( ) Gs ( ) if Gs ( ) <<1 y() EQUAION 277: G OL ( s) Gs ( )Hs ( ) G OL ( s) db Gs ( ) db + Hs ( ) db Gs ( ) 1 db Hs ( ) Csequenly in his case where H(s) cs he open loop gain is simply obained moving he G(s) plo rigidly oward he y-axis an amoun equal o 1/Hs). he problem now is: how can i be deermined wheher a sysem represened by Equai 274 is sable? And wha are he cdiis ha make a sysem sable? Boh quesis can be answered wih an approximae analysis. he key poin in crol heory is ha deermining if (and how well) a closed sysem like he e in Figure 79 is sable can be accomplished jus by looking a he behavior of he open loop gain (GOL(s)). In Equai 274 he denominaor mus be prevened from becoming zero; oherwise GCL would be infiniely large as shown in Equai 278. EQUAION 278: 1 + Gs ( )Hs ( ) 0 db 2009 Microchip echnology Inc. DS01207B-page 87

88 Solving Equai 278 resuls in Equai 279. EQUAION 279: he phase of G( s)hs ( ) mus be 180 where G( s)hs ( ) 1 Referring o Figure 80 i is recognized ha he poin where GOL(s) G(s)H(s) 1 is fco (crossover frequency). he phase a his frequency mus be differen from 180. o be he safe side a phase of abou is requesed or correspdingly a phase margin (180 - phase a fco) 45. Wih some simplificais he crieria of sabiliy can be saed as: he slope of GOL(s) a fco mus be -20 db/decade and he phase margin a fco mus be a leas 45. hese are ly sufficien cdiis for he sabiliy bu are widely used because of heir simpliciy. he meaning of he secd crieria should be clear from he previous discussi. he firs crieria can be inerpreed his way. By looking a he GOL(s) ransfer funci i is observed ha i is a raio of polynomials. Wih some effor (a his poin i does no really maer how difficul i can be) he GOL(s) numeraor and denominaor can be ransformed ino he produc of firs order erms (evenually complex numbers) as shown in Equai 280. EQUAION 280: G OL ( s) N k 1 M ( s ) z k l 1 ( s ) p l Each erm of he numeraor is a zero each erm a he denominaor is a pole. In normal cdiis like hose encounered in power supply unis each zero cribues o he open loop gain phase wih a +π/2 phase cribui while each pole cribues wih a π/2 phase cribui. From he poin of view of he loop gain each zero gives place o a change in he slope of he gain iself of +20 db/decade while a pole gives a -20 db/decade slope change. herefore he slope he GOL(s) crieria previously menied can be inerpreed as in he nearby of he crossover frequency (fco) he oal cribui o he loop gain is similar o wha a single pole sysem would provide. POWER CONVERER AND CONROL HEORY Now ha you have a rough idea of he meaning of sabiliy and he crieria o deermine if a sysem is sable refer back o he Buck Cverer wih a volage mode crol loop (Figure 63). I is imperaive o mach he cverer funcis o he general crol heory block diagram and deermine he ransfer funcis. herefore Figure 63 can be redrawn as Figure 81 where G(s) he inpu o oupu ransfer funci is made up of hree blocks: GEA(s) is he error amplifier ransfer funci GM(s) is he ransfer funci of he PWM generaor GLP(s) is he oupu low-pass filer ransfer funci. H(s) he ransfer funci from he oupu o he inpu is absen or beer: H(s) 1. FIGURE 81: BUCK CONVERER VOLAGE MODE LOOP VREF GEA(s) GM(s) GLP(s) DS01207B-page Microchip echnology Inc.

89 he GM(s) ransfer funci is probably no immediaely inuiive. Bu hink of i his way: if he inpu signal is a DC value wih a small ampliude sinusoidal waveform ripple superimposed he oupu will be a PWM signal whose duy cycle value follows he same sinusoidal law around he Seady sae value. Simplisically he inpu/ oupu relaiship is he raio beween he oupu duy cycle range and he inpu sinusoidal ampliude and he frequency is preserved. here are a few differen echniques ha can be used o mahemaically deermine he I/O relaiship. Wihou going ino such deails he imporan hing is ha as so as he opology and he power sysem have been decided GM(s) can be compued. GLP(s) is somehow easier and can be compued analyically csidering he low-pass filer in Figure 82 where he oupu capacior ESR has also been aken ino accoun. FIGURE 82: BUCK CONVERER OUPU SAGE FIGURE 84: GEA(s) ERROR AMPLIFIER RANSFER FUNCION Referring o he previous equais GOL(s) G(s)H(s) GEA(s)GM(s)GLP(s) being H(s) 1. Working in db resuls in Equai 281. EQUAION 281: fz fp f VI L VOU G OL ( s) db G EA ( s) db + G M ( s) db + G LP ( s) db CO known R0 known ESR unknown unknown A his poin GM(s) and GLP(s) are known: he design effor csiss in finding a funci GEA(s) ha makes he sysem sable according o he definii previously given. In an analog design his ranslaes ino he compuai of a few passive compens in sandard compensaing neworks where an op amp is used. One such circui is shown in Figure 83 and is ransfer funci is shown in Figure 84. FIGURE 83: ERROR AMPLIFIER NEWORK C2 he following deails he preferred gain even if GOL(s) is no known: he lower he frequency he higher he gain should be; his is because a very high gain a low frequencies gives place o small Seady sae errors he higher he frequency he smaller he gain should be o reduce he effecs of high frequency noise In beween frequencies i would be bes o have a fairly csan gain I can be ccluded he known and desired GOL(s) value can be saed resuling in Equai 282. EQUAION 282: C1 R2 G EA ( s) db G OL ( s) db G M ( s) db G LP ( s) db VIN R1 GEA(s) VOU In an analog implemenai a graphical solui can easily be found. In a less sysemaic approach differen capacior values can be esed in he circui of Figure 83 and Figure 84 unil a saisfacory solui is found Microchip echnology Inc. DS01207B-page 89

90 Digial Soluis Unil now ly he analog soluis (how he volage and curren mode loops can be implemened in analog) have been csidered. his is because for beginners i is easier o undersand he basic cceps in he analog domain firs and hen cver hem o he digial world. On he crary many experienced cverer designers have grea experience in analog design and he presened maerial is he foundai up which he digial approach is buil. Of course in a digial solui he passive power compens will be used; wha changes is he way he PWM is generaed and how he feedback loop is implemened. An overview of Microchip Swich Mode Power Supply devices follows which provides an undersanding of heir archiecure and he feaures hey provide which can be used o implemen a Swich Mode Power Supply. SWICH MODE POWER SUPPLY (SMPS) dspic DSC DEVICES Microchip s dspic DSC SMPS devices have been creaed specifically o aid designers wih he implemenai of digial swiching sysems. hese devices are 16-bi processors based he well esablished dspic30f and dspic33f family of devices wih hree main building blocks: 16-bi MCU Digial Signal Processor core Inelligen Power Peripheral (IPP) IPP is a superse of hree peripherals: a PWM generaor a high-speed 10-bi analog-o-digial cverer (ADC) and a high-speed comparaor. Nohing new compared o many oher processors? On he crary a lo of new feaures! he key poins are: High performance of he peripherals High degree of inercneci beween he hree menied peripherals ha cooperae o he generai and crol of he PWM oupu waveform wihou he direc inerveni of he CPU he PWM signals (up o four complimenary oupus) can have he same frequency or each e can operae independenly wih a duy cycle resolui as low as 1.05 ns. he PWM can operae in nine differen modes: Sandard edge-aligned PWM Complemenary PWM Push-pull PWM Muli-phase PWM Variable phase PWM Fixed off-ime PWM Curren rese PWM Curren-limi PWM Independen ime base PWM he PWM can generae a se of riggers ha will sar he ADC operai faul signals can sop he PWM operai currens greaer han a defined hreshold in he inernal comparaors can inhibi he PWM oupus and he PWM period couner can be rese by exernal signals o implemen csan-off/- oupus. he high-speed 10-bi ADC can sample up o five signals a he same ime and will always cver wo inpu channels a a ime (usually e curren and e volage). Muliple riggers can sar he cverer operai: Individual sofware rigger Global sofware rigger PWM Special Even rigger PWM generaors rigger imer1 or imer2 period mach PWM generaors curren-limi ADC rigger PWM generaors Faul ADC rigger he comparaors can be used o deec overcurren or as in some curren mode loops be used o deec when he inducor curren has reached a prese value. While he IPP akes care of he greaer par of he generai and managemen of he PWM ADC and comparaor signals he CPU and is DSP engine have pleny of ime o perform he compuais required o close he crol loop in a digial solui. he 16-bi by 16-bi high-speed muliplier and he 40- bi accumulaors allow a very efficien implemenai of even high-complexiy crol algorihms. he operais required o implemen a digial loop are basically a sequence of muliply/accumulae insrucis. he DSP core is capable of implemening such insrucis in a very efficien way. he MAC insruci performs he following operais in e machine cycle (33 ns in dspic30f devices 24 ns in dspic33f devices): 1. Muliply wo values. 2. Accumulae he curren muliply resul o previous sums. 3. Updae he regisers caining he wo facors wih new values for he following mac operai. 4. Incremen poiners so ha hey poin o he values ha will be used laer. Efficien usage of he memory allows implemenai of fas accesses o locais in RAM (and in Flash) wihou reducing he overall speed of he processing uni. Specifically e of he key problems in execuing a mac operai is ha while he muliply/accumulae compuaial par is performed wo new daa mus be feched from he RAM o be ready for he nex ierai. his means ha i mus be possible o make a readaccess o RAM wice in e insruci cycle. Muliple soluis are available. Microchip s approach is o spli (ly for mac class insrucis) RAM ino wo pars (X- RAM and Y-RAM) and duplicae he address and daa DS01207B-page Microchip echnology Inc.

91 bus and he address generaing hardware. wo pahs are hus available hrough which wo new facors can be feched simulaneously. o complee a crol loop implemenai some addiial work is needed o se up iniial cdiis and usually o check ha he resuls are wihin a specified range; however a full crol loop compuai is normally performed in 1 o 2 microsecds. HE PID In boh he volage and curren mode crol loops in he analog solui he objecive was o design he ransfer funci of he error amplifier (GEA(s)) o make he sysem sable. A similar design objecive is o be reached in he digial design. A very commly used building block is he PID (proporial inegraive derivaive). I is normally used also in he analog domain and is found o be a very easy and useful applicai in he digial domain also. As i can be guessed from is name a PID is made of hree basic blocks whose oupus are: Proporial o he inpu he inegral of he inpu he derivaive of he inpu Alhough here are a number of ways hese blocks can be inercneced he mos radiial echnique will be invesigaed where he hree blocks are cneced in parallel as shown in Figure 85. Figure 85 also shows how he PID is insered in he block diagram represening a sysem. he goal of he PID block is o generae an oupu u() ha drives he sysem a hand (he PLAN ) so ha is oupu [y()] maches a reference signal [x()]. he inpu o he PID is he error beween he reference signal (ideal or desired behavior of he PLAN) and he real oupu behavior. Obviously he arge is o operae such ha an error ha is as close o zero as possible resuls. Comparing Figure 81 and Figure 85 i is recognized ha GEA ransforms in he PID croller while he PLAN is he produc of GM(s)GLP(s). In he following saring from he descripi of a PID in he analog domain i will be ransformed ino he equivalen digial PID. For Figure 85 he equai ha describes he behavior in he cinuous ime domain is shown in Equai 283. EQUAION 283: de() u () K P e () + K I e ()d + K D d And is ransfer funci is (Laplace ransform of he impulse respse) shown in Equai 284. EQUAION 284: K I K Us ( ) K P D s 2 + K P s + K I + + K s D s s FIGURE 85: GENERIC SYSEM CONROLLED BY A PID Proporial KP Up() e() x() + Inegraive KI Ui() + U() PLAN y() Derivaive KD Ud() 2009 Microchip echnology Inc. DS01207B-page 91

92 As shown in Figure 86 here are wo zeros and e pole a he origin. A high gain a low frequency is preferred o reduce DC errors while a high gain a high frequency should be avoided (noise and spurious signals would be enhanced). his is why very ofen he ransfer funci is slighly changed o add a secd pole (fp2 dashed ransfer funci). he nex sep is o ransform he analog PID and is equais in he discree ime versi. o do ha a mapping from he s-domain o he z-domain mus be performed using he Equai 285. EQUAION 285: 1 z 1 s where is he sampling period he z-domain is he mos useful domain where sampled signals can be analyzed and sysems synhesized. his is he discree sysems counerpar of he Laplace ransform. I is easy o move from he ime domain o he z-domain and vice versa hrough a ransformai called Z-ransform. One of he mos noable feaures of he Z-ransform is ha a raial ransfer funci in s ransforms in a raial ransfer funci in z -1. his means ha saring from an analog ransfer funci like he e in Equai 280 a ransfer funci is obained in he digial domain which sricly resembles i as shown in Equai 286. EQUAION 286: Hz ( ) N A ( 1 c r z 1 ) r 1 M k 1 ( 1 d k z 1 ) here are a few possible variable ransformais like he e in Equai 285 ha maps he s-domain o he z-domain. Each ransformai has differen characerisics of how he wo domains map o each oher; however he deails are beyd he scope of his applicai noe. FIGURE 86: ANALOG PID RANSFER FUNCION U(s) Pole a he origin -20 db/sec +20 db/sec fz1 fz2 fp2 f DS01207B-page Microchip echnology Inc.

93 he block diagram now is as shown in Figure 87. FIGURE 87: GENERIC SYSEM CONROLLED BY A DIGIAL PID Proporial k p U p (z) VREF + E(z) + Inegraive k i z 1 U i (z) + U(Z) PLAN Derivaive k d ---- ( 1 z 1 ) U d (z) Using he mahemaics shown in Equai 287 he ransfer funci in he z-domain can easily be obained. EQUAION 287: U P ( z) k p Ez ( ) U i ( z) k i E 1 z 1 ( z ) he resuls are shown in Equai 288. EQUAION 288: Uz ( )( 1 z 1 ) [ K A + K B z 1 + K z 2 ]Ez ( ) C Going back o he ime domain (performing he inverse Z-ransform) is shown in Equai 289. k d U d ( z) ---- ( 1 z 1 )Ez ( ) k d k i Uz ( ) k p z 1 + ( 1 z 1 ) Ez ( ) ( k p + k i 2 + k d ) ( k p + 2k d )z 1 + Uz ( ) E d 1 z 1 ( z) ( ) Uz ( )( 1 z 1 ) [ K A + K B z 1 + K z 2 ]Ez ( ) C where K A k P k i k d ---- ; K B k p 2 k d k d + + ; K C ---- EQUAION 289: un ( ) un ( 1) + K A en ( ) + K B en ( 1) + K C en ( 2) un ( ) un ( 1) + ( k p + k i + k d )en ( ) + ( k p + 2k d ) en ( 1) + k d en ( 2) 2009 Microchip echnology Inc. DS01207B-page 93

94 he meaning of such an expressi is ha he curren value of he oupu [u(n)] (in his case he duy cycle of he PWM) is compued from he value of he oupu a he previous insan in ime [u(n - 1)] plus he curren error imes a coefficien (KA) plus he error from previous sep imes anoher coefficien (KB) plus he error from wo seps ago imes a hird coefficien (KC). his is he discree ime domain equai he dspic DSC device is requesed o calculae. Noe ha his operai is performed a maximum ce per PWM period. he erms in Equai 289 can be rearranged as shown in Equai 290. EQUAION 290: un ( ) + un ( 1) + + k p [ en ( ) en ( 1) ] + + k i [ en ( )] + + k d [ en ( ) 2e( n 1) + en ( 2) ] A few commens regarding Equai 290: he proporial cribui depends he difference beween he curren error and he previous error. he inegraive cribui depends he curren error. he derivaive cribui depends he incremen of he error which can be rewrien as Equai If all errors are 0 u(n) u(n - 1). 2. If here is a csan error: a) he proporial cribui is 0. b) he inegraive par presens a n-zero cribui. c) he derivaive par presens a zero cribui. 3. If ly KP is presen (KI and KD 0) when he curren error is very close o he previous error u(n) no lger changes. his explains he residual error received in his cdii. his residual error hen depends also he resolui being used in he ADC and he compuais. 4. If ly KI is presen here is always a cribui even when he e(n) is csan. Again he oal residual error depends he ADC and compuais resolui. EQUAION 291: [ en ( ) 2e( n 1) + en ( 2) ] [ en ( ) en ( 1) ] [ en ( 1) en ( 2) ] Δe n 1 n Δ e n 2 n 1 If saring from Equai 292 and nulling wo ou of hree coefficiens (KB KC 0) resuls in Equai 293 which means ha in realiy a cribui is coming from all hree building blocks. EQUAION 292: un ( ) un ( 1) + K A en ( ) + K B en ( 1) + K C en ( 2) EQUAION 293: un ( ) un ( 1) + K P en ( ) + K I en ( ) + K D en ( ) DS01207B-page Microchip echnology Inc.

95 Behavior of he PID As can be assumed from Equai 284 and Equai 288 changing he values of KP KI and KD changes he behavior of he PID sysem which changes is frequency respse. I is no easy o see he relaiship beween he coefficiens and he ransfer funci. Referring o Equai 287 in he z-domain: If KP 0 and KI KD 0 he ransfer funci is a csan kp If KI 0 and KP KD 0 he ransfer funci has a zero in he origin and a pole in z 1 If KD 0 KP KI 0 he ransfer funci has e zero in z 1 and e pole in he origin he proporial erm ale is capable of sensibly reducing he error bu i canno nullify i because (refer o Equai 290) when he error is almos csan (no maer is absolue value) bu no zero he oupu from he PID compuai is csan. his means ha he proporial erm can sensibly reduce he error bu a he end a n-zero residual error always resuls which canno be compleely eliminaed by he proporial facor ly. o overcome his difficuly he inegral erm represening he memory of he sysem is capable of reducing he proporial residual error o zero. Bu he inegral erm should be used wih caui since i can bring he sysem o oscillai. he cinuous accumulai of n-zero values can bring he sysem o saurae e side and hen o he oher side and so. he derivaive compen helps he sysem o be reacive o sharp changes in he error value since is cribui is proporial o he difference beween curren and previous errors. Unil now nohing has been said abou he values of he hree coefficiens KP KI and KD. here are basically wo mehods ha can be used o deermine heir values: 1. An empirical approach saring wih KP 0 KI KD 0 and rimming he KP value unil a small residual error is received and hen incremening KI unil he sysem reaches an almos zero final error. And finally he kd erm is incremened o improve he performances of he sysem agains sep changes in he inpu error. able 4 can be useful as a saring poin o undersand he relaiship beween he coefficiens and he sysem behavior. I should be noed however ha his able is ly a saring poin since dissimilar sysems behave differenly. ABLE 4: Closed Loop Respse RELAIONSHIP BEWEEN COEFFICIENS AND SYSEM BEHAVIOR Rise ime Overshoo Seling ime Seady Sae Error KP Decrease Increase Small Decrease change KI Decrease Increase Increase Eliminae KD Small change Decrease Decrease Small change 2. he secd approach is more sysemaic and is known as he Ziegler/Nichols mehod. In his echnique sar by incremening he proporial gain (while he oher coefficiens are zero) unil he sysem is a he edge of sabiliy (sep changes are applied o he reference value). In his cdii he oupu is an oscillai wih period and he correspding coefficien is KP. he oher coefficiens are read from ables ha can be found in Crol heory exbooks. I should also be noed ha he full PID equai is no ofen implemened. Ofen ly he proporial-inegrai par (PI) is implemened. his depends he sysem and sysem respses needed Microchip echnology Inc. DS01207B-page 95

96 HE DIGIAL CONROL LOOP WIH HE dspic DSC DEVICE How does he PID fi ino he DC-DC cverer crol loops? hinking in digial erms Figure 63 is redrawn as shown in Figure 87 where he sequence of operais is spli beween peripherals (hardware) of he SMPS pars and compuais (firmware). he feedback volage is cvered by he -board ADC. In he dspic DSC device a 10-bi value is reurned; in realiy i is known ha he cverer always cvers wo signals. his is inended o make available o he user a he same ime a volage and a curren. In his implemenai he curren measuremen is no used. Insead a basic volage crol loop is implemened. FIGURE 88: BUCK CONVERER VOLAGE MODE CONROL LOOP IMPLEMENED ON A dspic DSC DEVICE LO R1 VDC C0 R0 VOU R2 dspic DSC Duy Cycle Regiser DSP Engine MAC Operai A/D PWM IPP 16 VREF PID Coefficiens Buffer KA 16 X 16 Error Samples Buffer e(n) 16 KB 16 X 16 e(n - 1) KC 16 X 16 e(n - 2) (discarded) 40-bi Accumulaor 16 Boundary ess 16 PID Compuai (Duy Cycle) DS01207B-page Microchip echnology Inc.

97 he volage from he ADC is subraced from he reference signal and he resuling error is fed ino he DSP engine o implemen he PID. he DSP engine implemens Equai 289 exacly. he 40-bi accumulaor in he DSP engine is used o accumulae he previous resul values which is value u(n) in Equai 294. EQUAION 294: un ( ) un ( 1) + K A en ( ) + K B en ( 1) + K C en ( 2) he PID oupu (u(n)) is he curren duy cycle value and is wrien ino he IPP PWM duy cycle regiser. his is almos all ha is needed o implemen a basic digial loop. In realiy some aeni mus be paid o he fac ha if he feedback volage is very far from he reference volage large cribuis o he duy cycle are accumulaed. his resuls in he effec ha he duy cycle can become oo large wih a saurai effec. However he PID can recover from his siuai bu i is beer o avoid i since he respse ime is grealy affeced. A good pracice is o clamp he duy cycle value o he PWM period (his is he meaning of boundary ess in Figure 87). In he digial implemenai of he crol loop here are some delays ha mus be aken ino accoun: Analog-o-Digial sample/cver ime PID compuais ime Some n-zero delay in he power compen respse Low-pass filer delay All of hese delays can be summed up as his ime provides a boundary cdii for he sampling frequency in ha i does no make any sense o sample he sysem faser ha he reverse of his ime. In oher words his is he required ime for any change in he sysem o propagae alg he loop. he reverse of his delay ime deermines he maximum sampling frequency ha is reasable o use in he sysem. Remembering he Nyquis sampling heorem which saes ha o be able o recsruc he original signal he sampling frequency mus be a leas wice he maximum frequency of he signal of ineres. his value of 2 is in fac ly heoreical; in he real world i mus be higher. ypical values can be from 6 o 10. Correspdingly he maximum signal frequency ha can be correcly operaed up is six o en imes smaller ha he sampling frequency. o clarify he ccep look a Figure 89(A) where fs is he sampling frequency and fm is he maximum signal frequency value. Opimally rying o speed up as much as possible he operai of he digial loop o have he smalles possible delay in he loop which is he maximum available sampling frequency. Bu why? he key poin is ha if here is a high sampling frequency he maximum signal frequency is high; his means ha he loop can easily respd o high frequency changes in he envirmenal cdiis of he sysem. A graphical example is in Figure 89(B) for wo differen values of fs (fs1 < fs2). Keeping he same raio beween sampling frequency and maximum allowable signal frequency resuls in a larger bandwidh wih fs2 compared o fs1. o furher invesigae he ccep suppose he inpu volage VDC has some ripple added and his ripple is a sinusoid of frequency fo. If he sinusoid frequency is small he sysem can easily adap he parameers of he cverer o compensae for his sinusoidal change in he inpu and give a sable (wihou ripple) oupu. Now cinuously incremen he sine wave frequency. Up o a cerain value he sysem will be able o follow i and compensae; bu for some value of f he sysem will fail o correcly compensae up o a siuai where he sysem delay will be lger han he period of he sinusoid and he loop will compleely fail o crol he oupu volage (see Figure 89(C) wih some simplificais) Microchip echnology Inc. DS01207B-page 97

98 FIGURE 89: SYSEM LOOP BANDWIDH AND SAMPLING FREQUENCY (A) finie se of oupu possible values. For example in a 10-bi ADC ly 1024 oupu values are available while he inpu has an infiniely cinuous range. So wha is he effec of such discreizais? Boh of hem can be csidered as noise ha is added o he signals. However he analysis of he effecs of such addiive noise if far beyd he scope of his applicai noe. Bu an imporan poin regarding discreizai can be inroduced: how he ADC and he digial PWM resolui will impac he behavior of he sysem. he minimum ADC resolui can be compued from he raio of he desired oupu volage ampliude and he required precisi in vols of he oupu volage according o he relaiship shown in Equai 295. fm fs EQUAION 295: V OU res log Δ V OU requesed (B) A 5V nominal oupu when a 1% precisi is required resuls in Equai 296. EQUAION 296: 5 res log bis 0.05 fm1 fm fs1 fm1 Sysem Bandwidh (C) fs1 fs fm2 > fm1 fm2 fs2 As for he digial PWM peripheral here are wo differen resoluis. he digial PWM frequency resolui depends he number of bis used o generae he basic frequency. In SMPS devices he frequency of he PWM can be compued wih Equai 297. EQUAION 297: A B C F PWM PPER where PPER is he regiser seing he PWM frequency fm A B and C represen he sinusoidal superimposed signal o he nominal duy cycle where: A Signal is compensaed by he sysem B Signal is ly parially compensaed C Signal is no compensaed a all One of he main differences beween he analog and he digial loop is ha while in he former all values in ime and ampliude are cinuous in he laer ime and ampliude are boh discreized. ime is discree since as seen above samples of he signals have been aken wih a fixed period repeii rae. Ampliude is discree since he ADC maps inpu values ino a fs he minimum change in frequency correspds o he minimum change in he value of he PPER regiser. In dspic30f devices since he hree Leas Significan bis (LSbs) in he regiser are no available he minimum change is 8 (2 3 8) which correspds o 84 ns. able 5 provides he frequency resolui ha can be received for various values of he nominal frequency. he resolui is ploed in Figure 90. DS01207B-page Microchip echnology Inc.

99 ABLE 5: Frequency FIGURE 90: FREQUENCY RESOLUION Maximum Frequency Minimum Frequency Δf Series Frequency 2009 Microchip echnology Inc. DS01207B-page 99

100 he secd resolui in PWM signals is he duy cycle resolui which a 1.05 ns is very high. A parameer ha is worh compuing is he sysem oupu resolui which is how much he oupu volage will change in respse o a minimum change in he PWM duy cycle. his is a measure of he minimum correci of he oupu volage ha can be generaed (see Equai 298). EQUAION 298: ΔV MIN For example a 100 khz PWM frequency and nominal 5V oupu volage resuls in Equai 299. EQUAION 299: V MIN V OU nom 105ns F PWM Δ 5 105ns mV A final csiderai is ha he PWM resolui should be a leas e bi higher ha he ADC resolui; oherwise he oupu value will cross he boundary beween wo ADC values and he sysem will cinuously ry o reach a sable cdii oscillaing beween hese wo values. CODE EXAMPLE he block diagram in (Figure 91) shows a real implemenai of a volage mode closed loop. he code used in his applicai noe is available for download (see Appendix A: Source Code ). he main program is composed of wo pars: 1. A se of iniializai rouines where all he peripherals used (IPP PWM and IPP ADC) are programmed. 2. A main loop. In he example (Figure 91) i is empy. his is because all he relevan operais are performed in he ADC inerrup rouine. he reas for his is ha he compuais (as previously seen) should be performed as fas as possible o increase he bandwidh of he sysem. he main loop will be periodically inerruped by he high-prioriy ADC Inerrup Service Rouine (ISR) so ha low prioriy asks can be performed in his loop. For insance he managemen of he user inerface or communicai o exernal unis. he ADC inerrup as poined ou is he real core of he firmware. he basic operais performed are: 1. Collec daa from he ADC hardware. 2. Compue he difference beween he currenly read volage value of he sysem (VFB) and he reference volage value. 3. Implemen he PID whose oupu is he duy cycle. 4. Clamp he compued value beween a minimum and a maximum value. 5. Updae he duy cycle wih he currenly generaed (new) duy cycle. he processor is run from is inernal Fas RC (FRC) oscillaor wih a nominal frequency of MHz. An inernal PLL (32x) raises he operaing frequency of he core and peripherals. aking advanage of he clock speed and high performance DSP engine he ADC inerrup rouine is execued in 1.4 µs and he basic PID funcialiy is performed in 1.15 µs. In general erms i is no necessary o updae he duy cycle a each PWM period. As seen before he duy cycle updae frequency is wha deermines he maximum loop bandwidh which is he capabiliy of he sysem o respd o fas changes in he inpu (line regulai) or oupu (load regulai). If for insance he PWM frequency is 200 khz and he volage/curren is sampled and he duy cycle is updaed every oher period his resuls in a 100 khz updae rae which is 10 µs beween wo successive ineracis wih he sysem. If he firmware requires 1.4 µs o execue he ADC rouine 8.6 µs ( ) are sill available o perform all necessary operais such as communicai he UAR and/or he managemen of a human inerface. he dspic DSC device is powerful enough o provide he capabiliy o implemen no ly he raw crol loop bu addiial funcialiy as well! DS01207B-page Microchip echnology Inc.

101 FIGURE 91: PROGRAM FLOW MAIN Ini Rouines Ini Vars Ini Pors Ini I/O Ini imer1 Ini PWM Ini ADC Oupu Volage Ramp-up Endless Loop NOP ADC ISR Dummy Selec Pair Inpu Volage Pair AN2/AN3 Oupu Volage Read Oupu Volage Read Inpu Volage VIN REFIE Compue Error REFIE Compue PID Boundary Checks REFIE 2009 Microchip echnology Inc. DS01207B-page 101

102 DEAILED CODE DESCRIPION In he following seci some deails of he code ha implemens he basic PID funcialiy are analyzed. In his design he code has been designed and esed using Microchip s dspicdem Buck Developmen Board (par number DM300023). Variables Definii A buffer for he error values is allocaed in X-RAM memory in he near area as shown in Example 1. EXAMPLE 1:.seci PidVars_Xmem bss near xmemory ; Pid values Error_n:.space 2 Error_n_1:.space 2 Error_n_2:.space 2 Anoher buffer for he PID coefficiens is allocaed in Y-RAM again in he near area as shown in Example 2. EXAMPLE 2:.seci PidVars_Ymem bss near ymemory ;Pid gain values K_A:.space 2 K_B:.space 2 K_C:.space 2 Some addiial service variables are also allocaed in he near area as shown in Example 3. EXAMPLE 3: MyFlag:.space 2; bi flags Vdesired:.space 2 Vse:.space 2 Vin:.space 2 Vfb:.space 2 Sysemimer:.space 2 Vcrl:.space 2 Code Descripi he main code sars wih some iniializai rouines: IniVars Clears he buffers and iniializes he KA KB and KC parameers. I also iniializes some core regiser bis o obain he desired behavior of he DSP engine (signed mode enabled for DSP muliply operais accumulaor A saurai enabled daa space wrie saurai enabled ineger mode enabled for DSP muliply operais). Poiners are iniialized a he beginning of he wo buffers. IniPors A few pins from por B are used as analog inpus so he cfigurai regiser mus be csisenly programmed. PORE I/O pins are used by he PWM peripheral also and are iniialized as oupu pins. IniIO A fixed low value is oupu he PWM pors a sar-up in order o discharge any cap ha could be soring energy from previous runs. Iniimer1 Iniializes imer1 and enables inerrups. IniPWM One PWM channel is enabled in he following cfigurai: a) Primary ime base provides iming for his PWM generaor. b) DCx regiser provides duy cycle informai for his PWM generaor. c) Posiive dead ime acively applied for all oupu modes. d) Dead ime period (0x0190). e) rigger oupu for every secd rigger even. f) PWM module crols he PWMxH and PWMxL pins. g) Faul inpu is disabled. h) Compare value for PWM ime base for rigger he ADC module ( 8). ADC he cverer is enabled wih a clock of 13.3 MHz; pairs 0 and 1 are cfigured so ha IRQ is generaed and he rigger is in boh cases he PWM1 generaor. SarOps Sars he imers and all operais of he sysem. he arge oupu volage is se (VSE) and he iniial oupu volage is fixed o some small value (VDESIRED 0x40). Afer he iniial phase a ramp is generaed o have a smooh pah from he iniial zero volage o he final value. imer1 wih an inerrup rae of 1 µs is used. A each imer inerrup he desired volage is incremened by a fixed dela unil he final desired oupu volage is reached. hen he main code eners an endless loop which during normal operai is inerruped ly by he ADC ISRs. DS01207B-page Microchip echnology Inc.

103 ADC Inerrup Service Rouine (ISR) his is he real core of he code. he firs hing o do is o deermine which pair of inpu analog channels generaed he inerrup. A compued GOO is used o jump o he correspding piece of code. Since a volage crol loop is implemened ly he oupu volage value (label OupuValues) is of ineres. hen some housekeeping is performed (poiners o he buffer sar address are iniialized). hen he curren volage inpu value is read and adjused as shown in Example 4. In his pori of code W3 poins o he ADC regiser caining he volage value. A lef shif (muliply by wo) is required since he hardware circui o read he oupu volage is a e-half resisors volage divider. EXAMPLE 4: ; Calculae Volage error mov [W3] W0 sl W0 #1 W0 mov W0 Vfb he curren value of he error can now be deermined (see Example 5) remembering ha he error is he difference beween he desired volage and he real volage read hrough he ADC. In his pori of code W0 cains a he beginning of he real oupu volage value and a he end he newly compued error. EXAMPLE 5: ; compuai of proporial error ; ep Vdesired - curren oupu volage ; ep [W1] Vdesired - Vfb mov Vdesired W1 sub W1 W0 W0 he PID is compued using he movsac insruci firs (o iniialize he W6 and W7 regisers and he buffers poiners) and hen he mac insruci (hree imes) as shown in Example 6 which performs he muliply/ accumulae insruci as described in Figure 81. EXAMPLE 6: movsac A [W8]+2 W6 [W10]+2 W7 mac W6*W7 A [W8]+2 W6 [W10]+2 W7 mac W6*W7 A [W8]+2 W6 [W10]+2 W7 mac W6*W7 A ; save value rounded sac.r -#8 [W2] A he end he resul (sored in accumulaor A) is also rounded and saved in a RAM locai (VCRL). he duy cycle value accumulaed in subsequen seps is sored cinuously ino accumulaor A. Some checks he cen of accumulaor A are performed o make sure ha he accumulaed duy cycle never becomes larger ha he period or vice versa becomes oo small. Noe ha o increase he resolui for he PID coefficiens an 8.8 forma is used. his means ha here is an implied comma ( ) beween bi 7 and bi 8 of he 16-bi wide regiser. he nice hing of his represenai is ha i is also possible o use fracial numbers. In oher words a value 1 in his forma is represened by: x Microchip echnology Inc. DS01207B-page 103

104 CONCLUSION he need for higher performance AC-o-DC and DC-o- DC cverers is suppored by he availabiliy of processors such as Microchip s dspic DSC SMPS family of devices. hese devices are able o perform compuaial inensive algorihms while providing specialized peripherals. Covering all aspecs of cverer design is beyd he scope of his applicai noe. he inen is o provide a he very leas he basic ools needed o undersand and design a working cverer. A basic undersanding of he main cverer opologies heir requiremens and heir performance is fundamenal o implemening cverers where maximum performance is achieved. he firs par of his applicai noe deals wih opologies (isolaed and n-isolaed) and behavioral deails of he various sysems are provided. In some insances where appropriae addiial informai is presened such as power csumpi and efficiency. Design equais are provided for all opologies which serve o fill in he gap beween heory and pracical implemenai. Oher design approaches can be used if desired. Digial cverers are closed loop sysems which come wih advanages as well as issues. A fas review of basic crol heory is presened as well as an explanai how o use he powerful ools ha his heory provides oward designing a sable cverer. Some effor has been aken o show how hese resuls can be efficienly implemened using he Microchip dspic DSC SMPS family of devices. Implemenai of a PID sysem is shown and he code is also available (see Appendix A: Source Code ). REFERENCES Ned Mohan ore M. Undeland William P. Robbins Power Elecrics: Cverers Applicais and Design John Wiley & Ss Inc Abraham I. Pressman Swiching Power Supply Design McGraw-Hill 1997 Lawrence R. Rabiner Bernard Gold heory and Applicai of Digial Signal Processing Prenice-Hall Inc A. V. Oppenheim R. W. Schafer Digial Signal Processing Prenice-Hall Inc DS01207B-page Microchip echnology Inc.

105 APPENDIX A: SOURCE CODE Sofware License Agreemen he sofware supplied herewih by Microchip echnology Incorporaed (he Company ) is inended and supplied o you he Company s cusomer for use solely and exclusively wih producs manufacured by he Company. he sofware is owned by he Company and/or is supplier and is proeced under applicable copyrigh laws. All righs are reserved. Any use in violai of he foregoing resricis may subjec he user o criminal sancis under applicable laws as well as o civil liabiliy for he breach of he erms and cdiis of his license. HIS SOFWARE IS PROVIDED IN AN AS IS CONDIION. NO WARRANIES WHEHER EXPRESS IMPLIED OR SAU- ORY INCLUDING BU NO LIMIED O IMPLIED WARRANIES OF MERCHANABILIY AND FINESS FOR A PARICU- LAR PURPOSE APPLY O HIS SOFWARE. HE COMPANY SHALL NO IN ANY CIRCUMSANCES BE LIABLE FOR SPECIAL INCIDENAL OR CONSEQUENIAL DAMAGES FOR ANY REASON WHASOEVER. All of he sofware covered in his applicai noe is available as a single WinZip archive file. he archive may be downloaded from he Microchip corporae Web sie a: Microchip echnology Inc. DS01207B-page 105

106 APPENDIX B: REVISION HISORY Revisi A (June 2008) his is he iniial released versi of his documen. Revisi B (Sepember 2009) his revisi includes he following updaes which clarify he dspic DSC device families ha can be used in cjunci wih his applicai noe. Updaed he secd senence in he las paragraph page 98 by adding a reference o he dspic30f family. Updaed he device family reference o include he dspic33f par family in firs paragraph of he Swich Mode Power Supply (SMPS) dspic DSC Devices seci. Updaed he machine cycle value device family references in he eigh paragraph of he Swich Mode Power Supply (SMPS) dspic DSC Devices seci. DS01207B-page Microchip echnology Inc.

107 Noe he following deails of he code proeci feaure Microchip devices: Microchip producs mee he specificai cained in heir paricular Microchip Daa Shee. Microchip believes ha is family of producs is e of he mos secure families of is kind he marke oday when used in he inended manner and under normal cdiis. here are dishes and possibly illegal mehods used o breach he code proeci feaure. All of hese mehods o our knowledge require using he Microchip producs in a manner ouside he operaing specificais cained in Microchip s Daa Shees. Mos likely he pers doing so is engaged in hef of inellecual propery. Microchip is willing o work wih he cusomer who is ccerned abou he inegriy of heir code. Neiher Microchip nor any oher semicducor manufacurer can guaranee he securiy of heir code. Code proeci does no mean ha we are guaraneeing he produc as unbreakable. Code proeci is csanly evolving. We a Microchip are commied o cinuously improving he code proeci feaures of our producs. Aemps o break Microchip s code proeci feaure may be a violai of he Digial Millennium Copyrigh Ac. If such acs allow unauhorized access o your sofware or oher copyrighed work you may have a righ o sue for relief under ha Ac. Informai cained in his publicai regarding device applicais and he like is provided ly for your cvenience and may be superseded by updaes. I is your respsibiliy o ensure ha your applicai mees wih your specificais. MICROCHIP MAKES NO REPRESENAIONS OR WARRANIES OF ANY KIND WHEHER EXPRESS OR IMPLIED WRIEN OR ORAL SAUORY OR OHERWISE RELAED O HE INFORMAION INCLUDING BU NO LIMIED O IS CONDIION QUALIY PERFORMANCE MERCHANABILIY OR FINESS FOR PURPOSE. Microchip disclaims all liabiliy arising from his informai and is use. Use of Microchip devices in life suppor and/or safey applicais is enirely a he buyer s risk and he buyer agrees o defend indemnify and hold harmless Microchip from any and all damages claims suis or expenses resuling from such use. No licenses are cveyed implicily or oherwise under any Microchip inellecual propery righs. rademarks he Microchip name and logo he Microchip logo dspic KEELOQ KEELOQ logo MPLAB PIC PICmicro PICSAR rfpic and UNI/O are regisered rademarks of Microchip echnology Incorporaed in he U.S.A. and oher counries. FilerLab Hampshire HI-ECH C Linear Acive hermisor MXDEV MXLAB SEEVAL and he Embedded Crol Soluis Company are regisered rademarks of Microchip echnology Incorporaed in he U.S.A. Analog-for-he-Digial Age Applicai Maesro CodeGuard dspicdem dspicdem.ne dspicworks dsspeak ECAN ECONOMONIOR FanSense HI-IDE In-Circui Serial Programming ICSP Mindi MiWi MPASM MPLAB Cerified logo MPLIB MPLINK mouch Ocopus Omniscien Code Generai PICC PICC-18 PICDEM PICDEM.ne PICki PICail PIC 32 logo REAL ICE rflab Selec Mode oal Endurance SHARC UniWinDriver WiperLock and ZENA are rademarks of Microchip echnology Incorporaed in he U.S.A. and oher counries. SQP is a service mark of Microchip echnology Incorporaed in he U.S.A. All oher rademarks menied herein are propery of heir respecive companies Microchip echnology Incorporaed Prined in he U.S.A. All Righs Reserved. Prined recycled paper. Microchip received ISO/S-16949:2002 cerificai for is worldwide headquarers design and wafer fabricai faciliies in Chandler and empe Ariza; Gresham Oreg and design ceners in California and India. he Company s qualiy sysem processes and procedures are for is PIC MCUs and dspic DSCs KEELOQ code hopping devices Serial EEPROMs microperipherals nvolaile memory and analog producs. In addii Microchip s qualiy sysem for he design and manufacure of developmen sysems is ISO 9001:2000 cerified Microchip echnology Inc. DS01207B-page 107

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