Sigmoid Function Approximation for ANN Implementation in FPGA Devices

Transcription

1 Sigmoid Function Approximtion for ANN Implementtion in FPGA Devices Djll Eddine KHODJA, Aiss KHELDOUN, nd Lrbi REFOUFI () Fculty of Engineering Sciences, University Muhmed Boudif of M sil B.P N 6 Ichebili (8), Algeri, Tel/Fx: , E-mil: [email protected] () Signls & Systems Lbortory Institute of Electronics nd Electricl Engineering Boumerdes University [email protected] Abstrct - The objective of this work is the implementtion of Artificil Neurl Network on FPGA bord. This implementtion im is to contribute in the hrdwre integrtion solutions in the res such s monitoring, dignosis, mintennce nd control of power system s well s industril processes. Since the Simulink librry provided by Xilinx, hs ll the blocks tht re necessry for the design of Artificil Neurl Networks except few functions such s sigmoid function. In this work, n pproximtion of the sigmoid function in polynomil form hs been proposed. Then, the sigmoid function pproximtion hs been implemented on FPGA using the Xilinx librry. Tests results re stisfctory. Keywords - ANN, FPGA, Xilinx, Sigmoid Function, power system.. Introduction Monitoring, control nd mintennce of ny element of wide re power system become n importnt issue for ensuring the continuity of electric supply nd voiding the blck out. It is importnt to erly detect the defects tht cn occur in these elements by monitoring their opertions nd then developing methods for pplying dptive control nd preventive mintennce [,, 3]. The fst implementtion of the developed methods is necessry needs for the industry nd the complex (smrt) power systems. These methods my be investigted using severl techniques tht hve different chrcteristics to solve the encountering problems [, 5] The most commonly used techniques re the rtificil intelligence-bsed techniques such s Artificil Neurl Networks (ANN) [5, 6, 7] tht they re esier to implement on electronic circuit bord such s: Digitl Signl Processing (DSP) chips, Appliction Specific Integrted Circuits (ASICs) or Field progrmmble gte rry (FPGAs) [8, 9, ]. The objective of this work is the implementtion of rtificil neurl network on FPGA. This implementtion im to contribute in hrdwre integrtion solutions using FPGA pplied to different res such s monitoring, dignosis, mintennce nd control of power systems. In this study, we begin by dpting ANN to llow optiml implementtion. This implementtion must ensure efficiency, timeless nd minimum possible spce on the FPGA. Then, we schedule the ANN on the System Genertor. The System Genertor to generte VHDL code. This code is verified nd implemented on FPGA Sprtn-like by the ISE softwre from Xilinx Fondtion. ANN nd simultion To ensure efficiency, timeless nd minimum possible spce on the FPGA, we propose network tht contins two hidden lyers the first lyer hs three neurons nd the second hs two neurons, nd output lyer hs two neurons. We conducted mchine lerning using the MATLAB softwre to where we obtin smllest squred error (.7 e -5 ) for inputs, (see Fig.). The design of ANN through the use Simulink is shown in the figure. ISBN:

2 From the obtined results in the testing phse, it cn be found tht lmost ANN in ccordnce (with error E -8 ) with the desired predetermined outputs. 3 ANN Review nd Simultion of the System Genertor. Design of ANN in Simulink Figure Evolution of verge qudrtic error of ANN InOut Input neuron E Input InOut neuron E Input Neuron E3 InOut Out In neuron InOut Out In InOut neuron neurone y{} neuron3 Inputs Lyer Lyer Outputs lyer outputs The Simulink librry provided by Xilinx, works in the sme principle s the other elements of Simulink. It contins blocks representing different functions tht re subjected nd interconnected to form lgorithms [8]. These blocks do not only serve to simultion, but cn lso generte VHDL or Verilog code. In ddition, the librry provided by Xilinx to Simulink, hs ll blocks tht re necessry for the design of ANN except few functions such s sigmoid function.. For this reson, we suggested n implementtion of the sigmoid function through the use of Tylor series [9], the resulting function (of order 5) cuses n error of.5% with respect to the continuous model. In our work, the sigmoid function hs been pproximted in polynomil form s given in the following :function, f ( x) cx e () Eqution () cn be rewritten s follows : In 3 Input B w -Kw w3 w. Test of ANN Once the ANN tht is implemented nd lerning performnce hs reched. Stisfctory tests re investigted, their results re presented in tble. Tble.: Simultion (test) Results of ANN for different cses. Output of ANN MATLAB Function logsig logsig Sfety cse Fult Fult S. e -8. e e -6 S. e e -7. e + In Input Figure ANN using Simulink librry Out B w MATLAB Function Out f ( x) c bx x Where the coefficients c, b, re given by: first: with: c e b e e 3 where V/ F 3 () ISBN:

3 nd : F In Gtewy In - Constnt Constnt. x.59 CMult Constnt b z - (b) Mult.5 [:b] Slice b - b AddSub b - b AddSub3 b + b AddSub x.33 CMult not Inverter [:b] Slice [:b] Slice b b sub not AddSub Inverter Modeling the resulting function is given by Xilinx s shown in Fig.3:, hi lo Conct Constnt3 Constnt sel d d d Mux Sy stem Genertor Figure 3 modelling of sigmoid function. Out Gtewy Out simulink xilinx 6 8 Figure Comprison of Sigmoid functions of Simulink nd Xilinx Out Figure. shows tht the sigmoid function curve obtined by Simulink is in ccordnce with the curve of sigmoid function obtined by Xilinx. The design of ANN using Simulink is shown in Figure.5 According to the construction of ANN in the Simulink/Xilinx the system genertor cn lso generte the VHDL code. Implementtion of ANN in FPGA We plce the entire contents of the block of ANN in the sme subsystem, with single genertor system, then, it genertes the VHDL code (see figure.6). This prt is devoted to description of the implementtion of ANN on FPGA. In order, to do this, we use the Xilinx System Genrtor. Synthesizer: you click on Synthesizer to find spce resources occupied by the VHDL (see figure.7) The result is displyed in the Synthesizer s given in tble.. From the obtined results shown in the tble, we notice tht the VHDL code occupies n re of 8% on FPGA, mens tht the FPGA type Sprtn xcse-6tq does not support this VHDL code. However, the implementtion of the code obtined in system Sprtn3 gives the results shown in tble 3. From this tble, we found tht the code implemented in Sprtn3 tkes only 63% of storge spce of FPGA. 5 Conclusion In this work, we proposed simple lgorithm for the implementtion of the ANN. The proposed hrdwre synthesis lgorithm is performed by the System Genertor. Routing nd implementtion in FPGA type SprtnE ws mde by ISE Foundtion. The use of high-level design tool, System Genertor is very beneficil for the verifiction of the behviour of the lgorithm in Simulink. The simultions for the sigmoid function show tht the obtined results using Xilinx give the sme performnce s the sigmoid function obtined by Simulink. Furthermore, the implementtion of the obtined code using two different systems Sprtn nd Sprtn3 leds to the conclusion tht the FPGA type Sprtn3 supported the generted VHDL code gives dequte results. Finlly, one cn conclude tht the implementtion of functions in FPGAs is esier becuse now VHDL code of ny circuit cn be generted not only by n dvnced lnguge but lso by the softwre MATLAB. This gives us the bility to simulte ny function in simulink, using the librry of Xilinx fter tht the ltter is directly converted into VHDL by System Genertor. ISBN:

4 InOut InOut Input E Input neuron InOut neuron Out In neuron E Input E3 neuron InOut Out In InOut neuron neuron y{} Inputs Tble. : Spce used on FPGA neuron3 Lyer Lyer Lyer of outputs Output Fig.5 progrmming ANN using SIMULINK Tble.3: Summry of used spce on the FPGA. Fig.7 Spce occupied by the implementtion. References [] G.Zwinngelsten, «Dignostic des défillnces: théorie et prtique pour les systèmes industriels», Ed. Hermès Pris Figure 6 System Genertor interfce. [] B.Dubuisson ; «Détection et dignostic des pnnes sur processus», Technique de l ingénieur. R7597,99. [3] B.Chette, DJ.Khodj, «Dignostic en temps réel des défillnces d un ensemble Moteur synchrone-convertisseur électronique en utilisnt les réseux de neurones rtificiels», Journl Electrotekhnik, Moscou /3, pp:6- ISBN:

5 Tble 3 Summry of used spce on the FPGA [] DJ.Khodj, B.Chette, «ANN system for identifiction nd loclistion of fillures of ntomwed electric synchronous drive», nd Interntionl Symposium on Electricl, Electronic nd Computer engineering en Exhibition, Mrch, -3, NEU-CEE, NICOSIA, TRNC pp : [5] DJ.Khodj, B.Chette, «Development of Neurl Network module for fult identifiction in Asynchronous mchine using vrious types of reference signls», nd Interntionl Conference PHYSICS nd CONTROL, August,-6, Physcon 5, S t Ptersburg, Russi, 5,. pp : [6] V.A.Tolovk. «Réseux de neurones : Apprentissge, Orgnistion et Utilistion», Ed, Entreprise de rédction de journl Rdiotekhnik Moscou,. [7] N. Moubyed, "Detection et Loclistion Des Défuts Dns Les Convertisseurs Sttiques", 6TH Interntionl Conference on Electromechnicl nd Power Systems, Chişinău, Rep. Moldov, October, 7. [8] K. Roy-Neogi nd C. Sechen, "Multiple FPGA Prtitioning with Performnce Optimiztion", IEEE Computer Society, Proceedings of the Third Interntionl ACM Symposium on Field- Progrmmble Gte Arrys (FPGA 95), 995. [9] K. Renovell, P. Fure, J.M. Portl, J. Figuers nd Y. Zorin, "IS-FPGA: A New Symmetric FPGA Architecture With Implicit SCAN", IEEE ITC Interntionl Test Conference, Pper 33., /. [] Areibi, G. Grewl, D. Bnerji nd P. Du "Hierrchicl FPGA Plcement", CAN. J. ELECT. COMPUT. ENG., VOL. 3, NO., Winter 7. ISBN: