This document explains various evaluations of digital audio interface receiver LC89091JA.

Transcription

1 LC8909JAGEVK LC8909JA Digital Audio Interface Receiver Test Procedure This document explains various evaluations of digital audio interface receiver LC8909JA. Table of Contents. Function Check (PC doesn't use) P-. Function Check (PC uses) P-. Consumption Current Measurement P-. Lock-up Time Measurement P-. PLL Clock Jitter Measurement P-. Jitter Tolerance Measurement P Example of Sound Qualitiy Evaluation Circuit Configuration ( channel stereo audio) P Example of Sound Qualitiy Evaluation Circuit Configuration (. channel multi-channel audio) P- 9 Modification History Ver Date Description First edition /9

2 . Function Check (PC doesn t use) LC8909JAGEVK Test Procedure Basic operation of LC8909JA can be checked..v MHz CN Analog TOS TOS JP JP LC8909 D D D.7MHz SDIN ADC (Slave) J CN CN LC8909JAGEVB Register control YES NO PLL error monitor LED (D) PC input TOSLINK COAXIAL Non-PCM monitor LED (D) PC ADC connection YES NO Emphasis monitor LED (D) PC Linear-PCM Non-PCM Emphasis input D Emphasis LED indication D PLL error D Non-PCM output Off Turn on Off ADC data No Off Off Off Demodulation data Yes Turn on Off Off Demodulation data Off Off Turn on Demodulation data /9

3 . Function Check (PC uses) LC8909JAGEVK Test Procedure PC can be connected by USB and operation of LC8909JA can be checked by IC control. PC USB MHz CN Analog TOS TOS JP JP LC8909 D D D.7MHz SDIN ADC (Slave) J CN CN LC8909JAGEVB Register control YES NO PLL error monitor LED (D) PC input TOSLINK COAXIAL Non-PCM monitor LED (D) PC ADC connection YES NO Emphasis monitor LED (D) PC Setting Item R/W Adr D7 D D D D D D0 System R/W 00h "0" MPSEL DATWT ERRWT ADMODE AMPOPR PDMODE SYSRST Clock R/W 0h "0" "0" XOUTCK PRSEL PRSEL0 PLLDIV PLLDIV0 PLLACC Data R/W 0h NPMODE ERRSEL GPOSEL GPOSEL0 DATMUT THRSEL DINSEL DAFORM Fs R 0h ERRFLG FSC FSC FSC FSC0 R 0h CS7 CS CS CS CS CS CS CS0 Channel status R 0h CS CS CS CS CS CS0 CS9 CS8 R 0h CS CS CS CS0 CS9 CS8 CS7 CS R 07h CS CS0 CS9 CS8 CS7 CS CS CS R 08h CS9 CS8 CS7 CS CS CS CS CS /9

4 . Consumption Current Measurement LC8909JAGEVK Test Procedure The consumption current of LC8909JA can be measured. JP socket remove and a current measurement machine insert in TP and TP. Current limiting resistor (R, R8, R0, R) of LED remove. The current of various states can be measured by register control. (Current at the time of power down, etc.) PC.V USB TOS TOS J MHz JP JP CN CN LC8909 R R0 R8 D TP TP D D CN LC8909JAGEVB (Removal).7M Hz JP (Removal) R Register control YES NO PLL error monitor LED (D) PC input TOSLINK COAXIAL Non-PCM monitor LED (D) PC ADC connection YES NO Emphasis monitor LED (D) PC Setting Item R/W Adr D7 D D D D D D0 System R/W 00h "0" MPSEL DATWT ERRWT ADMODE AMPOPR PDMODE SYSRST Clock R/W 0h "0" "0" XOUTCK PRSEL PRSEL0 PLLDIV PLLDIV0 PLLACC Data R/W 0h NPMODE ERRSEL GPOSEL GPOSEL0 DATMUT THRSEL DINSEL DAFORM Fs R 0h ERRFLG FSC FSC FSC FSC0 R 0h CS7 CS CS CS CS CS CS CS0 Channel status R 0h CS CS CS CS CS CS0 CS9 CS8 R 0h CS CS CS CS0 CS9 CS8 CS7 CS R 07h CS CS0 CS9 CS8 CS7 CS CS CS R 08h CS9 CS8 CS7 CS CS CS CS CS /9

5 . Lock-up Time Measurement LC8909JAGEVK Test Procedure Time until an error flag is canceled is measured after input. It is set as register ERRSEL (address 0h, D) =. PC USB MHz CN TOS TOS JP JP TP LC8909 TP9 D D D.7M Hz signal ERR output J CN CN LC8909JAGEVB Register control YES NO PLL error monitor LED (D) PC input TOSLINK COAXIAL Non-PCM monitor LED (D) PC ADC connection YES NO Emphasis monitor LED (D) PC PLL unlock PLL lock input ERR output (ERRSEL=) Wait time (ERRWT register) Data output start Lock-up Time /9

6 . PLL Clock Jitter Measurement LC8909JAGEVK Test Procedure The clock jitter of master clock O is measured with a dedicated device. s input recommends a caxial with little influence of reflection..v MHz CN Agilent 0A etc TOS TOS JP JP LC8909 D D D TP0.7M Hz O output J CN CN LC8909JAGEVB Register control YES NO PLL error monitor LED (D) PC input TOSLINK COAXIAL Non-PCM monitor LED (D) PC ADC connection YES NO Emphasis monitor LED (D) PC /9

7 LC8909JAGEVK Test Procedure. Jitter Tolerance Measurement including jitter inputs to LC8909 and checks whether data is correctly receivable. The frequency and amplitude of impressing jitter are based on IEC098-. Please refer to the equipment manual for a measuring method..v Audio Precision SYS-7 etc MHz CN TOS TOS JP JP LC8909 D D D.7M Hz J CN CN LC8909JAGEVB Register control YES NO PLL error monitor LED (D) PC input TOSLINK COAXIAL Non-PCM monitor LED (D) PC ADC connection YES NO Emphasis monitor LED (D) PC 00 IEC098-: Receiver jitter tolerance template Jitter tolerance (UI) 0 Hz, 0UI 00Hz, 0.UI >00kHz, 0.UI Jitter frequency (Hz) 7/9

8 LC8909JAGEVK Test Procedure 7. Example of Sound Qualitiy Evaluation Circuit Configuration ( channel stereo audio).v MHz CN TOS TOS JP JP LC8909 D D D.7M Hz J CN CN LC8909JAGEVB Register control YES NO PLL error monitor LED (D) PC input TOSLINK COAXIAL Non-PCM monitor LED (D) PC ADC connection YES NO Emphasis monitor LED (D) PC 8/9

9 LC8909JAGEVK Test Procedure 8. Example of Sound Qualitiy Evaluation Circuit Configuration (. channel multi-channel audio).v MHz CN ch TOS TOS JP JP LC8909 D D D.7M Hz DSP J CN CN LC8909JAGEVB Register control YES NO PLL error monitor LED (D) PC input TOSLINK COAXIAL Non-PCM monitor LED (D) PC ADC connection YES NO Emphasis monitor LED (D) PC ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer applicationby customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 9/9