A low- power digital PWM DC/DC converter based on passive Sigma- Delta modulator

Transcription

1 S.K. Hoon, F. Maloberti, J. Chen: "A lowpower digital PWM DC/DC converter based on passive SigmaDelta modulator"; Proc. of the IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe, May, Vol. 4, pp xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 A LowPower Digital PWM DC/DC Converter based on Passive SigmaDelta Modulator Siew Kuok Hoon *, Franco Maloberti **, and Jun Chen *** * Wireless Analog Technology Center, Texas Instruments Inc., Dallas, USA, siewkh@ti.com ** Department of Electronics, University of Pavia, Pavia, Italy, franco.maloberti@unipv.it *** Advanced Analogic Technologies, Dallas, USA, junchen@analogictech.com Abstract This paper describes a novel method to obtain a digital control for PWM DC/DC switching regulator. A passive sigmadelta modulator which output is suitably processed obtains the PWM control and makes the control loop. The output of the sigmadelta enables generating the discretetime PWM control. The proposed method has been extensively simulated at the behavioral level. Results show that the method can be effectively employed in low power DC/DC converters. I. INTRODUCTION The scenario of portable power management system changed recently because of the explosive demand in portable devices such as cellular phone, PDA (personal digital assistant) and digital camera. The DC/DC converter plays a critical role in the power management system in keeping long battery life while providing stable supply and noise isolation [1]. The main requirements of DC/DC converter are high efficiency, low cost and small solution size. With the advancement of deep submicron technology, DC/DC converter based on digital controller exploits the advantage of the small digital system realization and offer as an attractive solution especially for the Systems On Chip (SOC) implementations. Moreover, digital controller poses the advantages of less sensitive to noise, process parameters, and low quiescent current [2]. Another feature is also the flexibility to modify control and stability compensation scheme corresponding to a change in external components, which can be critical to product cycle time in today s competitive market environment. On the other hand, digital controller for DC/DC converter suffers DC accuracy issue due to the finite signal resolution processed by the A/D converter and the time delays in the control loop due to the computation of the A/D converter and control processor. This paper presents a digital PWM DC/DC converter using a passive sigmadelta modulator. The benefit of the method is low power and less sensitive to mismatch as compared to the use of flash A/D (analogtodigital) converter in conventional digital PWM controller. The voltage ripple is low even with a relatively low oversampling. If higher accuracy is required the system can conveniently increase the oversampling rate of the sigmadelta modulator instead of modifying the A/D converter design and with a relatively small increase of power consumption. II. CONVENTIONAL TECHNIQUE A DC/DC buck converter system as illustrated in Fig.1 can replace the analog controller with a digital controller. The conventional analog loop including a filter, a comparator and ramp generator is replaced by a digital controller to produce the PWM signal. The only analog part is the A/D converter. The challenge is to design a low power, high immunity to noise and process variation, low complexity A/D converter. The most common A/D converter used is a multibit flash A/D converter. VS CMP digital controller RAMP (from OSC) Figure 1. Proposed DC/DC Switching Regulator VREF However, the flash architecture requires high power consumption (an Nbit converter requires 2 N comparators) A/D /05/$ IEEE. 3873

3 and large silicon area. In [3], instead of using the flash A/D converter a delayedline A/D converter has been used. The implementation of the delayedline converter is purely digitaltype. However, the performances of the delayedline depend on the matching of thresholdvoltages of the chain inverters. The optimum solution is to have digital control and at the same time flexible process portability and small in area. Solutions described in [4],[5] use digital controller and an analog section made by a window comparator with 2 decision levels. Here, the optimal window range is the critical and difficult design parameter. Solutions in [6],[8] use sigmadelta converters. The sigmadelta modulation is used primarily in driving the power switches, thus reducing EMI and switching noise. Using high variable frequency switching can be problematic and PWM power switching scheme becomes preferable. Finally, [9] uses a PWM DC/DC converter based on a sigmadelta modulator but the active implementation costs area and power. III. PROPOSED TECHNIQUE This switching regulator, with proportional control, uses a passive firstorder signal delta modulator [10] as input stage of the control circuit. The output of the sigma delta is a bitstream at the main clock frequency, f CK. The processing (PROC) block consists of an integrateanddump by N clock periods and a digital to dutycycle converter that produces a PWM pulse at f CK /N. Fig. 2 shows the block diagram of the system. Figure 2. Proposed DC/DC Switching Regulator A simple RC switched capacitor circuit replaces the integrator normally used in a sigmadelta modulator. Capacitor is charged to the regulated voltage minus the twolevels DAC output during phase 1 and during phase 2, capacitor is in parallel to C 2 through V set. Therefore, the z transfer function of the SCRC is V c = V ε V DAC where V ε is the quantization error, it results V DAC (z) = (V reg V set ) z 1 (C 2 )z 1 V ε ( C C 2 z 1 ) (C 2 )z 1 Therefore, the sequence of the digital bitstream driving the digitaltoanalog converter (DAC) depends on the term (V reg V set ) and the quantization error of the modulator, V ε. The noise shaping is modest and, actually, its effect is causing an acceptable degradation of performances as verified with behavioral level simulations. The accumulation of the output bitstream will lead to an averaging operation: the term (V reg V set ) is preserved while the quantization noise is reduced by N 1/2. The amplitude at the output of the accumulateanddump by N clock period is used as input of a digitaltoduty cycle converter. The value of the duty cycle is discrete and holds k/n, where k is the number of 1 at the output of the sigmadelta in an Nclock period. The generated pulse, decimated by N with respect to f CK is used for the PWM control. Since the system requires a sequence of PWM pulses with continuoustime duration, the output of the system accomplishes the request by generating a sigmadelta like modulation of the PWM duration by using N1 possible dutycycles (k/n; k=0 N). In addition to the above features the system can work with very low power consumption. The power required by the switched capacitor circuit is negligible being the equivalent resistance of the SC structure very high. The power required by the comparator can be in the µw range or below for clock frequency as high as 16 MHz. With this frequency, assuming =0.2pF the equivalent resistance T/ is 312 KΩ. If the reference voltage used by the DAC is 0.1V the SC current is 0.3 µa. IV. SIMULATION RESULTS The proposed modulator has been simulated in the MatlabSimulink! environment. Fig. 3 shows the highlevel block diagram. Three blocks make the control loop. The PWM control is monitored together with the regulated voltage. The output to workspace enables postprocessing. C V C (z) = 1 z 1 C 2 z V 1 DAC V reg V set [ ] since Figure 3. Simulink block diagram of the DC/DC converter. 3874

4 Fig. 4 shows the used model for the buck regulator. The schematic is the representation of the VI equations of the circuit elements used in the buck converter [11]. In addition, the ESR resistance in series with the capacitance (in parallel with the load K) is accounted for. The saturation block ensures that the current in the inductor flows always in the direction of the load. Figure 4. Behavioral model of the buck voltage regulator. Figure 6. Regulator output voltage and P control only Fig. 5 shows the model of the passive sigmadelta modulator. The values indicated in the diagram correspond to C 2 / =4. A random number generator enables the studying of a possible noise affecting the reference or the input terminal. The descriprion of the processing block is not given here being already discussed the digital functions. Figure 7. Regulated voltage with PD control Figure 5. Passive sigmadelta modulator. The performance of the buck converter using only proportional control (P) and proportionalderivative (PD), based on the design parameters in Table I, are compared in Fig.6 and Fig.7. It is apparent the derivative component is essential in damping the overshoot and providing stability compensation. The damping comes from a proper tradeoff between response improvement and complexity. PID is also possible with additional passive SC filters before the sigmadelta or with suitable processing in the digital domain. The noise on the V set is ± 2mV peak. Observe that, after a transient the voltage settles around the set value 2.23V. The duty cycle control varies between 6/16 and 9/16 as shown in Fig. 8. The average duty cycle is 7.32 as required to achieve the value of the setting. Having discrete values for the duty cycle slightly affects the regulated voltage. TABLE I. Design Paramenters Parameter Value Dimension Main clock frequency 16 MHz PWM frequency` 1 MHz L 20 µh C 40 µf R in series with C 0.1 Ω R_load 8 Ω V_set 2.23 ±0.02 V Figure 8. PWM duty cycle generated by the Σ _processor 3875

5 Figure 9. Expanded view of the regulared voltage As shown in Fig. 9 there is some ringing in the crest output value. The fluctuation is below 2mV. The effect of the used control is also evident looking at the spectrum of the regulated voltage after the transient. Fig. 10 compares the spectrum at the output of a DC/DC regulator with digital control and that of a conventional buck converter using the same design parameters. The result is that the noise spectrum with sigmadelta conversion is higher than the conventional buck converter, but it has tones lower than 80dB. They are at a lower level than the peak tones produced by the buck. The obtained spectrum depends on the value of the regulated voltage and the design parameters but the above features remains. Figure 10. Spectrum of the regulated voltage after the intitial transient. V. CONCLUSION This paper presented a new approach for obtaining a digitalcontrolled switchedmode DC/DC regulator. The proposed method utilized low power sigmadelta A/D conversion. The PWM signal has a discrete duty cycle that changes like the signal at the output of a multilevel sigmadelta modulator. Simulated performances show limited degradation with respect to a conventional buck converter. However, the method brings about a number of advantages: the design is small and because of the passive implementation of sigmadelta modulator, the overall power consumption is very low. Design consideration such as mismatch requirement can be less stringent due to the oversampling scheme. In addition, PID control is made possible in the analog or in the digital domain making the design flexible. The PWM powerswitching scheme makes the design suitable for the wireless portable power management application. The proposed solution uses a fixed PWM frequency (f ck /N). However, it is also possible using a timevarying decimation factor, N, thus permitting a modulation of the frequency used in the PWM. REFERENCES [1] B. Arbetter, R. Erickson, and D.Maksimovic, DCDC converter design for batteryoperated systems, IEEE PESC '95. Vol. 1, pp Jun [2] T.W.Martin, S.S.Ang, Digital control for switching converters, IEEE ISIE 95, Vol.2, pp , Jul [3] B.J.Patella, A.Prodic, A.Zirger, and D.Masimovic, Highfrequency digital PWM controller IC for DCDC converters, IEEE Trans. On Power Electronics, Vol.18, pp , Jan [4] Philips Semiconductor Product Datasheet, TEA1206 [5] F.Sluijs, K.Hart, W.Groeneveld, and S.Haag, Integrated DC/DC converter with digital controller, Intl Symp on Low Power Electronics and Design, pp.8890, Aug [6] J. Paramesh, and A. Jouanne, Use of sigmadelta modulation to control EMI from switchmode power supplies, IEEE Trans. On Industrial Electronics, Vol..48, pp , Feb [7] A.Hirota, S.Nagai, and M.Nakaoka, A novel deltasigma modulated DCDC power converter utilizing dither signal, IEEE PESC 00., Vol.2, pp , Jun [8] G.Capponi, P.Livreri, G.M.Di Blasi, F.Marino, and E.Cannella, A new analysis technique for fast transient power conversion system based on sigmadelta modulator, INTELEC '03, pp , Oct [9] G.M. Cooley, T.S.Fiez, and B.Buchanan, PWM and PCM techniques for control of digitally programmable switching power supplies, IEEE ISCAS 95, Vol..2, pp , May [10] F.Chen, and B.Leung, A 0.25mW lowpass passive sigmadelta modulator with builtin mixer for a 10MHz IF input, IEEE Journal of SolidState Circuits, Vol.32, pp , Jun [11] S.K.Hoon, J.Chen, and E.Yu, Analysis and Simulation of switching regulators using a circuitoriented model in MATLAB, Intl. Signal Processing Conf. and Global DSP Expo, pp , Mar