Implementation of Low Power Scalable Encryption Algorithm

Transcription

1 Iteratioal Joural of Computer Applicatios ( ) o of Low Power Scalable Ecryptio Algorithm K.J. Jegadish Kumar Assistat Professor SSN College of Egieerig Kalavakkam Cheai, Idia S. Salivahaa Pricipal SSN College of Egieerig Kalavakkam Cheai, Idia K. Chea Kesava Reddy Pricipal Jyothismathi College of Egieerig ad Techology Shamirpet , Idia ABSTRACT SEA Scalable Ecryptio Algorithm is a block cipher based symmetric ecryptio scheme, particularly iteded for resource costraied devices. SEA proposes low computatioal cipher schemes, that is, miiaturized code size, memory ad power, developed for processors with a restricted istructio set. SEA is parametric with plai-text, key ad microprocessor size, ad foud to be powerful with the groupig of eciphermet or deciphermet ad derivatio of the keys. SEA was primarily meat for software implemetatios i microcotrollers, smart cards ad small embedded systems. I this article, we look ito the performace ivestigatio of modified SEA with efficiet modular adder i a Field programmable gate array (FPGA) device. For this reaso, a loop based iterative desig of the block cipher is realized o FPGA. Apart from its miimum cost, the proposed modified desig is etirely flexible with ay parameters ad acquires advatage of geeric VHDL codig. The efficiet modular adders implemetatio based modificatio i SEA achieves lower area, power cosumptio ad cosiderably higher throughputs o the target platform VIRTEX-4, xc4vl25 ad SPARTAN-3, xc3s1400. Keywords: Block ciphers, costraied applicatios, FPGA implemetatio. 1. INTRODUCTION Symmetric ecryptio schemes desiged for resource costraied devices have oly a limited history. Tiy Ecryptio Algorithm (TEA) is a example of cipher desiged especially for resource costraied devices. TEA is commoly kow as Yuval's proposal [1,2]. Earlier cipher does ot give efficiet resistace to differetial ad liear cryptaalysis attacks. Block ciphers i recet days, like the Rijdael Advaced Ecryptio Stadard (AES) cocetrates o decidig a trade-off i iformatio security, hardware/software complexity, ad overall efficiecy. Cosequetly, there arises a requiremet for a ew cryptosystem that edows with apt solutio for resource costraied systems. Embedded applicatios that are basic buildig structures posses importat features ad a challege for ew cryptosystem like Scalable Ecryptio Algorithm (SEA) [1,2]. 1.1 SEA: A Overview The purpose for SEA [1, 2] is to implemet i restricted resources; the architecture proposed is parametric with respect to plai-text, cipher-text, key ad the processor size. Sice the architecture is parametric i ature, it has flexibility ad ca be implemeted i all platforms with miimum code chage. Most algorithms perform differetly o differet platforms but SEA is a exceptio as it allows obtaiig a optimal method of cipherig that suits ay give microprocessor ad the security of this cipher is tailored accordig to its key size [2]. Sice it operates o a limited resource processor, it oly does some basic operatios (i.e. XOR, AND, OR, mod 2 b additio). 1.2 Literature Survey Though there are may cryptographic algorithms, most of them require high or moderate processig power, like Advaced Ecryptio Stadards (AES) [3-6], Data Ecryptio Stadard (DES) [7], Tiy Ecryptio Algorithm (TEA) [8,9], Exteded TEA (XTEA) [10]. But these ecryptio algorithms caot be implemeted i a resource costraied system due to various complexities ivolved like i.e. No Scalability, Processor Itesive, ad Security Level. AES (Rijdael) [3-6] comprises three block ciphers, all the block ciphers vary depedig o the umber of bits. AES is a predetermied block cipher havig 128 bits. It has differet key size of 128, 192 ad 256 bits. AES requires four 256 etry, 32 bit tables, so totally 4096 of memory which equals 1kilo byte for each table. AES is more processor itesive ad is o scalable, so it caot be implemeted o costraied systems. Though there are efficiet implemetatios of AES, there are still oscalable for eed of ay processig platform. DES [7] is based o symmetric key algorithms of bit size 56. DES is the classic symmetric key ecryptio algorithm that receives a predetermied legth sequece of plai-text bits ad alters through a sequece of complex tasks performed i a differet bit strig kow as cipher-text bits usig the same key. Though DES is ot a secured ecryptio, it is widely used i a mode of operatio as per Federal Iformatio Processig Stadard (FIPS-81). DES is more processor itesive, o scalable ad is breakable by Liear Cryptaalysis. TEA [8] or Yuval s proposal [9] is otable for its simplicity ad implemetable o various platforms (scalability) ad works o block size of 64 bits with a key size of 128 bit. Whe crypt aalyzed with equivalet key, each key gives three other keys. So i terms of security TEA is isecure. XTEA [10] was a advaced versio of TEA, maily aimed at improvig all the security glitches. XTEA has complex key schedulig ad rearragemet of Shift XOR ad additio operatios. XTEA is vulerable to related key differetial attack. Like SEA, HIGHT 14

2 Iteratioal Joural of Computer Applicatios ( ) [11] is also aother Block Cipher for resource costraied systems, but its o scalable ad cosumes more umber of gates ad the throughput ad operatig frequecy are much less whe compared to SEA (48, 8). So, implemetig SEA for costraied systems is a better optio. This paper is orgaized as follows. The itroductio ad literature survey are provided i sectio 1. Sectio 2 describes parameters, defiitios ad basic operatios for implemetatio of SEA. Sectio 3 illustrates hardware implemetatio strategies. I sectio 4 implemetatio results are preseted. Fially, i sectio 5 coclusios based o the results are made. 2. IMPLEMENTATION OF SEA Majority of recet private key cipher desig resulted i tradeoffs i the cost of executio ad their performaces. However, the objective is to effectively implemet o a wide rage of platforms. SEA is a differet method ad cosiders a perspective i which it has iadequate throughput ad resources. The cipher was primarily targeted as a desig to provide cost effective implemetatio ad certificatio routie for processors with a restricted istructio set [1]. I additio, opposite to block ciphers that are widely used, it cosiders the parameters such as bus sizes, key ad plai-text. Hece it ca be tailored straightly to a variety of security requiremets ad implemetatio eviromets. I cotrast, i compariso with the solutios that rus traditioal ciphers like Yuval s proposal or TEA (Tiy Ecryptio Algorithm), SEA additioally promotes a resistace to cryptaalysis [2]. Whe put ito practice, SEA was demostrated to be a proficiet aswer for microcotrollers ad related applicatios. Although, SEA is a efficiet hardware implemetatio, its performace is yet to be explored. This paper therefore proposes to ivestigate the iterest of this algorithm to be modified for area ad power i costraied applicatios. The ivestigatio begis with a exploratio of the quality of a cost effective FPGA implemetatio of SEA [1] ad our progress is to modify SEA usig efficiet modular adder i [12-14] to reduce the hardware complexities i terms of area ad power. 2.1 Algorithmic Descriptio Basic Operatios Owig to its optimality costraits, SEA,b [1,2] is based o a restricted umber of basic operatios chose for their accessibility i the give device. This ca be classified ito differet categories as give i Stadert et.al [1,2] 1. Basic XOR : Z 2 Z 2: x, y z = x y z i = x i y i, 2. S-Box: SEA,b make use of 3-bit substitutio table stated as: S T : = [0; 5; 6; 7; 4; 3; 1; 2], ad is evaluated as i followig expressios S: Z b 2 b Z b 2 b : x x = S(x) x 3i = (x 3i+2 x 3i+1 ) x 3i x 3i+1 = x 3i+2 x 3i x 3i+1 x 3i+2 = x 3i x 3i+1 x 3i+2, : bitwise AND : bitwise OR. 3. Word rotate R: For b -word vectors the word rotate is expressed as: b R: Z 2 b 4. Bit rotate r: Z b 2 b : x y = R x r: Z b 2 b Z b 2 b : x y = r x y 3i = x 3i 1 y 3i+1 = x 3i+1, y 3+2i = x 3i+2 1, where : right shifts ad : left shifts. 5. Additio modulo 2 b : : Z b 2 b Z b 2 b b : x, y z = x y Z 2 b z i = x i y i, I the followig sub-sectio, complete descriptio of the algorithm which ca be referred to [1, 2] is briefed. It starts with the vital parameters, ad the highlights its basic operatio. The the sequece of key geeratio is described Ecryptio/Decryptio ad Key Geeratio The ecrypt roud F E, decrypt roud F D ad key roud F K are defied as: Ecryptio Roud F E : L i+1, R i+1 = F E L i, R i, K i R i+1 = R L i r S R i K i, L i+1 = R i Decryptio Roud F D : L i+1, R i+1 = F D L i, R i, K i R i+1 = R 1 L i r S R i K i, L i+1 = R i 15

3 Iteratioal Joural of Computer Applicatios ( ) Figure.2.1. Ecryptio ad decryptio ad key schedulig [1, 2] Key Schedulig Roud F K : KL i+1, KR i+1 = F K KL i, KR i, C i KR i+1 = KL i R r S KR i C i, KL i+1 = KR i Cipher Descriptio This cipherig is based o the umber of rouds r ad uses iterative based loop desig. The pseudo code give i Figure 2.2 illustrates the ecessary steps for ecryptig a plai-text. where, P: Plai-text, C: Cipher-text K: Key ad all these three are parameterized by bit size. Takig ito accout the parametric b-bit words, the operatios are doe i the cipher. Sice r is odd, referrig to Figure 2.2 for key schedulig ad ecryptio, the value of r must be rouded up or dow. Roudig up or ceil is deoted as ad roudig dow or floor is deoted as. Figure 2.2: Pseudo Code descriptio [1, 2] Recommeded Number of rouds The expressio r = [3(/4) + 2((/2b )+ b/2)] evaluates the umber of rouds, r, required to sufficietly secure agaist covetioal attacks. i.e, calculatio of r is related to resist either differetial or liear attacks addig to twice the umber of rouds to get absolute diffusio. Cosecutively, it prevets statistical ad structural attacks. The value of r must be always odd, if ot, 1 must be added to make it odd [1,2]. 3. HARDWARE IMPLEMENTATION 3.1 o Descriptio The first ivestigatio step to the [1] hardware implemetatio of SEA proposes to take a look at a straightforward implemetatio of the algorithm o a FPGA platform, achievig a roud/clock cycle ad deoted as the loop implemetatio. It is kow that the S-boxes ad the mod 2 b adder are the operators that cost more i hardware implemetatio; but the operators like Word Rotate ad Bit Rotate blocks i the cipher are realized by swappig wires. As per the specificatios of SEA [1], the key geeratios cosist of two multiplexers to switch the right ad left part of the key whe the algorithm reaches half. The executio is doe by the suitable cotrol sigal called Swap. The switch cotrolled multiplexer supplies the loopig fuctio with the right part of the key durig the executio of first half of roud ad pass o its left part after the switch. The Geeric Loop Architecture is simple ad oly chages i the locatio of the R ad R -1 Block. I this paper, we maily focus to describe [12] a light weight Modular adders to modify modulo 2 b additio operator i SEA so as to achieve cosiderable low power optimizatio at the sythesizable VHDL desig level. 16

4 No: of Slices Iteratioal Joural of Computer Applicatios ( ) 3.2 o of Modified SEA with efficiet Modular adders Additio modulo m of x ad y {0,1,2,..m-1} is give by the equatio: (x + y) mod m = x + y, if x + y < m, ad = x + y m, if x + y m, (3.1) which ca be simply realized usig a suitable basic arithmetic operators. But, their implemetatio is complex, as they require more space ad speed. The algorithm described allows to liberate the implemetatio cost ad thus results i powerful hardware operators. Here, the equatio k = [log 2 m]+1 desigates the umber of bits which are essetial to predetermie output ad iputs of a modulo m adder. Fudametally a additio modulo m ca be performed by three methods [12]: 1. Table based operator method 2. Hybrid based operator method 3. Adder-Based operator method. Adder-Based Operators: Implemetig Equatio (3.1) ad illustrated by Algorithm 3.1 directs to attai architectures i Figure 3.1 ad [12] delivers i detail the proof of validatio of this method. This algorithm implemetatio resulted i use of two carry-propagate adders ad a Multiplexer ad is cosidered to be appropriate for FPGAs. Algorithm 3.1 Additio Modulo m. Determie k 2 k-1 < m < 2 k Assig s0 x + y Assig s1 (s0 mod 2 k ) + 2 k m if the carry-out bit of s0 or s1 is oe the (x + y) mod m s1 mod 2 k else (x + y) mod m s0 mod 2 k ed if The architecture of implemeted algorithm 3.1 is portrayed i Figure 3.1. proposed modulo additio algorithm leads to smallest circuits, i tur reduced overall circuit complexity of SEA. Figure IMPLEMENTATION RESULTS The results were derived by sythesizig the algorithm usig Xilix ISE 9.2i tool o VIRTEX-4 platform device XC4VLX25 with speed grade-12 ad XC3S1400, SPARTAN-3 platform with speed grade -4. XPower Aalyzer tool was used to aalyze the power cosumptio of the implemetatio. The implemetatio was doe for variats bit data () ad a processor word size (b). We achieved reductio i umber of slices (Figure 4.1), high throughputs (Figure 4.2) ad icrease i work frequecy (Figure 4.3) i implemetatio compared to implemetatio of [1]. Throughput /Area ratios are also show i Figure 4.4. implemetatio of SEA exhibited cosumptio of small area ad move toward at the cost of icreased throughput ad reduced power cosumptio as i Figure 4.5. As a result, it ca be well thought-out as the attractive substitute for costraied devices. No: of slices vs Data ,8 72,12 96,8 o o[1] Data Size, Word Size i bits Figure

5 Throughput/Area Ratio Frequecy i MHz Throughput i Mbps Total Power Cosumptio i mw Iteratioal Joural of Computer Applicatios ( ) Throughput vs Data ,8 72,12 96,8 o o [1] Power Cosumptio of our Modified SEA Data Size, Word Size i Bits Data Size, Word Size i bits Figure 4.2 Frequecy vs Data ,8 72,12 96,8 Data Size, Word Size i bits Figure 4.3 o o[1] Throughput/Area Ratio vs Data Figure CONCLUSION SEA was origially proposed for efficiet implemetatio i software. Cosiderig the eed for efficiet implemetatio i hardware, with the ew desig criteria, it was foud to have better solutios as compared to software implemetatio. Through the hardware ivestigatio of the SEA, we show that this modular symmetric algorithm, targeted for low-resources software solutios, ca iterestigly respod to costraied hardware eeds. We first demostrated that the scalability of this algorithm ca be kept i the hardware descriptio laguage(vhdl). The simple iterative loop desig achieves iterestig performace i area ad power reductio, improvise throughputs i FPGA. I additio, we aalysed the power cosumed by the SEA module for differet variats i data block ad word size. It is also sigificat to highlight a umber of merits i SEA compared to recet block ciphers, specifically its simplicity, scalability(re-implemetig SEA for a ew block size does ot ecessitate to re-write code), ad beig a spledid desig of ecryptio ad decryptio. 6. ACKNOWLEDGEMENT We are grateful to the experts who have cotributed towards developmet of our work. We ackowledge Shakar Kuha, Thirumuruga ad Pravee V for all their help durig the desig phase Data Size, Word Size i bits Figure 4.4 o o[1] 7. REFERENCES [1] F.Mace, F.X Stadert, J J Quisquater FPGA implemetatio(s) of a Scalable Ecryptio algorithm IEEE Trasactios o VLSI Systems, Vol.16, 2008, pp [2] Fracois-Xavier Stadaert, Gilles Piret, Neil Gershefeld, Jea-Jacques Quisquater SEA a Scalable Ecryptio Algorithm for Small Embedded Applicatios i Proc. CARDIS, 2006, pp [3] J. Daeme ad V. Rijme, The Desig of Rijdael. New York: Spriger-Verlag, [4] Advaced Ecryptio Stadard, FIPS PUB 197, Nov

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