Routine for 8-Bit Binary to BCD Conversion

Transcription

1 Algorithm - Fast ad Compact Usiged Biary to BCD Coversio Applicatio Note Abstract AN2338 Author: Eugee Miyushkovich, Ryshtu Adrij Associated Project: Yes Associated Part Family: CY8C24x23A, CY8C24x94, CY8C27x43 Software Versio: PSoC Desiger 5.1 Associated Applicatio Notes: AN2112, AN2113 This Applicatio Note describes a fast ad compact method to covert 8- ad 16-bit biary umbers to BCD (biarycoded decimal). This algorithm differs from similar methods i executio speed ad code size. Also discussed are fuctios to covert 8- ad 16-bit biary umbers to strig (aalogous to the stadard fuctio itoa ). Itroductio Biary to BCD coversio is used whe biary umbers must be displayed o text-based devices. Such devices iclude LCD displays, 7-digit LED idicators, priters, ad i other applicatios where iformatio must be displayed coveietly i decimal format for a huma to read. Divisio ad subtractio are the two most commo methods used for biary to BCD coversio. The first method, divisio, icludes a series of divisios of the target biary umber by 1 (see Applicatio Note AN2113, Math Programs ). The remaider holds the sigle decimal for each step. The umber of divisio operatios is equal to the umber of decimal digits i the umber. This method has several drawbacks. First, the use of the divisio is costly ad secod, the executio time rises sharply with icreasig magitude of the biary umber to be coverted. Therefore, the first method is oly optimal for 8-bit umber coversio. The essece of the secod method, subtractio, lies i serially repeated subtractio of the 1 umber from the target biary umber, where is the umber of the decimal digit (, 1, 2, 3, 4). After each subtractio a check for zero takes place. The umber of subtractio operatios is equal to the umber of digits i the resultig decimal umber. Very log executio time, eve for a 8-bit umber, is the mai drawback of the subtractio method. The maximum umber of subtractio operatios it takes to covert a 16- bit umber is 41. The worst-case umber for this operatio is A iterestig method of biary to BCD coversio is described i AN2112, Biary To BCD Coversio. It uses miimal code, which icreases slowly as the magitude of the umber icreases from 8 to 24 bits. But it has the same drawback as the methods described above, log executio time. A very fast ad compact 8- ad 16-bit biary to BCD coversio method is proposed i this Applicatio Note. It is based o the PSoC device Multiply Accumulate (MAC) ad special mathematical methods to traslate biary umbers to decimal base. This method is especially useful for 8- ad 16-bit biary umbers but loses its advatage for umbers of greater magitude. Fortuately, 8- ad 16- bit biary umbers are the most commo choice for use i embedded applicatios. November 17, 21 Documet No Rev. *A 1

2 The Algorithm A followig algorithm was used to develop our fast ad compact biary to BCD coversio method [1]. To uderstad the algorithm, we first cosider the data structure. Let s cosider a 16-bit umber. The iput is straightforward biary. The output is i upacked BCD. See Figure 1. For a 16-bit biary umber, the maximum value is So the equivalet BCD umber has 5 bytes: 6; 5; 5; 3; 5. Each byte cosists of oe decimal digit. Figure Bit Biary ad BCD Number Data Structure N15 Biary Number N, 16 Bit N max = N14 N13 N12 N11 N15 N9 N8 N7 N6 N5 N4 N3 N2 N1 N Upacked BCD Number D, 5 Digit N max = N3 D N3 D N3 D N3 D N3 D N2 N2 N2 N2 N2 N1 N1 N1 N1 N1 N N N N N...16 A 16-bit biary umber ca be broke ito 4 fields of 4 bits each. Let s call these fields 3, 2, 1,. Write the value of the umber, usig these coefficiets: = Equatio 1 Let s cosider the decimal umber d 4 d 3 d 2 d 1 d, where d 4, d 3, d 2, d 1 ad d are decimal digits. I the base 1, the value of ca be expressed as: = 1d 4 + 1d 3 + 1d 2 + 1d 1 + d Equatio 2 By combiig equatios (1) ad (2), we ca rewrite the origial equatio as: = 3 ( ) ( ) + Equatio ( ) + ( 1 1 ) If we distribute the i over the equatios for each factor, we get the followig: = 1(4 3 ) + 1( ) + +1( ) + Equatio 4 +1( ) We ca use this to arrive at first estimates a i for d 3 through d : a 3 = 4 3 a 2 = a 1 = Equatio 5 a = d i =(a i /1) mod 1 Equatio 6 The values of a i are ot proper decimal digits because they are ot properly bouded i the rage a i 9. Istead, give that each of i is bouded i the rage i 15, the a i are bouded as follows from Equatio (5): a 3 6 (4*15) a 2 3 (2*15) a (9*15 + 5*15 + 1*15) Equatio 7 a 285 (6*15 + 6*15 + 6*15 + 1*15) This is actually quite promisig because a 3 through a 1 is less tha 256 ad may therefore, be computed usig the 8 bit PSoC arithmetic logic uit (ALU), ad eve a may be computed i 8 bits if we ca use the carry-out bit of the PSoC ALU to hold the high bit. Furthermore, if our iterest is two s-complemet arithmetic where the high bit is the sig bit, the first step i the output process is to prit a mius sig ad the egate, so the costrait o 3 becomes 3 7 ad we ca coclude that: a 243 Equatio 8 As we ca see, operatios o all cosidered umbers are executed o a 8-bit basis. November 17, 21 Documet No Rev. *A 2

3 To illustrate the described algorithm, sample C code is show below: Code 1. usiged short it // - bi umber usiged char d4, d3, d2, d1, q; //d4 d - decimal umbers usiged short it a; //Fid 3 umbers d = & xf; d1 = (>>4) & xf; d2 = (>>8) & xf; d3 = (>>12) & xf; //Calculate d d4 umbers d = 6*(d3 + d2 + d1) + d; q = d / 1; d = d % 1; d1 = q + 9*d3 + 5*d2 + d1; q = d1 / 1; d1 = d1 % 1; d2 = q + 2*d2; q = d2 / 1; d2 = d2 % 1; d3 = q + 4*d3; q = d3 / 1; d3 = d3 % 1; Routie for 8-Bit Biary to BCD Coversio The stadard divisio algorithm is used for 8-bit biary to BCD coversio. It works as follows: 1. Divide the biary iput by Save the itermediate result. 3. Multiply the result by Subtract the multiplicatio result from biary iput umber. 5. Store the result i [uits]. 6. Divide the itermediate result by Store the result i [hudreds]. 8. Multiply the hudreds by Subtract the multiplicatio result from itermediate result. 1. Store the result i [tes]. See the followig example. The biary iput umber is 123. The BCD output is stored i D[]. D[2]: /1= [D1] 3. 12*1= = [D] 6. 12/1= [D2] 8. 1*1= = [D1] d4 = q; /* Prit d d4 umbers */ At first, the biary umber that is to be coverted to BCD is broke ito 4 fields of 4 bits each. These fields are placed i variables d d 3. Next, values for a a 4 are calculated accordig to Equatio (5). The remaiders from dividig the coefficiets, a a 4 by 1, are decimal umbers, which is what we eed. November 17, 21 Documet No Rev. *A 3

4 The assembly source code that coverts a 8-bit biary umber to BCD is show below. I this implemetatio, the divisio istructio is represeted by multiplicatio ad shift istructios. Code 2. Byte2BCD: ; Divide biary iput by 1 mov [D+], A;5/2 store N i D[] asr A; 4/1 A = N div 2 ad A, 7fh; 4/2 clear MSB of A mov REG[MUL_X], 67h; 8/3 mov REG[MUL_Y], A; 5/2 mov A, REG[MUL_DH]; 6/2 asr A; 4/1 A = N div 1 ; Save itermediate result mov [D+1], A;5/2 D[1] = N div 1 ; The result is multiplied by 1 mov REG[MUL_Y],A;5/2 prepare to ext mul ret; 8/1 ; Result 52/15 ; Total Byte2BCD: 123 cycles / 38 bytes This code is optimized for the PSoC ALU. It therefore is very compact ad executes quickly. A biary umber is placed ito A. After the coversio procedure, the BCD result is placed ito global variables, D D 2. The lowest digit of the decimal umber ad part of the ext digit are defied i the first part of the code. The other digits are foud i the secod part of the code. The PSoC MAC is used for both programs. This helps reduce code size ad decrease executio time. Whe it is ecessary to port to other PSoC devices that do ot support MAC, the multiplicatio that the MAC executes ca be replaced by several additio ad shift operatios. But eve i this case, the method still yields compact code ad executes quickly. Routie for 16-Bit Biary to BCD Coversio The algorithm for 16-bit biary to BCD coversio is show ahead: asl A; 4/1 A = 2*(N div 1) asl A; 4/1 A = 4*(N div 1) add A, [D+1];6/2 A = 5*(N div 1) asl A; 4/1 A = 1*(N div 1) ; Subtract multiplicatio result from biary iput umber ad store result i [uits] sub [D+], A;7/2 D[]= N mod 1 ; Result 71/24 ; Divide itermediate result by 1 mov REG[MUL_X], 1Ah; 8/3 mov A, REG[MUL_DH]; 6/2 ; Store the result i [hudreds] 1 mov [D+2], A; 5/2 D[2] = D[1] div ; The hudreds is multiplied by 1 asl A; 4/1 A = 2*D[2] asl A; 4/1 A = 4*D[2] add A, [D+2];6/2 A = 5*D[2] asl A; 4/1 A = 1 * D[2] ; Subtract multiplicatio results from itermediate result ad store result i [tes] sub [D+1], A; 7/2 D[1] = (N div 1) mod 1 November 17, 21 Documet No Rev. *A 4

5 Code 3. ;Biary value - passed i X:A [MSB:LSB] ;returs Global variables [D+4], [D+3], [D+2], [D+1] & [D+] Word2BCD: mov [D+], A; 5/2 D[] = asr A; 4/1 ad A, 78h; 4/2 A = 81 sub [D+], A; 7/2 D[] = 81 + asr A; 4/1 A = 41 asr A; 4/1 A = 21 sub [D+], A;7/2 D[] = 61 + asr A; 4/1 A = 1 mov [D+1], A;5/2 D[1] = 1 ; Result 44/14 mov A, X; 4/1 A = asr A; 4/1 ad A, 78h; 4/2 A = 83 add [D+1], A;7/2 D[1] = asr A; 4/2 A = 43 mov [D+3], A;5/2 D[3] = 43 add [D+], A;7/2 D[] = asr A; 4/2 A = 23 add [D+], A;7/2 D[] = asr A; 4/2 A = 3 add [D+1], A;7/2 D[1] = ; Result 57/2 mov A, X; 4/1 A = ad A, Fh; 4/2 A = 2 add [D+1], A;7/2 D[1] = asl A; 4/1 A = 22 add [D+], A;7/2 D[] = mov [D+2], A;5/2 D[2] = 22 asl A; 4/1 A = 42 add [D+1], A;7/2 D[1] = add [D+], A;7/2 C:D[] = mov [D+4], ;8/3 clear D[4] mov REG[MUL_X],67h;8/3 prepare to MUL mov X, -4; 4/2 set idex / loop couter jc loop; 5/2 skip correctio if C== ; Result 74/25 add [D+1], 2;9/3 D[1]+2 equ C:D[] - 2 add [D+], 56;9/3 D[] + 56 ; Result 18/6 loop: mov A, [X+D+4];6/2 copy D[i] to A rrc A; 4/1 A = D[i] div 2 mov REG[MUL_Y], A; 5/2 mov A, REG[MUL_DH]; 6/2 asr A; 4/1 A = D[i] div 1 add [X+D+5], A;8/2 D[i+1]=D[i+1]+(D[i]div1) asl A; 4/1 A = 2(D[i] div 1) sub [X+D+4], A; 8/2 D[i]= D[i] - A asl A; 4/1 A = 4(D[i] div 1) asl A; 4/1 A = 8(D[i] div 1) sub [X+D+4], A;8/2 D[i]= D[i]mod1- completed ic X; 4/1 ic idex/loop couter jz loop; 5/2 repeat 4 times ; Result 7*4 = 28/2 ret; 8/1 ; Total Word2BCD: 458(481) cycles / 82 bytes The assembly laguage source code carries out the 16-bit biary to BCD coversio i the same maer as the C source code. This source code is optimized for PSoC assembly laguage. After each M8C istructio, two umbers follow i the commet field. The first umber shows the quatity of CPU machie cycles. The other umber shows the size of the give istructio i bytes. This is useful for calculatig ad revisig executio time ad code size. First, the coefficiets a a 3 are calculated. This is doe i three virtually idetical procedures. To calculate these coefficiets, the additio ad shift operatios are used. Overru correctio is doe at the ed of these operatios. November 17, 21 Documet No Rev. *A 5

6 After the a a 3 coefficiets are calculated, the loop procedure is executed four times. The loop procedure executes the same fuctio as the followig С code: q = a2 / 1; a2 = a2 % 1; This fuctio extracts the decimal digits ad places them ito D D 4. Routie for 8- ad 16-Bit Biary to STRING Coversio Very ofte biary umber to strig coversio is eeded. For this task, the stadard C fuctio itoa is commoly used. The fuctios proposed ahead reduce executio time by a factor of 1 ad code size by a factor of 3, relative to the imagecraft library fuctio. A itoa (iteger to strig) fuctio is described ahead. For byte to strig coversio, a btoa fuctio ca be used. These two fuctios are similar, therefore, we will discuss oly oe. Code 4. ;Biary value - passed i [SP-6] [SP-5] MSB LSB ;Retur zero termiated strig was placed from [SP-3] ITOA: _ITOA: mov X, SP mov A, [X-3] ;read strig poiter mov [pt], A ; mov A, [X-5] ;read iput umberlsb mov X, [X-6] ;read iput umber MSB ; call Word2BCD ;covertig BIN to BCD mov [ct], 4 ;iitialize loop couter mov [fl], ;iitialize o-zero flag ; L: mov X, [ct] mov A, [X+D] ;read oe BCD umber add A, 48 ;covert to ASCII mvi [pt], A ;save ASCII umber to str cmp A, x3 ;compare umber with zero jz.z1 ;jump if ozero.z: mov A, [fl] ;check o-zero flag jz.z2 ;jump if ozero flag dec[pt] ;decremet strig poiter jmp.z2.z1:mov [fl], 1 ;set o-zero flag.z2:mov A, [ct] ;check loop couter jz.ex dec [ct] jmp.l ; ex: ;exit procedure mov A, [fl] jz.z3 ic [pt] ;icremet strig poiter ; ;if o-zero flag is clear.z3: mov A, ;add ul to ed of strig mvi [pt], A ret ; ; Total ITOA: 925 (95)cycles / 58+82=14bytes ; After the itoa fuctio call, the parameters are read from the stack. The parameters are placed oto the stack accordig to the #Pragma Fastcall16 rules. After that, the Word2BCD fuctio is called. This fuctio coverts iput data to BCD format. The procedure for covertig data ad writig it ito a array i ASCII format is the performed five times. This procedure igores leadig zeros ad does ot write these zeros to the array. The followig example illustrates this. If we covert the umber 123 to strig, we get the result: [][][1][2][3]. A strig cosists of [ h]. As we ca see, the zeros i the high digits are ot writte ito the strig. November 17, 21 Documet No Rev. *A 6

7 To mark the ed of the strig, a biary should be added to the last ASCII character as strig termiator. С Prototype: exter void ITOA(usiged char *, usiged it ); exter void BTOA(usiged char *, usiged char); Whe we eed to call this fuctio from the assembler, the #Pragma Fastcall16 rules should be used. ITOA Fuctio Call: PUSH X; MOV A,[wTest] ;LSB of iput value MOV A,[wTest+1] ;MSB of iput value MOV A, ;page poiter MOV A,28 ;Output strig poiter LCALL ITOA ADD SP,252 POP X The associated project is attached. This project icludes a library file ad source code for library testig. The testig cosists of comparig the fuctio result with a stadard result. The compariso occurs i the rage from to N, where the N is the maximum iput value for the give fuctio. The compariso results are set to the serial port coected to the P1[1] pi. The trasmissio format is 1152 baud, o parity, ad a 1 stop bit. Summary I this Applicatio Note a fast ad compact usiged biary to BCD coversio method has bee cosidered. O the basis of this method, iteger to strig ad byte to strig fuctios were writte ad well tested. As we ca see from Table 2 ad Table 3, they are smaller ad faster tha other fuctios. I the followig tables a compariso of the described fuctios is show. The drawback of the described method is a sharp decrease i effectiveess as umber magitude icreases beyod 16 bits. The data to estimate the complexity of the algorithm at 32- bit digit calculatios are show i Appedix 1. There is curretly o implemetatio of this fuctio. BTOA Fuctio Call: PUSH X MOV A,[bTest] ;iput value MOV A, ;page poiter MOV A,28 ;Output strig poiter LCALL BTOA ADD SP,253 POP X These fuctios were writte oly for the small memory model. The user ca easily modify the associated project for a large memory model, which is supported i the CY8C29xxx device family. November 17, 21 Documet No Rev. *A 7

8 Table 1. Code Size/Executio Time Details of Proposed Fuctio Set Fuctio Name Iput Output, (Global Variables) Code Size i Bytes Executio Time i CPU Cycles Miimum Maximum Byte2BCD A ([D+2], [D+1] & [D+]) Word2BCD MSB X, LSB A ([D+4], [D+3], [D+2], [D+1] & [D+]) BTOA usiged char usiged char * (strig) ITOA usiged it usiged char * (strig) Table 2. Compariso Betwee Described Coversio Fuctios ad Fuctios Described i AN2112 Source Fuctio Name Code Size i Bytes Executio Time i CPU Cycles Miimum Miimum Proposed Byte2BCD AN2112 bi2bcd Proposed Word2BCD AN2112 bi2bcd Table 3. Compariso Betwee Described Biary to Strig Fuctio ad Stadard C itoa Fuctio Source Fuctio Name Code Size i Bytes Executio Time i CPU Cycles Proposed ITOA C compiler Library Itoa Refereces 1. November 17, 21 Documet No Rev. *A 8

9 Appedix. 32-Bit Biary to BCD Coversio Arithmetic Numbers i decimal form: = d 1 + d 1 + d 1 + d 1 + d 1 + d 1 + d 1 + d 1 + d1 + d = = (2*1 6*1 8*1 4*1 3*1 5*1 4*1 5*1 6) (1*1 6*1 7*1 7* 1 7*1 2*1 1*1 6) (1*1 *1 4*1 8*1 5*1 7*1 6) (6*1 5*1 5*1 3*1 6) (4*1 *1 9*1 6) 2 1 2(2*1 5*1 6) (1*1 + 6) Coefficiets a a: a = a = a = a = a = a = a = a = a = Maximum value of coefficiets a a: a 31 8 a 16 7 a a a 31 4 a a a a 646 Decimal digits d d 9 : d = ( a /1) mod1 i i November 17, 21 Documet No Rev. *A 9

10 About the Authors Name: Eugee Miyushkovich Name: Ryshtu Adrij Title: Post-Graduate Studet Title: Udergraduate Studet Backgroud: Eugee eared his computer egieerig diploma i 21 from Natioal Uiversity "Lvivska Polytechika" (Lviv, Ukraie). He is furtherig his studies at this uiversity. His iterests iclude embedded systems desig ad ew techologies. Backgroud: Adrij is a 5 th -year studet pursuig a MS at Natioal Uiversity Lvivs`ka Polytechika. Cotact: miyushk@svitolie.com Cotact: ryshtu@gmail.com Documet History Documet Title: Algorithm - Fast ad Compact Usiged Biary to BCD Coversio Documet Number: Revisio ECN Orig. of Chage Submissio Date ** SSFTMP4 9/7/27 Recataloged Spec *A ANUP 1/17/21 Updated to PSoC Desiger 5.1 Descriptio of Chage I March of 27, Cypress recataloged all of its Applicatio Notes usig a ew documetatio umber ad revisio code. This ew documetatio umber ad revisio code (1-xxxxx, begiig with rev. **), located i the footer of the documet, will be used i all subsequet revisios. PSoC is a registered trademark of Cypress Semicoductor Corp. "Programmable System-o-Chip," PSoC Desiger, ad PSoC Express are trademarks of Cypress Semicoductor Corp. All other trademarks or registered trademarks refereced herei are the property of their respective owers. Cypress Semicoductor 198 Champio Court Sa Jose, CA Phoe: Fax: Cypress Semicoductor Corporatio, The iformatio cotaied herei is subject to chage without otice. Cypress Semicoductor Corporatio assumes o resposibility for the use of ay circuitry other tha circuitry embodied i a Cypress product. Nor does it covey or imply ay licese uder patet or other rights. Cypress products are ot warrated or iteded to be used for medical, life support, life savig, critical cotrol or safety applicatios, uless pursuat to a express writte agreemet with Cypress. Furthermore, Cypress does ot authorize its products for use as critical compoets i life-support systems where a malfuctio or failure may reasoably be expected to result i sigificat ijury to the user. The iclusio of Cypress products i life-support systems applicatio implies that the maufacturer assumes all risk of such use ad i doig so idemifies Cypress agaist all charges. This Source Code (software ad/or firmware) is owed by Cypress Semicoductor Corporatio (Cypress) ad is protected by ad subject to worldwide patet protectio (Uited States ad foreig), Uited States copyright laws ad iteratioal treaty provisios. Cypress hereby grats to licesee a persoal, o-exclusive, o-trasferable licese to copy, use, modify, create derivative works of, ad compile the Cypress Source Code ad derivative works for the sole purpose of creatig custom software ad or firmware i support of licesee product to be used oly i cojuctio with a Cypress itegrated circuit as specified i the applicable agreemet. Ay reproductio, modificatio, traslatio, compilatio, or represetatio of this Source Code except as specified above is prohibited without the express writte permissio of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make chages without further otice to the materials described herei. Cypress does ot assume ay liability arisig out of the applicatio or use of ay product or circuit described herei. Cypress does ot authorize its products for use as critical compoets i life-support systems where a malfuctio or failure may reasoably be expected to result i sigificat ijury to the user. The iclusio of Cypress product i a life-support systems applicatio implies that the maufacturer assumes all risk of such use ad i doig so idemifies Cypress agaist all charges. Use may be limited by ad subject to the applicable Cypress software licese agreemet. November 17, 21 Documet No Rev. *A 1