COMPENSAZIONE DEI DEAD TIMES NEGLI INVERTER DI TENSIONE. M.Zigliotto Università di Udine

Transcription

1 14/04/2004 COMPENSAZIONE DEI DEAD TIMES NEGLI INVERTER DI TENSIONE M.Zigliotto Università di Udine INTRODUCTION The vilbility of powerful nd reltively inexpensive fst digitl signl proessors (DSP) is the rel event of this lst dede in the field of eletril drives. Lrge prt of the pplied reserh is now devoted to the implementtion of full-digitl, high-relibility nd low-ost drives, to extend s muh s possible the vrible-speed drive pplition rnge. Cler exmples re submerged pumps, in whih speed ontrol yields energy svings nd performne optimistion. A generl trend is the redution of sensors tht re umbersome nd delite. Thus, effetive sensorless ontrol is still the hllenge for drive designers nd produers. Giving n insight to the different sensorless tehniques, it is quite evident how they trust on good phse voltge nd urrent mesurements to bypss the bsene of ny mehnil trnsduer. It is onvenient nd usul to ssume idel inverter nd modultion opertion suh tht desired voltges re pplied extly to the terminls of the mhine. This ssumption implies idel power swithing devies tht hve no on-stte voltge drop nd swith between the on nd off sttes instntneously. In ddition, n infinitely stiff d link voltge must be ssumed. However, it is known tht prtil power swithing devies require finite time to hnge sttes. In order to prevent short iruit developing ross the d link it is neessry to dely the turn-on of eh inverter devie to llow the omplementry devie suffiient time to regin its full bloking pbility. This dely is usully termed the swithing ded time (DT) or blnking time. The min problems rise t low speed, where inverter voltge distortion due to DT beomes relevnt. The voltge distortion inreses with swithing frequeny, introduing hrmoni omponents tht, if not ompensted, my use instbility. The DT problem n be suessfully fixed by n urte ompenstion strtegy tht llows the referene voltges to be used insted of the tul phse voltges in the ontrol lgorithm. This elimintes either dditionl voltge sensors, with relted signl filtering, nd outer voltge loops. Effetti dei ded time. Gli effetti dell'inserimento dei ded time può essere filmente ompreso osservndo l tensione prodott in un rmo dell'inverter durnte un periodo di modulzione, ome mostrto in Fig.1. per un orrente di fse positiv. T, ON = T, ON td S S td i > 0 i < 0 td Fig.1 - Effetti dei ded time t u n n d e vlgono relzioni nloghe per u b e u. T d Si può llor srivere () t u () t = U

2 Utilizzndo l notzione dei vettori spzili: 2 t u = () () = d ( ) + ( ) 3 + ( ) 3 se us t us t Ud i ib e i e Si può or lolre 3 b + e 3 + e = 2 Inftti esso è ome se fosse il vettore spzile di un inverter di tensione in tutte le sue possibili onfigurzioni, m on U d invee he U d /2. Per esempio, se 1 = 1 = 1 = b 1 1 si h 1 e 3 e 3 = 1+ + = 2. Si ottiene dunque: 2 2 u se 4 t () () () d t = us t us t = Ud ( is ) ( ) ( i ) + e ( ib ) + e ( i ) i s = ( i ) + e + e b 1 = 1 i i > 0 < 0 he può essere rppresentto grfimente ome in Fig.2: Fig.2 - Effetti dei ded-time nell tensione prodott dll'inverter. Il lolo dell distorsione è nor più omplesso se un o più orrenti di fse mbino segno ll'interno di un periodo di ommutzione. Si dimostr he in tl so vlgono le relzioni: v s () t 4 td U d s 2 3 td U = d 2 td U d s 0 s ll urrents > 0 or < 0 ny one urrent <> 0 ny two urrents <> 0 ll urrents <> 0

3 e dunque vengono prodotti tredii ulteriori vettori distorenti. Effetto dell distorsione nelle orrenti di fse. To understnd the shpe of the urrent wveform, onsidertion of the intertions of ll three phses of distortion is neessry. Assume tht the ngulr seprtion of eh line urrent is 120 degrees. Sine the distortion voltge is 180 degrees out of phse with the urrent for eh phse, then eh of the distortion wveforms is lso seprted by 120 degrees, s illustrted in Fig.1. Assuming the motor lod is liner, we n use superposition nd nlyze the system response to the distortion lone (for instne, modultion signl equls zero). Under this ondition, if we ssume tht the motor lod is blned, we n verge the three distortion voltges to obtin the motor neutrl voltge, n. Unlike 3-phse sine wves, the distortion wveforms do not result in neutrl voltge of zero over time. Insted, it is squre wve whih trnsitions every 60 degrees. For the ske of our nlysis, let s ssume tht the motor is 3-phse Y onneted lod (lthough the results pply eqully to delt onneted lods). By subtrting n from d1, we obtin the distortion voltge whih tully is impressed ross the phse 1 leg of the lod, whih is shown s the bottom wveform of Fig.1 nd in Fig.2. Fig.1 Digrmm delle orrenti e dell distorsione legt i dt. Fig.2 Effetto dei dt sull form d'ond di tensione u n This voltge sets up urrent in tht phse whih is funtion of the lod impedne. When the originl sine wve urrent is dded bk in by superposition, the result is urrent wveform whose peks re lipped, s seen in Fig. 3. In ft, under ertin onditions when the distortion wveform is lrge with respet to the modultion wveform, the distortion n tully use the urrent to dip t its peks. Fig.3 Form d'ond dell orrente di fse, no omp. dt Fig.4 - Effetti dell ommutzione bss orrente

4 Inquiring minds lso will wonder bout the mysterious flt spots of the urrent wveform t the zero rossings in Fig.3. Up to now, we hve ssumed tht the distortion wveform is perfet retngulr wve shpe, nd, therefore, hs onsistent rising nd flling edges. Relted to this premise, we lso hve implied tht the inverter output voltges re either high or low t ny given time, inluding the ded-time intervls. Fig.4 shows the voltge wveforms out of one hlf-bridge of the inverter under both high nd low urrent onditions, the ltter ourring ner the zero rossings. In these onditions, the indutor is less ggressive in snpping the voltge high or low, presumbly due to prsiti pitne in the motor nd drive whih n support the indutor s low urrent flow. Prior to the ded-time intervl, if the output voltge lredy ws driven in the diretion tht the indutor would drive it nywy bsed on the urrent polrity, this phenomenon is not observble. The problem ours when the other trnsistor ws previously on nd the indutor must drive the output voltge through the full power supply rnge during the ded-time intervl. The net effet is tht the voltge wveshpe does not trnsition instntneously when the urrent polrity hnges. Insted, softer trnsition ours whih tkes the "edge" off of the distortion wveform.the next question to ddress is how this effet uses the urrent to fltten out t the zero rossings. Let s exmine the se of positive indutor urrent whih is deresing so tht the output voltge hnges to the forth wveform of Fig.4. As stted erlier, the polrity of the distortion voltge is suh tht it opposes the polrity of the urrent. Per lti vlori di orrente positiv l tensione sul rio rimne ostntemente inferiore l vlore di riferimento fino ll'istnte del mbio di polrità, dl qule l tensione sul rio rimne ostntemente superiore l riferimento. Nel so di bssi vlori di orrente positiv deresente, l tensione sul rio non rimne ostntemente inferiore l riferimento, in qunto omini diventre meno inferiore del riferimento prim dello zero rossing, perhè il rio non riese srire prontmente le pità di usit degli IGBT. Un po' ll volt l tensione su rio diventerà superiore l riferimento, m rimrrà ostntemente superiore un po' dopo lo zero rossing, qundo l orrente si potrà di nuovo ritenere negtiv lt. Dunque si speriment un derivt (dv) di tensione positiv, whih ontributes to positive di. In other words, the dv results in negtive feedbk whih opposes the urrent deresing further. As result, the urrent mgnitude is regulted, nd the zero rossing is delyed. Wveform (5) in Fig.4 shows the ondition of the output voltge shortly fter the urrent zero rossing finlly ours. As the urrent ontinues to go more negtive, the voltge trnsitions from wveform (6) to the usul risp trnsition. The dv of the distortion (in the drker shded ded-time region) is still positive, whih ontinues to oppose the negtive trend of the urrent. As result, the urrent remins flttened until the urrent hs risen enough, t whih point the dv in the distortion is zero. Severl hrteristis bout ded-time distortion re worth mentioning: 1. The mplitude of the distortion per unit of bus voltge is equl to the rtio of the ded-time to the PWM period. Sine ded-time is system prmeter whih is usully fixed in ordne with the swithing hrteristis of the power devies, the problem is usully ssoited with higher PWM frequenies. In some ses, n engineer will speify higher PWM frequeny to minimize THD (totl hrmoni distortion) without relizing tht the distortion from ded-time tully gets worse. 2. The voltge distortion uses urrent distortion, nd the net result is torque pulstions felt on the motor shft. Severl ustomers hve reported tht, under ertin onditions, this lso trnsltes into stbility problems between the motor nd drive. 3. Unlike the modultion signl, whih is purposefully impressed upon the motor windings, the mplitude of the distortion is not ffeted by the modultion index. This mens tht the problem, when viewed from signl-to-noise vntge point, is most severe when the pplied motor voltge is smll. On n AC (lternting urrent) indution motor, this ours when the motor RPM is lso smll, nd the momentum of the rotor nnot smooth out the torque pulstions, mking them even more pprent.

5 Strtegi di ompenszione tx,1 t x, 2 tx,1 t x, 2 ntiipted by td ntiipted by td Fig.5 - Compenszione on orrente positiv Fig.6 - Compenszione on orrente negtiv With positive urrent, the lower flling edge should be ntiipted by t d. The urrent sign is smpled few ns before this possible swithing instnt. Norml PWM re bsed on mp timers, nd they nnot issue swithing edges in rel time. With negtive urrent, the upper flling edge should be ntiipted by t d. The urrent sign is smpled ustin-time to perform this ompenstion. For eh phse, urrent sign is smpled twie in period, thus ensuring orret ompenstion. Risultti sperimentli, bsti sull'utilizzo di un FPGA. 5 th db 7 th db 11 th -3.4 db Fig.7 - Spettro dell orrente di fse senz e on l ompenszione dei dt. It hs been shown n improved on-line ompenstion of the ded time effet in voltge inverter. The keyfeture is the exploittion of fst omputtion pbility of FPGA omponents. The urrent sign is smpled ust few instnts before the swith ommuttion. Experimentl tests, performed on working prototype, hve onfirmed the vlidity of the proposed strtegy over both onventionl nd prior FPGA-bsed tehnique. The proposed tehnique lso represents step towrd the retion of drive-oriented intelletul property (IP) librries, tht in the future ould stop the ontinuous nd umbersome migrtion of the bse ontrol lgorithms to the next vilble DSP/µP.