ACHIEVING accurate broadband on-wafer calibrations

Transcription

1 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 9, SEPTEMBER Broadband Space Conservative On-Wafer Network Analyzer Calibrations With More Complex Load and Thru Models Sathya Padmanabhan, Member, IEEE, Lawrence Dunleavy, Senior Member, IEEE, John E. Daniel, Member, IEEE, Alberto Rodríguez, Member, IEEE, and Peter L. Kirby, Member, IEEE Abstract An improved vector network analyzer (VNA) calibration approach is demonstrated that utilizes planar lumped shortopen-load-thru standards and achieves accuracy comparable to thru-reflect-line (TRL) at high frequency, without the commonly occurring errors in TRL at low frequency. The approach relies on complex load and thru models for coplanar waveguide and microstrip standards that are not currently available in typical VNA firmware. It is shown that the RF performance changes due to variations in fabrication of load can be addressed by calibrating or adjusting the load model with the measured dc resistance for a particular load. Good results are shown for a wide range of substrates (GaAs, alumina, and FR-4) and frequencies to 110 GHz. Index Terms Calibration, error correction, millimeter-wave measurements, scattering parameters, standards. I. INTRODUCTION ACHIEVING accurate broadband on-wafer calibrations with a minimum set of common footprint calibration standards decreases the cost of real estate on planar substrates and wafers. It also reduces calibration time. The goal of this study is to establish a methodology for characterizing custom standards with sufficient accuracy for broadband calibrations with a manageable set of standard definitions. We also sought a technique that would account for potential fabrication variability of on-wafer (or on-board) loads. Most on-wafer lumped standard calibration techniques use an ideal lossless thru-line model. More appropriate modeling of the thru line, as well as the load standard, enables the proposed method to achieve accurate calibrations from very low to high frequencies (e.g., dc to Manuscript received February 1, 2006; revised May 12, This work was supported in part under grants by Anritsu, M/A-Com Companies, and Modelithics Inc. S. Padmanabhan was with the Center for Wireless and Microwave Information Systems, Department of Electrical Engineering, University of South Florida, Tampa FL USA. She is now with Semflex Inc., Mesa, AZ USA. L. Dunleavy and A. Rodríguez are with the Center for Wireless and Microwave Information Systems, Department of Electrical Engineering, University of South Florida, Tampa, FL USA ( alrodrig@eng.usf.edu). J. E. Daniel was with the Center for Wireless and Microwave Information Systems, Department of Electrical Engineering, University of South Florida, Tampa, FL USA. He is now with the Insyte Corporation, Palm Harbor, FL USA. P. L. Kirby is with the School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA USA. Color versions of Figs. 1 and 3 27 are available online at ieee.org. Digital Object Identifier /TMTT GHz) using a minimal set of compact short-open-load-thru (SOLT) standards, including cases where the reference plane is not at the center of thru. The work described herein follows from a series of developments for on-wafer calibration improvement [1] [3]. A method for using measured lumped standard definitions in place of the more common equivalent-circuit models (msolt) was shown to be capable of transferring the accuracy of thru-reflect-line (TRL) calibration to a compact set of lumped standards. Since msolt suffers the low-frequency inaccuracies commonly associated with TRL calibrations, a broadband accurate calibration is not established. A multiline TRL calibration can extend the classical TRL band to lower frequencies, but it requires different probe-to-probe spacing with each line, and this is a major disadvantage with semiautomated calibrations. msolt, as well as the technique of this paper, solves this problem. Although the technique presented depends on TRL for the initial model parameters, it will be clear later on that the accuracy of the parameters is not affected by the low-frequency issues of TRL. A careful study of multiple microstrip and coplanar calibration standards on different substrates showed that the -parameter variations in the load standards were the most significant. This variation in RF performance was verified to be directly correlated with the dc resistance [2]. An attempt to fit existing VNA load models to broadband TRL-calibrated load measurements revealed that a more complex load model is needed to represent planar coplanar waveguide (CPW) and microstrip loads [3], [4]. This paper demonstrates a modified physical model that fits measured data well and has a resistive part directly tied to the measured dc resistance of the load. An established approach that has some of the advantages as of the proposed method is the line-reflect-match (LRM) method [5], [6]. The main drawback to the original method is that it is assumed that the -parameter measurements are referenced to the impedance of the match standard. In our study, we found that, for some load standards, their impedance are complex with a real part that varies with the standard s dc resistance. The reference planes are also established in the middle of the thru-line standard, and are often moved to the probe tips (for commercial substrate calibrations) using a lossless thru-line assumption. The line-reflect-reflect-match (LRRM) method [7] is an improvement to LRM that addresses the complex nature of the load through determination of a series inductance resistance (R L) model for the load standard. Another method also /$ IEEE

2 3584 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 9, SEPTEMBER 2006 accounts for imperfections in LRM loads [8] using a -determined TRL (typically) to first measure the complex impedance of the load and then translate the -parameters to a desired (e.g., 50 ) reference impedance. However, in some cases, as illustrated in this paper, where the load varies significantly with frequency, the technique can fail because its equation-based model cannot track the measured load. One drawback to LRM and TRL methods, in general, is that one-port calibrations cannot be directly accomplished. This paper demonstrates an alternate practically useful calibration approach, called the complex SOLT (csolt) that achieves TRL level accuracy at high frequency and avoids commonly occurring low-frequency TRL calibration issues, which have been briefly introduced in [9]. The method is implemented using LabVIEW software, allowing for differing definitions on each port when necessary. The method has been demonstrated to produce excellent results using the Anritsu Lightning 37397C and Wiltron 360B vector network analyzers (VNAs) in a number of different calibration experiments conducted on a wide range of substrates (GaAs, alumina, and FR-4) and at frequencies extending to 110 GHz. II. CSOLT METHODOLOGY The SOLT calibration method is a well-established method for VNA calibration [10]. In many situations, it has been supplanted by the generally more accurate TRL method [11], [12], however, there are situations where a SOLT calibration can be advantageous. In the current case, the interest is in producing a solution that can lead to minimizing the space occupied by on-wafer standards, while maximizing broadband (e.g., dc to over 110 GHz) calibration accuracy. The methodology used can achieve accurate broadband calibrations. Modeling of the load is accomplished by combining dc data with -corrected TRL calibrated data. The thru model is modeled by fitting a lossy propagation constant equation that accounts for attenuation as a function of frequency to a thru-line standard measured with a probe-tip referenced TRL calibration. Once the standards have been modeled, the csolt carries out subsequent SOLT calibrations. III. STANDARD MODELS AND MEASURED DATA This study emphasizes the use of improved models for the load and thru standards, while utilizing conventional models for the open and short standards. In all the cases, standard models are derived from -corrected 50- TRL measurements enabled with the National Institute of Standard s (NIST) s MultiCal software [12], [13] for each of the standards, combined with dc measurements of the loads. A. Shorts/Opens We found no improvement necessary to the conventional approach to modeling calibration opens and shorts. Hence, the measured open/short were used to fit the respective capacitance or inductance models. Fig. 1. Microphotograph of a typical GaAs microstrip load. Fig. 2. Complex load model for CPW and MS loads, which accounts for dc resistance variation. B. Loads Fig. 1 shows a typical microstrip load after fabrication. The existing load model from NIST [4] accounts for the dc resistance of the load, series inductance ( ), and the capacitance to ground ( ) (Fig. 2). However, with the results shown further here, it is seen that with an increase in frequency, the basic model cannot track the variations of the load well. Thus, the proposed load model includes elements that help the model fit the high-frequency measured loads. It includes a gap capacitance ( ) that exists between the signal line to via pad and inductance ( ) to ground through the via. When a CPW load is of interest, the via inductance is set to zero in the model. The load models are derived such that they fit high-frequency TRL data, but smoothly transition to the dc resistance at low frequencies. The model is also used to fit each of the ports separately since the dc resistances of the ports may vary independently. The fitting procedure is important because, though most of the commercial substrates are laser trimmed and well fabricated (hence, negligible variation in load impedance with frequency), there are many cases where the load is not so well behaved. It is seen in Figs. 3 and 4 that the proposed load model tracks well with the dc resistance of the load at lower frequencies and follows the high-frequency measured data through the entire frequency range when compared to the existing models. The physical significance of the model is validated by comparing the simulation-based optimized model parameters to those calculated using RF transmission-line theory. Table I gives the simulated values of the parameters used in the model for microstrip loads contained in a calibration set designed by Imparato, Tampa, FL [1] and fabricated by ITT GaAs Tek (now M/A-Com), Lowell, MA. The inductance of the load and capacitance to ground were calculated with LINPAR [17] (calculates matrix parameters for transmission lines). The parameters were calculated treating the load as a transmission line. The load inductance and capacitance to ground are found to be 48 ph and 18 ff, respectively. The gap capacitance is a low value, as

3 PADMANABHAN et al.: BROADBAND SPACE CONSERVATIVE ON-WAFER NETWORK ANALYZER CALIBRATIONS 3585 Fig. 3. Real part of load impedance of center of thru referenced GaAs microstrip load measured (R = 50:256 ) versus modeled load impedances for different models. Fig. 5. Real part of load impedance of probe tip referenced GGB CS5 CPW load (R =49:9 )measured versus modeled load impedance. Fig. 4. Imaginary part of load impedance of center of thru referenced GaAs microstrip load measured (R = 50:256 ) versus modeled load impedances for different models. Fig. 6. Imaginary part of load impedance of probe tip referenced GGB CS5 CPW load (R =49:9 )measured versus modeled load impedance. TABLE I TABULATION OF LOAD MODEL PARAMETERS AND THEIR VALUES FROM SIMULATION expected. This capacitance represents the combined coupling through the air to the pad on top of the ground via, as well as coupling through the substrate to the conical shaped via below the load (which is more significant). The same model topology fits CPW loads very well with an analogous physical motivation. In addition to the ITT GaAs microstrip load, the complex load model is further validated with CPW and microstrip loads measured on other substrates. Figs. 5 and 6 show the real and imaginary impedance of a load measured on a commercially available substrate (GGB CS5). As stated earlier, the loads are well fabricated and, hence, the impedance does not vary widely with increase in frequency. The proposed model is also verified with surface-mount resistors soldered on 14-mil FR-4 substrates with microstrip lines, as shown in Figs. 7 and 8. The significance of modeling such loads is to illustrate that broadband SOLT calibrations can be performed on printed circuit boards (PCBs) with chip resistors as loads. A point not to be overlooked is that due to TRL measurement inaccuracies at low frequencies, the model (which trends to the dc resistance) is a more correct representation of the load than the measured data, especially at low frequencies. Measurement of an ITT GaAs load was made to 110 GHz, shown in Figs. 9 and 10. The broadband measurement data in Figs. 9 and 10 was obtained by combining data taken from two separate VNAs; the Anritsu Lightning 37397C (40 MHz 65 GHz) and the Wiltron 360B ( GHz). The model parameters were obtained from the 40-MHz 65-GHz data. Expanding the frequency range to 110 GHz, the load model s performance holds with no additional tuning required. The degradation in data stability near 65 GHz is due to the two sets reaching their performance limits.

4 3586 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 9, SEPTEMBER 2006 Fig. 7. Real part of load impedance of center of thru FR-4 load (surface mount) (R = 49:75 ) measured versus modeled load impedance. Fig. 9. Real part of load impedance of center of thru referenced GaAs microstrip load measured (R = 49:9799 ) versus proposed model load impedance. Fig. 8. Imaginary part of load impedance of center of thru FR-4 load (surface mount) (R =49:75 ) measured versus modeled load impedance. C. Thru VNA calibration algorithms like SOLT or LRM mostly assume an ideal lossless transmission-line model for the thru-line standard. In reality, the thru line is lossy and the attenuation loss varies with respect to the substrate and conductor properties. Thus, it becomes necessary that the thru line be well modeled in terms of the propagation constant over the design frequency range. Even though most VNA firmware allows incorporating for loss in thru lines, it is very common for practitioners to neglect loss during calibration since it is not mandatory. In this paper, the need for an accurate thru model is emphasized and has been implemented independent of the network analyzer. The thru-line equations [14] treat the transmission line as a lossy line and, thus, compensates for the losses. It is known that the propagation constant of a transmission line is represented as Fig. 10. Imaginary part of load impedance of center of thru referenced GaAs microstrip load measured (R = 49:9799 ) versus proposed model load impedance. either not too significant or cannot be modeled directly. The attenuation constant equation was thus designed to be dependent on the aforementioned losses. The conductor loss of a transmission line is represented by the sheet resistivity of the line and is given by where is frequency (in hertz), is the permeability, and is the conductivity of the material. The dielectric loss is represented by the equation (2) where is the attenuation constant (nepers/unit length) of the transmission line. The dielectric loss of the substrate and conductor loss of the metal are the two main factors that are generally significant in a thru-line measurement. The other losses are (1) where (3) (4)

5 PADMANABHAN et al.: BROADBAND SPACE CONSERVATIVE ON-WAFER NETWORK ANALYZER CALIBRATIONS 3587 for the 8390-m delay line on the ITT GaAs mi- Fig. 11. Magnitude of S crostrip substrate. Fig. 13. Reflection coefficients of loads for the ten GaAs loads used, with varying dc resistances from 49.5 to 52.5 on the Smith chart. ITT GaAs microstrip substrate. Using (6), the equation-based data traces well with the measured -parameters of the transmission line through the frequency range concerned. IV. VARIATION WITH RF PERFORMANCE OF LOAD for the 8390-m delay line on the ITT GaAs mi- Fig. 12. Magnitude of S crostrip substrate. where is the effective dielectric constant, is the relative permittivity, is the loss tangent of the conductor, and is the speed of light in vacuum. The phase constant of the line is given by is represented by the fol- and the total attenuation constant lowing equation: (5) The above equation includes a fitting factor, which is multiplied with the total attenuation. This is because the equation uses simple approximations to estimate the losses and, hence, the total loss is underestimated. The thru equation suggested above is a good approximation for typical transmission lines and substrates. Figs. 11 and 12 show the thru equation fit with an m delay line measured, after a TRL calibration, on the (6) The fact that the dc resistance can vary between loads was verified with the availability of a whole wafer (ITT GaAs microstrip) with multiple identical dies. Fig. 13 is a plot of the reflection coefficients of ten different loads measured across the wafer after a corrected center of thru TRL calibration. It is clear from the Smith chart that the load impedances vary from die to die on the wafer. This can be attributed to fabrication issues like film resistivity and thickness tolerances. The advantage of the proposed load model when compared to existing models is its ability to track the dc resistance of the load at the lower end and at the same time follow the load behavior at higher frequencies more accurately. It also lends itself to a better physical justification than that proposed in [3]. For validation, 14 loads of varying dc resistance were measured. The measured loads are fit with the load model shown in Fig. 2, adjusting for the respective dc resistances, but making no changes to the other model parameters. Example results presented here correspond to loads with dc resistance of and Figs. 14 and 15 show the load impedances measured and matched with the compensated model. These data comparisons show the load model can track the RF performance of the load at both dc and higher frequency ranges. As a reminder, the model parameters are values obtained when optimizing for a load. It is seen that the model can fit well with 52- and

6 3588 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 9, SEPTEMBER 2006 Fig. 14. Real and imaginary parts of load impedance of measured load versus load model with adjusted R of at center of thru reference. Fig. 17. Comparison of vector error difference between the measured and model with and without compensation for varying R. Fig. 15. Real and imaginary parts of load impedance of measured load versus load model with adjusted R of 49.8 at center of thru reference. equivalent model for the load standard. For Fig. 16, the load model parameters were obtained by optimizing each of the three different load models for a single load measurement. In order to plot the vector error difference between the model and 14 measured loads, the model s component was then the only parameter that was adjusted to correspond to the measured dc resistance. It is observed from the graph that the series RL model had the maximum error because the model is basically a constant real impedance and a linear imaginary impedance with little accommodation for complex impedance variations with frequency. The NIST model is seen to present a large improvement and can model varying dc resistance, however, the vector error difference is approximately 14 at 65 GHz and the error through most of the bandwidth is approximately 8. The proposed load model has an average error of less than 4 throughout the frequency range. The importance of adjusting for is highlighted again in Fig. 17. The plot shows the vector error differences for model versus measured data for varying and nonadjusted cases. It is clear from the graph that if the load is assumed to be 50 with no variation die to die, then the error between the measured and model is much more significant. Fig. 16. Average vector magnitude error of 14 loads comparing the different load model conditions loads and are at most 1.5 different from the simulated load at the higher frequencies. The average vector error difference between the 14 measured loads and three different load models is plotted in Fig. 16 for a complete analysis. The comparison is made between the proposed complex load model, the NIST model, and series RL model that is available in the commercial VNA firmware as the V. CSOLT IMPLEMENTATION A LabVIEW program has been implemented to perform the SOLT calibration with the complex load and thru models. The calibration software can presently be used on Anritsu Lightning and Wiltron 360B VNAs. The program accounts for the small variations that can occur between ports by providing independent model options for the two ports of the calibration standards. The program also allows using measured data files for standard definitions as in the case of the msolt calibration method. The results illustrated herein are obtained from an Anristu Lightning ( GHz), as well as the Wiltron 360B ( GHz) VNA. The improvement in accuracy is verified using a calibration comparison program also implemented for the purpose of this study. The method as presented by Marks et al. in [15] compares the error coefficients of two calibrations and, thus, plots

7 PADMANABHAN et al.: BROADBAND SPACE CONSERVATIVE ON-WAFER NETWORK ANALYZER CALIBRATIONS 3589 Fig. 18. S and S of a 0.03-pF capacitor with respect to TRL and csolt calibrations referenced to center of thru on a GaAs microstrip substrate. the maximum upper error bound. The comparison provides a quick and meaningful comparison and establishes the maximum possible error between two calibrations. The program compares two one-tier calibrations directly from the network analyzer or reads from the error coefficients that are saved in a file. The significance of the implementation of this comparison method where the benchmark calibration is not TRL, as described in [16], will be presented in Section VII. VI. CALIBRATION AND DEVICE MEASUREMENTS The SOLT calibration standards on the ITT GaAs and FR-4 substrates were measured after the center of thru TRL calibration and modeled as discussed earlier. A csolt calibration was performed with the standard definitions generated with the models fit to TRL data along with the dc resistance measurements. The accuracy of the calibration is verified with -parameter measurements of devices that were available. The devices were also measured with respect to a TRL calibration for comparison purposes. A 0.03-pF capacitor was measured on the GaAs microstrip substrate with respect to csolt and TRL calibrations. Fig. 18 shows and of the measured capacitor. It is observed from the graphs that the -parameters of the two calibrations are very close. The worst case difference between the measurements with respect to the calibrations is plotted in Fig. 19. The vector difference for is less than throughout most of the frequency range, which is a relatively small difference at 65 GHz. The results from calibrating a 14-mil-thick FR-4 substrate are also illustrated in this paper to verify the broadband accuracy of csolt calibrations with surface-mount components. A 0.2-pF chip capacitor was measured with respect to csolt and TRL calibrations. It is clear from the graph in Fig. 20 that the -parameter measurements match very well with each other. The vector error difference between the two calibrations was less than 0.02 throughout the frequency range. VII. CSOLT ACCURACY VERIFICATION In Section VI, capacitors were measured with respect to csolt and TRL calibrations, and the difference in the measured -parameters was analyzed for comparison. However, Fig. 19. Vector error difference between S from TRL and csolt calibrations referenced to center of thru on a GaAs microstrip substrate. Fig. 20. S and S of 0.2-pF capacitor with respect to csolt and TRL calibrations referenced to center of thru on a 14-mil FR-4 microstrip substrate. the difference between two calibrations is best predicted with upper error bound graphs. This graph shows the worst possible measurement differences between passive components, which are calculated directly from the error coefficients. The proposed csolt is compared with TRL, msolt, and front panel SOLT calibrations performed on the same substrate. The comparison graphs presented here are generated from the LabVIEW program implemented for the study. Figs. 21 and 22 show the upper error bound between the calibrations performed on the ITT GaAs microstrip substrate. The benchmark calibrations for the two cases are TRL and csolt, respectively. The fact that the csolt method is good at lower frequencies and behaves close to the TRL at higher frequencies is highlighted when all the calibrations are compared with csolt as the reference calibration. Note in Fig. 22 that the csolt compares with SOLT at low frequencies (zoomed-in part of the graph) as desired, and has a maximum upper error bound of 0.05 at 65 GHz when compared to TRL. When the frequency range is expanded to 110 GHz, csolt retains its TRL-like performance, as shown in Fig. 23. In contrast, the low-frequency error of the TRL reference calibration in Fig. 21 causes all the calibrations to show a high upper error bound at low frequencies. The absolute value of this rise in error at low frequencies varies depending on various

8 3590 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 9, SEPTEMBER 2006 Fig. 21. Upper error bound between TRL, csolt, msolt, and SOLT calibrations with respect to TRL as reference on ITT GaAs microstrip substrate with center of thru reference. Fig. 23. Upper error bound between TRL, csolt, and SOLT calibrations with respect to TRL on ITT GaAs microstrip substrate with center of thru reference. Fig. 22. Upper error bound difference between TRL, csolt, msolt, and SOLT calibrations with respect to csolt on ITT GaAs microstrip substrate with center of thru reference. Fig. 24. Upper error bound between csolt, msolt, and SOLT with respect to TRL calibration on 14-mil FR-4 microstrip substrate. factors impacting the quality of the TRL calibration standards (skin depth of metals used, length of longest delay line, etc.). Since the msolt technique depends on the TRL measured data files for its definitions of standards, the accuracy of the calibration follows with the accuracy of TRL, which fails at the lower frequency end. The front panel SOLT calibration compared to TRL has a maximum upper bound that increases with frequency because the standards are not defined adequately. However, with the csolt method where the standards are accurately defined, the error is reduced to a great extent. csolt has minimum error at the lower frequencies when compared to the TRL and msolt calibrations and closely follows TRL at high frequency, as desired for a broadband calibration. The compatibility of the load model with surface-mount chip resistors and the increase in accuracy of csolt calibrations is illustrated with the FR-4 copper clad substrate. The same comparison as in the GaAs case is also performed with this case. Figs. 24 and 25 show that csolt is comparable to the TRL at higher frequencies (maximum upper bound of 0.02 at 18 GHz) and retains low-frequency accuracy of the SOLT. Fig. 25. Upper error bound between TRL, msolt, and SOLT with respect to csolt calibration on 14-mil FR-4 microstrip substrate. VIII. CALIBRATING OVER MULTIPLE DIE WITH CSOLT A best practice strategy for calibrating over multiple die on a whole wafer is suggested in this paper. The short, open, and complex load with thru equation models are established from one of the dies based on measured data after -corrected TRL

9 PADMANABHAN et al.: BROADBAND SPACE CONSERVATIVE ON-WAFER NETWORK ANALYZER CALIBRATIONS 3591 Fig. 26. Upper error bound difference for the csolt calibration versus TRL on multiple die from an ITT GaAs microstrip substrate using csolt as the reference calibration. Fig. 27. Upper error bound between csolt (equal-length SOLT standards) and TRL calibration referenced at probe tips on the M/A-Com GaAs microstrip substrate. calibration. It has been verified that the load standard varies the most from port to port and die to die. However, with the RF performance (load impedance) directly dependent on the of the load, a complex load model with variable dc resistance that accounts for variations in its performance has been illustrated. Thus, the calibration process can be simplified by adjusting for the value of in the load model and perform SOLT calibrations on the multiple dies available. This eliminates the need to model standards after -corrected TRL calibrations for each new die in the substrate without compromising the accuracy of the calibrations. To illustrate the proposed strategy, a csolt calibration is performed on the reference substrate whose dc resistance of the load is on port 1 and on port 2. The model parameters calculated from the reference substrate is retained for the die under test, except for the dc resistance. Another csolt is performed on a different die whose on either port are 51.8 and The calibration thus performed is compared with that of a TRL performed on the same substrate. It is also compared with the csolt versus TRL comparison data from the reference die. From Fig. 26, it is clear that the error bound shows very good agreement with the upper bound data from the reference substrate up to approximately 45 GHz. It is also observed that the difference between the two error bounds is just approximately 0.03 after 45 GHz. IX. SPACE CONSERVATIVE CSOLT The importance of the equal length (same footprint) SOLT standards is highlighted in cases where space is an issue in the fabrication of bulk wafers with active and or passive devices. In device wafers, the area allocated for calibration standards might be of concern if it is a significant number. The other advantages to the proposed methodology are that with the compact set of space conservative standards, probing is very easy and less time consuming and still highly accurate. Availability of a semiautomatic probing system ensures more repeatable measurements with the equal footprint standards. To illustrate the same, TRL and SOLT (half the thru and equal footprint) standards (dc 110 GHz) were designed on a custom calibration substrate (100- m-thick microstrip GaAs) and fabricated by M/A-Com. From the design, it was noted that the TRL standards occupied approximately 4.2 mm 9 mm, while the SOLT standards with the same footprint size occupied just approximately 1.7 mm 1.4 mm. Since the csolt calibration requires a set of TRL standards to model the SOLT standards, one reference substrate with the required TRL can be fabricated. The other die on the wafer can just have the SOLT standards. It has been illustrated that the loads measured on the other die can be modeled accurately by adjusting the dc resistance of the respective loads. It was observed that the dc load resistance variation was very well controlled for the M/A-Com standards fabricated for the study, as compared to the other GaAs substrate. The equal footprint SOLT standards were measured and modeled after a probe-tip TRL calibration. It is very important that a calibration comparison be performed with these standards, as this is instrumental in proving that the equal-footprint SOLT standards can be substituted for TRL calibration when modeled accurately. Fig. 27 shows the maximum upper bound when TRL and csolt calibrations referenced at the probe tip plane are compared with each other. The results as seen are very close to the TRL repeatability data up to approximately 45 GHz. The error rises to at 50 GHz and this is because the open and short were resonating at around 47 GHz. The resonance could be because of coupling from the adjacent standards. Nevertheless, the equal-footprint SOLT standards are validated to predict a very low upper error bound when compared to the TRL repeatability data at higher frequencies while still retaining accuracy at lower frequencies. X. CONCLUSION An improved approach to on-wafer SOLT calibrations utilizing models currently unavailable in the firmware of network analyzers has been presented. Complex load and thru models have been implemented with external calibration programs in order to account for variations with frequency due to fabrication imperfections and parasitic effects. The use of more complex models allow for a reduction in the error normally incurred in an SOLT calibration as frequency increases, achieving TRL

10 3592 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 9, SEPTEMBER 2006 accuracy, while eliminating the low-frequency problems associated with a TRL calibration. The relation between the dc resistance and RF performance of the load is utilized to demonstrate the fact that SOLT calibrations can be performed on multiple die without having to model the load variation on each individual die or pair of load standards. A significant advantage is that csolt utilizes a compact set of space-conservative calibration standards in comparison to the long delay lines needed to achieve broadband TRL. The calibration algorithm can also be used for one-port calibrations, which is not possible with TRL or LRM calibration techniques. Thus, broadband accuracy can be achieved when compared to other methods where the compromise is either at the lower or higher frequency ranges. [12] R. Marks, A multiline method of network analyzer calibration, IEEE Trans. Microw. Theory Tech., vol. 39, no. 7, pp , Jul [13] R. B. Marks and D. F. Williams, Characteristic impedance determination using propagation constant measurement, IEEE Trans. Microw. Guided Wave Lett., vol. 1, no. 6, pp , Jun [14] B. C. Wadell, Generalized transmission lines, in Transmission Line Design Handbook. Norwood, MA: Artech House, 1991, ch. 2, pp [15] R. B. Marks, J. A. Jargon, and J. R. Juroshek, Calibration comparison method for vector network analyzers, in 48th Automat. RF Technol. Group Conf. Dig., Clearwater, FL, Dec. 1996, pp [16] D. F. Williams, R. B. Marks, and A. Davidson, Comparison of on-wafer calibrations, in 38th Automat. RF Technol. Group Conf. Dig., San Diego, CA, Dec. 1991, pp [17] A. R. Djordjevic, M. B. Bazdar, T. K. Sarkar, and R. F. Harrington, LINPAR for Windows: Matrix Parameters for Multiconductor Transmission Lines. Norwood, MA: Artech House, 1995 [Online]. Available: ACKNOWLEDGMENT The authors would like to thank Dr. D. Williams, National Institute of Standards and Technology (NIST), Boulder, CO, and J. Martens, Anritsu, Morgan Hill, CA, and E. Daw (formerly with Anritsu) for helpful discussions and encouragement, Dr. J.-P. Lanteri and Dr. T. Büber, both with M/A-Com, Lowell, MA, for fabrication of custom GaAs calibration standards, J. Capwell and M. Laps, both with Modelithics Inc., Tampa, FL, for providing surface-mount FR4 calibration boards, and G. Boll, GGB Industries, Naples, FL, for providing some of the probes and commercial calibration standard substrates used. Author L. Dunleavy would also like to credit Dr. D. Metzger, a consultant, as the author of some of the software algorithms used in the early phases of this paper s research. REFERENCES [1] M. Imparato, T. Weller, and L. Dunleavy, On-wafer calibration using space-conservative (SOLT) standards, in IEEE MTT-S Int. Microw. Symp. Dig., Anaheim, CA, Jun. 1999, pp [2] P. Kirby, L. Dunleavy, and T. Weller, The effect of load variations on on-wafer lumped element based calibrations, in 54th Automa. RF Technol. Group Conf. Dig., Atlanta, GA, Dec. 1999, pp [3], Load models for CPW and microstrip SOLT standards on GaAs, in 56th Automat. RF Technol. Group Conf. Dig., Boulder, CO, Dec. 2000, pp [4] D. K. Walker, D. F. Williams, and J. M. Morgan, Planar resistors for probe station calibration, in 40th Automat. RF Technol. Group Conf. Dig., Orlando, FL, Dec. 1992, pp [5] H. J. Eul and B. Schiek, Thru-match-reflect: One result of a rigorous theory for de-embedding and network analyzer calibration, in Proc. 18th Eur. Microw. Conf., Stockholm, Sweden, Sep. 1988, pp [6] S. Lautzenhiser, A. Davidson, and K. Jones, Improve accuracy of on-wafer tests via LRM calibration, Microw. RF, vol. 29, no. 1, pp , Jan [7] A. Davidson, K. Jones, and E. Strid, LRM and LRRM calibrations with automatic determination of load inductance, in 36th Automat. RF Technol. Group Conf. Dig., Monterrey, CA, Nov. 1990, pp [8] D. F. Williams and R. B. Marks, LRM probe-tip calibrations using non-ideal standards, IEEE Trans. Microw. Theory Tech., vol. 43, no. 2, pp , Feb [9] S. Padmanabhan, P. Kirby, J. Daniel, and L. Dunleavy, Accurate broadband on-wafer SOLT calibrations with more complex load and thru models, in 61st Automat. RF Technol. Group Conf. Dig., Philadelphia, PA, Jun. 2003, pp [10] J. Fitzpatrick, Error models for system measurements, Microw. J., vol. 21, no. 5, pp , May [11] G. F. Engen and C. A. Hoer, Thru-reflect-line : An improved technique for calibrating the dual six-port automatic network analyzer, IEEE Trans. Microw. Theory Tech., vol. MTT-27, no. 12, pp , Dec Sathya Padmanabhan (M 01) received the B.E. degree in electronics and communications from the University of Madras, Madras, India, in 2001 and the M.S.E.E. degree from the University of South Florida (USF), Tampa, in From October 2001 to May 2004, she was a Research Assistant with the Center for Wireless and Microwave Information Systems, where she was involved with the improvement of the accuracy of calibration techniques over a broadband frequency range. She is currently a Microwave Engineer with Semflex Inc., Mesa, AZ. Her responsibilities include design, development, and testing of high-performance microwave and millimeter-wave connectors and cable assemblies. Lawrence Dunleavy (S 80 M 82 SM 96) received the B.S.E.E. degree from Michigan Technological University, Houghton, in 1982, and the M.S.E.E. and Ph.D. degrees from The University of Michigan at Ann Arbor, in 1984 and 1988, respectively. Along with four faculty colleagues, he established the Center for Center for Wireless and Microwave Information Systems, University of South Florida (USF), Tampa. In 2001, he cofounded Modelithics Inc., a USF spinoff company to provide a practical commercial outlet for developed modeling solutions and microwave measurement services. He has been involved in industry for E-Systems ( ) and Hughes Aircraft Company ( ), and was a Howard Hughes Doctoral Fellow ( ). In 1990, he joined the Department of Electrical Engineering, USF, where he is currently a Professor. He guides a team of graduate students in various research projects related to microwave and millimeter-wave device, circuit, and system characterization and modeling. From 1997 to 1998, he spent a sabbatical year with the Noise Metrology Laboratory, National Institute of Standards and Technology (NIST), Boulder, CO. He has authored or coauthored over 75 technical papers. Dr. Dunleavy is very active in the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) and the Automatic RF Techniques Group (ARFTG). John E. Daniel (M 00) was born in St. Petersburg, FL, in He received both the B.Sc. and M.Sc. degrees electrical engineering from the University of South Florida (USF), Tampa, in While with USF, he was a Research Assistant. He was also an RF Measurement Technician with Modelithics Inc., Tampa, FL. In December 2005, he joined the Innovative Systems and Technology Corporation (Insyte Corporation), Palm Harbor, FL, as a Lead RF Test Engineer. In March 2006, the Insyte Corporation was acquired by the Aerospace and Communications Division, ITT, and has retained the same position with ITT-ACD at the facility in Palm Harbor, FL.

11 PADMANABHAN et al.: BROADBAND SPACE CONSERVATIVE ON-WAFER NETWORK ANALYZER CALIBRATIONS 3593 Alberto Rodríguez (S 00 M 06) received the B.S. and M.S. degrees in electrical engineering from the University of South Florida (USF), Tampa, in 1997 and 2003, respectively, and is currently working toward the Ph.D. degree in electrical engineering at USF. His current research interests are in the computer-aided design (CAD) and characterization of microwave and millimeter-wave balanced and multimode circuits and devices. Peter L. Kirby (S 97 M 05) received the B.S. and M.S. degrees in electrical engineering from the University of South Florida (USF), Tampa, in 1999 and 2002, respectively, and is currently working toward the Ph.D. degree in electrical engineering at the Georgia Institute of Technology, Atlanta. His current research interests are monolithicmicrowave integrated-circuit (MMIC) design in the millimeter-wave frequency range and development of alternative terahertz waveguide structures for use in terahertz multiplier applications.