LPF1. Loop 1 VCO. Loop 2

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1 A 1.25 Gb/s Clock and Data Recovery Hard-IP : H04 1 IP 功 能 及 規 格 1.1 Functional description and architecture Functional Description This report discusses the design issues related to the clock and data recovery (CDR) architectures. A common technique to design an integrated CDR includes a phase-locked loop (PLL) modifying the frequency of the recovered clock and compensating for process and temperature variations. In this work, the CDR contains several major building blocks. (1) Phase detector: A Linear sample-and-hold circuit detects the phase difference between the recovered clock and the data. (2) Frequency detector: The digital quadricorrelator technique is adopted. At initial state, a fundamental property of the FD is to produce output signals, which generate charge or discharge currents, proportional to the frequency difference between incoming NRZ data and recovered clock. After the FD pulls in the VCO frequency to the data rate, the FD is automatically disabled itself from the loop. (3) Voltage-controlled oscillator: A local clock generator that is aligned to the incoming NRZ data. Recovered clock from VCO is used to sample the incoming NRZ data. Incoming NRZ Data Decision Making Circuit Recovery Data 2 PD LPF1 Loop 1 Recovery Clock VCO Loop 2 ED FD LPF2 Clock Data Recovery Circuit Remove FD path after frequency lock Figure 1-1 A CDR block Diagram. Figure 1-1 shows the block diagram of a proposed dual-loop controlled CDR base on a phase-locked loop (PLL). This type of CDR was first suggested by Richman [1] and modified by Belliso [2]. The function of the CDR operation is as follows. At 1

2 first state, both the FD and the PD compare the input NRZ data stream and recovery clock at the same time. Secondly, the frequency-locked loop, which is constructed from Loop 2, detects the frequency difference between the incoming NRZ data and the recovered clock. This FD pulls the VCO output frequency to the data rate. Thirdly, after the operation of frequency lock has been acquired, the digital quadricorrelator FD automatically disables itself from Loop 2. This means Loop 1 dominates the whole loop and the PD decreases the phase offset. Finally, the operation is completed and the CDR can achieve fast locking and wide pull-in range by the digital quadricorrelator FD without compromising the jitter performance of the CDR system Architecture Description Edge Detector The edge detection technique is used in Loop 2 of the CDR system. There are many ways to implement this function, such as an exclusive-or gate with a delay time t, double-edge triggered Flip-Flops, and master-slave Flip-Flops consisting of two D latches. In this design, exclusive-or gates are incorporated with a delay time t as shown in Figure 1-2(a). The point about this technique is to sense the rising and falling edges of the input NRZ data, x(t).the input data x(t) through the delay path would produce data y(t), determined by the truth table of exclusive-or gates. The timing diagram of the output data z(t) is shown in Figure 1-2(b). x(t) t y(t) z(t) x(t) y(t) z(t) (a) Figure 1-2 Edge detector (a) scheme, and(b) timing diagram. (b) Frequency Detector The digital quadricorrelator frequency detector significantly increases the acquisition range and the lock time of CDR system, compared to traditional FDs [3]. In the initial state, the CDR system is out of lock. The digital quadricorrelator FD should produce a useful output to pull the frequency of the VCO to the data rate. When the frequency lock is achieved, the digital quadricorrelator FD outputs zero. As shown in Figure 1-3, the digital quadricorrelator FD consists of six D Flip-Flops, Q1- Q6. A synchronous transition detector processes the operation of the Flip-Flops Q1 and Q2. The Flip-Flops Q3 and Q4 are to store the state corresponding to the present 2

3 transition. The Flip-Flips Q5 and Q6 store the previous state. NRZ data Iclk D Q1 Q i D Q3 Q D Q5 Q t Qclk D Q2 Q q D Q4 Q D Q6 Q Figure 1-3 A digital quadricorrelator frequency detector. We can obtain some informations of the transition from the input data and the in-phase clock (iclk) and quadrature-phase clock (qclk) of the voltage control oscillator (VCO). The input NRZ data is assumed to be a periodic signal for easier to analysis. In Figure 1-4, the timing diagram of FD shows that the input data is acquired by the VCO output, iclk and qclk, on the transition state. We define state Ⅰto be iclk=0 qclk=0, state Ⅱ to be iclk=0 qclk=1, state Ⅲ to be iclk=1 qclk=1, and state Ⅳ to be iclk=1 qclk=0. In this example, the data rate runs faster than the VCO frequency F VCO, as shown in Figure 1-4(a). Judging from above, the state changes in orderⅠ Ⅱ Ⅲ Ⅳ. On the other hand, when the data rate runs slower than the VCO frequency F VCO, as shown in Figure 1-4(b), the state changes reversely, Ⅳ Ⅲ Ⅱ Ⅰ. Data Data iclk iclk qclk qclk state Ⅰ Ⅱ Ⅲ Ⅲ Ⅳ Ⅰ Ⅱ Ⅲ Ⅲ state Ⅳ Ⅲ Ⅱ Ⅰ Ⅳ Ⅲ Ⅱ Ⅰ Ⅳ (a) (b) Figure 1-4 Timing diagram of the FD (a)f VCO < data rate, (b) F VCO > data rate. Since the state varies with the input data and the VCO output iclk and qclk, the following state will be any possible state. In order to analyze these states conveniently, we identify the three-state logic, as shown in Figure 1-5. It has three states: F VCO up, F VCO down and Don t care. When state Ⅰand state Ⅱ go to state Ⅲ or state Ⅳ, the VCO output frequency F VCO goes up. The reverse holds for state Ⅲ and state Ⅳ go to state Ⅰor stateⅡ, then the VCO output frequency F VCO goes down. Other cases are Don t care. 3

4 F VCO F VCO Ⅲ Ⅳ Ⅲ Ⅳ Ⅰ Ⅱ Others Don t Care Ⅲ Ⅳ Ⅰ Ⅱ Ⅰ Ⅱ Figure 1-5 A three-state logic of the digital quadricorrelator FD. Table 1-1 Logic table of digital quadricorrelator FD. Q3 Q5 Q4 Q6 VCO frequency 0 0 * * Don't care up up up Don't care down down down Don't care 1 1 * * Don't care We have to cope with above diagram of the three-state logic that recognizes the state and sets frequency up and down, see in Table 1-1. Table presented above gets the combinational circuit in detail. This type of FD has two major advantages. One is that the synchronous processing guarantees the FD automatically disabled when the F VCO is equal to the data rate and there is no need to turn off the FD in the lock state. It means the FD cannot influence the system on the lock state and we can achieve low jitter performance. The other, the digital quadricorrelator FD is furthering the frequency difference between input data and the VCO clock. The FD is able to detect frequency derivation over ±30 percentage of the data rate. Phase Detector Figure 1-6 illustrates the proposed sample-and-hold phase detection method for a phase tracking state [4], [5]. The operating frequency is only half of the bit rate of the NRZ data. The output drives a V/I converter and the loop filter. The V/I converter output is equivalent to a copy of high frequency clock signal on top of a slow varying 4

5 signal representing phase error. Because of the hold function of the phase detector, it is able to remember the previous phase error. It has better tolerance for missing data transitions. When the loop is not in lock and a transition occurs, the edge samples are non-zero and a monotonic function of the phase difference between sampling NRZ date edge and clock zero crossing. Consequently, to a first order approximation, the phase error is proportional to the voltage difference of the phase detector output. This function can be approximated by a linear function, when the sampling edge occurs within the clock transition interval and the loop is near its locking point. Thus, for edge samples within this interval of interest we have: V K φ (1.1) S/ H where K S/H is the gain of the phase detector. NRZ data Clock V O } V φ Figure 1-6 Proportional tracking phase detection method. As we described before in the operation of the phase detector, the transistor implementation of the differential sample-and-hold circuit is depicted in Figure 1-7. It consists of a differential pair, capacitance C1-C6, common-mode feedback (CMFB), load devices M3-M4, and four switches. The common-mode feedback (CMFB) circuit senses the output common-mode level, providing correction through M3 and M4. Both the matching and the channel-length modulation of M1-M4 in Figure 3-11 impact the residual phase error in locked condition. Thus, their lengths and the widths are relatively large to minimize these effects [6]. The differential pair M1 and M2 whose tail current and load device M3 and M4, turn off simultaneously, thereby storing the instantaneous value of V C+ and V C- on the capacitances C1-C6. M3 M4 CMFB C1 C3 C5 V O+ V O- V C+ M1 M2 V C- C2 D in+ C4 D in- C6 Figure 1-7 Sample-and-hold implementation of phase detector. 5

6 VCO The ring oscillator consists of two delay cells as shown in Figure 1-8. An NMOS input pair is used to achieve the high transconductoin-to-capacitor ( gm C ) ratio to operate in high frequency. Frequency tuning is achieved by tuning the transconduction ( gm ) of the diode-connected PMOS devices Mp2. Con Mb1 Delay#1 O1- O1+ Mp2 Mp1 Mp1 Mp2 Out- Out+ Delay#2 Mn1 Mn1 O2- O2+ (a) (b) Figure 1-8 Circuit implementation of the (a) delay cell and (b) ring oscillator. Charge Pump In general, charge pump can be implemented in a number of ways. The key issues for the implementation are input offset and nonlinearity. The input offset caused by a mismatch in precharge or discharge currents or by charge injection. Another nonliearity near the lock point can be caused by edge-rate dependencies and current source switching. A push-pull charge pump and the associated capacitor are shown in Figure 1-9 [7]. A common problem in the charge pump circuits is the phase offset resulting from the charge injecting errors induced by the parasitic capacitance of the switches and current source transistors. To mitigate this problem, the current source transistors are connected to the output node V CTL. The charge pump intermediate node charges the output voltage by the gate overdrive of the current source device. It reduces the charge sharing effect. In addition, the controlled voltage is isolated from the switching noise induce by the gate-to-drain overlap capacitance of the switching transistors. 6

7 U I P V CTL D Figure 1-9 Push-pull charge pump scheme. 1.2 Key Features and Claims A CDR circuit is one of the key components of optical transmission receivers. A common method to design an integrate clock-and-data recovery circuit involves a phase locked loop (PLL) to adjust the frequency of the recovered clock and compensate for process and temperature variations. As an application to the VCO s frequency range for this VCO is well within the process corner and has a tuning range between 1GHz and 1.5GHz. Then we claims the data-eye and clock output for a CDR successfully locked to a 1.25 Gb/s PRBS (pseudo-random-bit-stream) of length The data eye has as opening of 600 ps for a clock period of 800 ps. The measured peak-to-peak jitter for the output clock is 50 ps. The power dissipation is under 300 mw at 3.3 V supply voltage when the data rate is 1.25 Gb/s and occupies μm 2. It is suitable for high-speed CDR recovery applications. 1.3 Configuration Information and Parameters In the loop performance analysis, the FD can be neglected because it dose not affect the CDR system after the lock is acquired. The linear model of the CDR is shown in Figure 1-10, where K PD is the phase detector gain (rad/s), K VCO is the VCO gain (Hz/V), and F(s) is the transfer function of the loop filter. Phase Detector Loop Filter VCO θ i K PD F(s) K VCO s θ o R P C S C P Figure 1-10 Linear model of the CDR. Considerable insight can be obtained into the design of the CDR by first considering its open-loop response. Breaking the loop at the feedback input of the phase detector can derive this response. The output phase, θ o (s), is related to the input phase, θ i (s), 7

8 by KVCO θ o ( s) = θi ( s) K PD F( s). (1.1) s The open-loop response, H(s), then given by θ o ( s) KVCO H ( s) = = K PD F( s). (1.2) θ ( s) s i When the loop filter in Figure 1-10 is used, Eq. (1.1) and Eq. (1.2) becomes H ( s) = K PD C s K + C VCO p 1+ s R C p R Cs C s 1+ s Cs + C p = K s s + ω z 1 + s ω p 2 p (1.3) where K = K PD K VCO K f is the loop bandwidth of the CDR We can see the phase of H(s) is 180 at ω=0, and the zero, ω z, and the pole, ω p1, introduce the phase shift of +90 and -90, respectively. The phase margin will be a function as follows 1 K 1 K PM = tan tan. (1.4) ω z ω p 1 Another way to approximate is ignored the shunt capacitor C s. Because C p >>C s, the zero, ω z = 1 R C p can be re-written as Cs + C p, is much small than the pole, ω p1= R Cs C p. Hence, the Eq. (1.3) 1 where F(s)= R + s C p K 1 s R C PD K + VCO p H ( s) =. 2 C s. For the CDR to be stable, the following condition should hold: p (1.5) 1 R C p K PD C p K VCO (1.6) Recall above example in which loop performance analysis. The design of the CDR includes establishing the loop parameters for that lead to desirable control dynamics. The loop parameters are often set by the application. In the design CDR, the jitter peaking must be considerably low. For given close-loop bandwidth, the damping factor of ξ>1 is required to provide low jitter peaking of less the 0.1dB [8] [9]. The value of the loop parameters must somehow be mapped into acceptable value 8

9 for the device parameters R, C s, C p, K PD, K VCO. In our case, the capacitor C p is implemented on chip, which is desirable to minimize jitter, its size are constrained about 100 pf. The problem of selecting device parameter is made more difficult by number of constraining factor. In the first place, loop bandwidth and damping factor both depend on all of the parameters. In the second place, the maximum value for C p and the minimum current for charge pump current. Furthermore and the most important, all worst case of the parameters due to process and temperature variation must lead to acceptable loop performance. A design flow of the CDR can be used as follows: (1) Determine K VCO : the VCO gain can be found from simulation results, experimental results or data sheets when a commercial VCO is used. (2) Determine K PD : the phase detector gain can be found from simulation results. (3) Determine ξ: the system designed to be over-damping to avoid the jitter peaking effect. Set damping factor ξ>1 is required to provide low jitter peaking. Cp (4) Determine C ratio: the ratio of the C p to C s, defines the maximum possible phase margin. s (5) Determine K: the loop bandwidth is then determined depending on the demand noise and transient characteristic. (6) With K, K VCO, and K VCO determined, R can be calculated. 1.4 Comprehensive Technical Specifications and Data Sheet Theoretically, the PD s gain and loop filter are defined simultaneously. While the 2 nd -order loop filter is chosen, the component values are calculated with the loop bandwidth, which is 3 MHz, a phase margin of The final employed CDR parameters are listed in Table 2-1. Table 1-2 Performance Summary. Loop BW 3MHz PD Gain 127mv/rad VCO Central Frequency 1.25GHz CDR spec. Conversion Gain 150MHz/V Frequency Range 1GHz~1.5GHz Phase Margin 67.4 Loop Filter fp=15mhz fz=0.6mhz Cs=6.3pf Cp=150pf Rp=1.74KΩ Power Supply 3.3V Power Consumption <300mW@1.25GHz Chip Size <1.5mm*1.5mm Technology TSMC 0.35um 1P4M CMOS 9

10 Figure 1-11(a) shows the pin assignments and Figure 1-11(b) shows the pin configuration diagram for the CDR circuit. The chip of the CDR is bounded on the PC board directly. PIN NAME I/O DESCRIPTION 1 T_VCO_I OUT VCO test key I-phase clock 2 T_VCO_Q OUT VCO test key Q-phase clock 3 T_BIAS_CLK * VCO test key bias voltage in source follow 4 T_VCO_VDDI * VCO test key analog power 5 T_VCO_IN * VCO test key control voltage 6 VSS_A * Analog VSS 7 VDD_D * Digital VDD 8 ON_CHIP * Switch loop filter on-chip OFF_CHIP * Switch loop filter off-chip RESET * Reset STAGE6 * Switch delay stage of edge 16 detection VSS_D * Digital VSS BIAS_PD * Bias voltage in PD BIAS_VI * Bias voltage in VI VDD_A * Analog VDD BIAS_CMFB * Bias voltage in CMFB NRZB IN NRZ data input 18 NRZ IN NRZB data input 19 R_CLK OUT Retime clock output 20 R_DATA OUT Retime data output 21 BIAS_R_CLK * Bias voltage in source follow 22 VDD_D * Digital VDD 23 BIAS_R_DATA * Bias voltage in source follow 24 ICTRL * Charge pump current control 25 CP OUT Capacitor of loop filter 26 VCO_VDDI * VCO power Figure 1-11 (a) (a) Pin assignments and (b) pin configuration diagram (b) 1.5 Uniqueness or Differentiation of this Design This is a first attempt by the author and has much room for improvement. After 10

11 testing the circuit, a few fundamental understandings and handful of details have been realized. These realizations may improve the future design. However, no matter what the applications are, how to design high-speed CDR up to Gb/s range remains a challenging yet promising task. We presented a 1.25 Gb/s CDR circuit designed in a 0.35μm CMOS technology. The circuit utilizes a dual-loop topology for both frequency acquisition as well as phase locking. The frequency detector can be extended for a large frequency range. 2 IP 設 計 驗 證 及 測 試 環 境 2.1 Provided design models Timing specifications and performance In this section, we will discuss about the several design models and how to build the total system by these blocks. In general, the task of the CDR architectures is to recovery the phase-and-frequency information from the input by extracting the clock from the transitions in the data stream. We can see the optimal sample point is about midway between the possible data transition times, as shown in Figure 2-1. Beside, this technique offers good loop stability and bandwidth, but most suffer from a systematic phase offset and they require a sampling clock frequency equal to the high serial data rate [10]. Sampling transition by the same mechanism as for the symbol centers reduces the systematic phase offset in data recovery. This technique was used in our case. Data eye Timing margin Sample clock Figure 2-1 Data recovery using phase-tracking PLL Installation Scripts In this section, we will describe the installation of a CDR circuit that employs some circuits to support a high performance, low cost, short design time and testable design. The methodology should conform an input data rate of 1.25 Gb/s. When the circuit architecture design is completed, the realization of such a high-integrated chip requires a consequent top-down design approach to ensure the first time functionality and an acceptable total design time. Figure 2-2 shows the typical top-down design flow chart. To achieve this, a fully integrated design environment with well define 11

12 interfaces is needed which enable the use of advanced design tools at each level of the design. In the first step of the design, the paper survey to build up architecture and the behavior simulation to verify our idea are right or wrong. In the next step of design, we selected an appropriate technology base on the optimal balance between the design complexity measured with die size, power consumption and the technology availability and maturity. Most blocks of the proposed CDR circuit can be designed with a HSPICE tool generating a gate level simulation result. Due to the excellent performance and reliable function of the proposed CDR, the post-layout simulation, which uses the extracted netlist and addition parasitic resistance and capacitance, must be simulated. Design Entry Architecture Design Behavior Simulation Gate Level Design Hspice Simulation Post-Layout simulation Yes Satisfactory Result Optimization Yes Satisfactory Result No No Type out Measurement Setup Report Figure 2-2 A CDR design flow chart Behavior Model PD NRZ Data R FD C s C p VCO Figure 2-3 The loop filter transfer function for behavior simulation. Because of the tremendous amount of gate counts in a clock and data recovery system, closed-loop simulation with HSPICE will take many times. Therefore, some prior architecture simulations must be done with Simulink in order to have a well-defined closed-loop behavior. Besides, in order to observe the transient response when power-up and loop switching occurs. First, we can see the loop filter in the dual loop system implemented as shown in Figure 2-3. The transfer function behind the phase detector output will be a function as follows: 12

13 P () s = D s R C + 1 p 2 s R Cp Cs + s Cs + Cp ( ). (2.7) and the transfer function behind the frequency detector output will be a function as follows: F () D s = 1 ( ) 2 s R Cp Cs + s Cs + Cp. (2.8) Consider the transfer function quoted above, the complete CDR can implement in Simulink [11] as shown in Figure 2-5. The discrete-time characteristic and some other effects such as pull-in process of a charge-pump PLL can be observed through this model. The input NRZ data signal and charge pump block are composed of the logic gates provided by Simulink, which are shown in Figure 2-4. With the input NRZ data being a time-domain signal, the FD constitutes of six DFFs and one combination gate, and the outputs U and D are summed with opposite polarity in the charge pump. A simple adder in the charge pump is used to perform the summing and gives outputs of "+1", "-1" and "0" which correspond to pump current flowing into the filter, pump current flowing out of the filter, and no net pump current flowing through the filter, respectively. The pump output current is then filtered by the loop filter transfer function, F D (s). On the other side, the PD constitutes of two sample-and-hold block, and the outputs voltage difference is summed. Then the output through the gain of the phase detector converts to the loop filter transfer function, P D (s). The VCO input control voltage V ctrl is first multiplied by 2πK vco, and then a free-running frequency 2πf free that denotes the VCO output frequency when V ctrl =0 is added. In the feedback path, the VCO output frequency f out is used a integrator to transfer the frequency signal into phase signal since frequency is the derivative of phase. Finally, a sine and cosin function generates in-phase clock (iclk) and quadrature-phase clock (qclk) and a limiter are then used to transfer the phase signal into a square wave in time domain and then feed back into the FD and PD. Using this model, the loop parameter can be varied and their effect on the CDR transient characteristic can be evaluated rapidly, saving a lot of time in HSPICE simulation. Further, the appropriate noise sources can also be introduced in the model to see their effect on output phase noise. 13

14 (a) (b) Figure 2-4 A simple Simulink model for the (a) input NRZ data, and (b) charge pump in Figure 2-5. Figure 2-5 A Simulink model for CDR architecture simulation. Here we take a CDR simulated with the described Simulink model file as an example. Since the OC-24 (optical carrier) specifications is with nominal frequency 1.25GHz. We simulate with a VCO gain 150 MHz/V, free-running frequency of 1.2 GHz and 1.3GHz, respectively. The gain of phase detector, K PD =23 mv/rad. With Cp fixed loop bandwidth while keeping ratio constant gives the results. With ξ>1, C s Figure 2-6(a), and (b) correspond to the free-running frequency of 1.25 GHz and 1.3 GHz. We can found that the frequency tracking behavior. The frequency detector outputs Up and Down signal when system unlock. While system lock, we can see that no output signal of FD as a long time. The results of lock behavior were the same to what we had expected. Figure 2-6(c) shows the data regeneration form the complete CDR system. In fact, simulation on HSPICE exhibits the same pull-in phenomenon, which verifies the advantage of this model file. 14

15 Output freq. Output freq. Up Up Down Down (a) (b) Input Data Retime Clock Output Data (c) Figure 2-6 Illustration of the fixed K and ξ on transient behavior results, (a)f free =1.2 GHz, (b) f free = 1.3 GHz, and (c) data regeneration Hspice Simulation Result The CDR system is simulated in HSPICE using TSMC 0.35μm model provided by TSMC. The CDR dual loop successfully locks to random NRZ data. The data pattern has a maximum run-length of 15. The control voltage for the VCO and the frequency detector (FD) outputs, Up and Down, show the locking behavior, as shown in Figure 2-7. The top graph shows the frequency-training loop can bring the frequency close enough for the CDR loop to lock within 5us. It shows that the loop can capture and lock very fast. Zoom in lock state, the control voltage ripple is about 10 mv. Figure 2-8 shows the retime NRZ data with the maximum run-length of 15 and retime clock at 1.25 GHz. It shows that the loop can tolerate a slight frequency offset, which is much larger than the frequency variation between the VCO output and 15

16 input NRZ data, and can lock onto the noisy random data stream. Control Voltage FD Output: Down FD Output: Up Figure 2-7 CDR locking behavior. Input Data Retime Data Retime Clock 15 bits are Figure 2-8 Retime data and Retime clock. 2.2 Verification strategy Introduction In this section, we present the testing environment, including the instruments and component circuit on the print circuit board (PCB). Following the experimental test results for the CDR described in Chapter 2 and 3 and fabricated in a standard 0.35μm CMOS technology are presented Test Setup When the circuit design is done, the next work is to make it real by drawing the layout. This section of the design is as important as the circuit design for the ensuring the operation of the CDR system. Chip on PCB is chosen for its simplicity and for its ability to bring the traces as close to the chip as possible. This chip uses a total of 26 pads and the number of high-speed inputs and outputs are about 4. Figure 2-9 depicts the test setup used to assess the performance of the experimental CDR described in this work. A high-speed pulse pattern generator, as shown in Figure 2-10(a), provides the input to the chip. The supply voltages for both analog and digital portions of the chip are generated by regulator circuit and 9 V batteries. In order to prevent the digital noise coupling to analog circuit, analog ground and digital ground are isolated to each 16

17 other. The retime clock and retime clock are fed to the communication signal analyzer, CSA 8000, as shown in Figure 2-10(b). The details of the various components of the test system are described below Input Source The input signal of the CDR is generated by a high-speed NRZ data pulse pattern generator, which can provide random data. The output is connected to the SMA (Surface Mount Adaptor) then fed into the signal line of the PC board. The measured waveform of the differential output is shown in Figure The output voltage, NRZ and NRZB, are differential and maximum amplitude is 2 V peak to peak. When input data at 1.25Gb/s, the jitter for is 25 ps (peak to peak). Communication Signal Analyzer CSA 8000 Pulse Pattern Generator MP 1652A R_Clk R_NRZ NRZ NRZB V DD,D Digital Power V DD Regulator 9V 9V Battery 9V Battery Analog Power Regulator 9V V DD V DD,A Analog Ground Digital Ground Figure 2-9 Experimental test setup Power Supply and Ground Since the CDR system is a mixed-mode system, we often partition the ground-reference net on the PC board for a CDR circuit isolated analog and digital region. Hence, the digital and analog ground planes on the top and bottom plane of the PC board is separated and connected by a bead inductor. This inductor can short the DC voltage of the analog and digital grounds, and prevent the high-frequency noise in the digital circuit coupling to the analog circuit by their grounds. (b) (a) Figure 2-10 The photographs of the (a) pulse pattern generator MP 1652A and (b) communication signal analyzer CSA

18 Figure 2-11 Measured input NRZ data eye for at 1.25Gb/s. The analog and digital powers are generated by LM 317 adjustable regulators as shown in Figure 2-12 [12]. The input of the regulator circuit is connected to a 9 V battery instead of a general power supply. Because of the noise of general power, supply is much larger than the battery. The regulator circuit is easy to use and require only predicted by the Equation 3.1 [13]: V out R 2 = + ADJ R1 I R. (3.1) 2 where the I ADJ is the DC current that flows out of the adjustment terminal ADJ of the regulator. The capacitor C 1 can be added to improve transient response at the output. The outputs of the regulators are bypassed on the PC board with the parallel combination capacitors then connected to the chip. The bypassed filter network is combined by 10μF, 1μF, 0.1μF, and 0.01μF capacitors as shown in Figure Thus, the capacitor arrangement in Figure 2-13 provides decoupling of both low-frequency noise with large amplitude and high-frequency noise with small amplitude [14]. LM 317 V in V in ADJ V out V out C 1 =0.1 uf R 1 =240 C 2 =1 uf R 2 =2 K Figure 2-12 LM 317 regulator. V in V out L 1 =100 u C 1 =10 u C 2 =1 u C 3 =0.1 u C 4 =0.01 u Figure 2-13 Bypass filter at regulator output. 18

19 Print Circuit Board Layout Measurement was performed with raw die mounted on the PC board to prevent the parasitic effect of the package, which is illustrated in Figure2-14(a), and the testing PCB was shown in Figure 2-14(b). The discrete components such as the loop filter, the bias resistor of charge pump and the PD, the DIPswitches and the input, NRZ and NRZB, are mounted with an equal distance from the die. A large amount of inductance attached to supply line, high-speed input and output lines reduces the circuit s ability to reject noise and the ability to bring in the undistorted input signal. Beside, high-frequency signal traces are made as short as possible and the length of differential signal traces are made close to each other reduce the parasitic clock skew. High-speed output lines can easily couple the large output swing onto the sensitive i Bond wire Bond wire Raw Die PCB NRZ NRZB R_Clk R_NRZ (a) Figure 2-14 Off-chip bonding wire test, and (b) the testing PCB in CDR. (b) Die Photo The die micrograph of the experimental CDR circuit is shown in Figure The clock data recovery is implemented in the 0.35μm TSMC one-poly quadruple-metal CMOS process and the chip active area is 1.49 mm 1.5 mm. The power supply voltage is 3.3 V. Separate digital and analog ground plane were used to the inductor (i.e., bead). CDR VCO Test Key Capacitor Array Cp Cs Figure 2-15 Die micrograph of the CDR. 19

20 2.3 Experimental Results In this section, we will discuss the experimental results of the CDR. There are two kinds of results. The first important parameter to test is the VCO s free running frequency and tuning range. The free running frequency for this VCO is well within the process corner and has a tuning range between 1080 MHz and 1430 Mhz. We will compare the simulation results with the experiment, as shown in table 4-1. The measurement result is slower than the post-layout result. Table 2-1 Comparison between simulation results and experimental Pre_sim without load results. Pre_sim with load post_sim with load Measurement Result f max 1800MHz 1480MHz 1490MHz 1430MHz f min 950MHz 1050MHz 1140MHz 1080MHz f range 850MHz 430MHz 350MHz 350MHz Kvco 360MHz/V 180MHz/V 145MHz/V 145MHz/V Figure 2-16 shows the post-simulation corners and measurement result difference. The measurement result is close to the typical corner and the slow corner. The process seems to be a little bit slower than the typical condition. Figure 2-17 shows the retimed data-eye and retimed clock for a CDR locked to a 1.25Gb/s PRBS (pseudo-random-bit-stream) of length The data eye has the opening width of 633 ps for a clock period of 800 ps. The top graph is the retimed data eye at 1.25Gb/s which DC offset is 550 mv and peak to peak amplitude is 400 mv. The bottom graph is the retimed clock at 1.25 GHz which DC offset is 370 mv and the peak-to-peak amplitude is 250 mv. VCO Output Frequency 1.65E E E E E E E E E E E E E E Control Voltage Experimental Result Sim_TT_25 Sim_FF_0 Sim_SS_80 Figure 2-16 Compare post-simulation corners with measurement result. 20

21 Retime Data 400 mv 550 mv Retime 250 mv 370 mv Figure 2-17 Retime data eye at 1.25 Gb/s and retime clock at 1.25GHz. (a) (b) Figure 2-18 (c) (d) Measured data-eye open versus different PRBS length (a) 2 7-1, (b) , (c) , (d) We also measured different lengths of PRBS which including 2 7-1, , and Figure 2-18 shows the different lengths versus the data-eyes. Figure 2-19(a) shows that data-eye open width versus different PRBS lengths of 2 7-1, , and Figure 2-19(b) shows that data-eye open height versus different PRBS lengths of 2 7-1, , and The measured output retimed clock jitter for different PRBS lengths of 2 7-1, , and is shown in Figure For example, the rms and peak-to-peak jitter for the retimed clock is ps and ps, respectively, 21

22 in the case of PRBS length of 2 7-1, as shown in Figure 2-20(a). Figure 2-21 illustrates the retimed clock jitter for different PRBS lengths of 2 7-1, , and Data Eye Width (ps) Data Eye Height (mv) Figure n -1 (a) Measured data-eye open (a) width, (b) height versus different PRBS length 2 7-1, , and n -1 (b) (a) (b) (c) (d) Figure 2-20 Measured jitter versus different PRBS length (a) 2 7-1, (b) , (c) , (d)

23 100 Pk-Pk rms Jitter (ps) n -1 Figure 2-21 Jitter performance for different PRBS length 2 7-1, , and Figure 2-22 shows the waveforms of the retimed NRZ data and the retimed output clock. In this experiment, a period NRZ pattern is set at 1.25 Gb/s. At the receiver side, the retimed clock locks at falling edge of the retimed data. The rms and peak-to-peak jitters for the retime clock are ps and 13 ps, respectively Retime Clock Retime NRZ Data Figure 2-22 Retime data and retime clock waveform at 1.25 Gb/s. 23

24 Figure 2-23 Jitter performance for period NRZ data. Table 2-2 summarizes the measured performance of the clock-and-data recovery circuit. We presented a 1.25 Gb/s clock-and-data recovery circuit designed in a 0.35μm CMOS technology. The circuit utilizes a dual-loop topology for both frequency acquisition as well as phase locking. The frequency detector can be extended for a large frequency range. Process Table 2-2 Performance summary Performance Summary Supply 3.3V Power VCO Range Data rate 1P4M0.35um CMOS 258mW 1.08~1.43 GHz 1.25Gbps BER for PRBS <10-10 Jitter for PRBS Jitter for PRBS Area 3 IP 應 用 方 法 及 實 例 ps, rms ps, Pk-Pk ps, rms 91.2 ps, Pk-Pk 1.5mmx1.5mm 3.1 Application Method In fact, the clock and data recovery (CDR) has become so important in electronics over the past 10 years. The optical-fiber communication systems have been used mainly for high-speed, high-density, long-distance communications. The advantages of optical-fiber transmission in the local systems are now being explored 24

25 in applications, such as Local Area and Wide Area Network (LAN, WAN) systems for multimedia, Fiber To The Home (FTTH) [15], and the board-to-board interconnections is exchange systems and computers [16]. To maintain the clock signal during a consecutive data stream, a conventional nonlinear clock recovery circuit needs a high-q filter. However, the high-q filter is difficult to integrate monolithic ally with other electrical circuits. Therefore, a common method to realize an integrated CDR circuit involves a phase locked loop (PLL) to adjust the frequency of the recovered clock and compensate for process and temperature variations. 3.2 Application Example Figure 3-1 shows a common fiber-optic data communication system consisting of a transmitter and a receiver [17]. At the transmitter side, a line multiplexer that manages several signals and interleaves them into a high-speed output. The output stream is sent to a laser driver and turned into an optical signal through a laser diode. The optical signal travels through a fiber to the receiver side. At the receiver side, it comprises of a photo diode (photo detector), a transimpedance amplifier (TIA), a clock-and-data recovery (CDR) circuit, and a demultiplexer to separate out the channels. The received light is transformed to an electric current by the photo detector. The photo detector outputs a weak current, which is amplified and converted into voltage through a transimpedance amplifier. This amplifier is a low-noise high-bandwidth transimpedance amplifier that converts the current into a voltage with a swing large enough for the proceeding block. One of the important blocks is the CDR block in the receiver end. This block recovered the timing information that is lost at the input to the fiber cable. This means that if the clock signal is used to retime the data, the sampling occurs at the optimum point, improving the bit error rate (BER) of the receiver. Finally, the retimed data is used to demultiplexer the signal into several low-speed outputs. Transmitter MUX Laser Driver Receiver TIA Clock/Data Recovery DEMUX Clock Generator Laser-diode Photo-diode Figure 3-1 Block Diagram for a common Fiber-Optic Transceiver. Reference: 25

26 [1] D. Richman, Color-carrier reference phase synchronization accuracy in NTSC color television, Proc. IRE, vol. 42, pp , Jan [2] J. A. Belliso, A new phase-locked timing recovery method for digital regenerators, IEEE Int. Conf. Rec., vol. 1, pp , June [3] C. G. Yoon, J. S. Lee, C. W. Lee, Digital Logic Implementation of Wide-Range Frequency Linear Detector, IEICE Trans. Commun., vol. E82 B, no. 1, Jan [4] H. Wang, R. Nottenburg, A 1Gb/s CMOS Clock and Data Recovery Circuit, IEEE International Solid-State Circuits Conference, WA, 20.5, [5] S. B. Anand and B. Razavi, A 2.5-Gb/s Clock Recovery Circuit for NRZ Data in 0.4-µm CMOS Technology, IEEE Custom IC Conference, pp , 2000 [6] N. Ishihara, Y. Akazawa, A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit Using the Sample-and-Hold Technique, IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp , Dec [7] P. Larsson, A MHz CMOS Clock Recovery PLL with Low-Vdd Capability, IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp , Dec [8] K. Kishine, N. Ishihara, K. I. Takiguchi, H. Ichino, A 2.5-Gb/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LAN s and WAN s, IEEE Journal of Solid-State Circuits, vol. 34, no. 6, June [9] K. Kishine, K. Ishii, H. Ichino, Loop-Parameter Optimization of a PLL for a Low-Jitter 2.5-Gb/s One-Chip Optical Receiver IC With 1:8 DEMUX, IEEE Journal of Solid-State Circuits, vol. 37, no. 1, Jan [10] C. Hogge, A self correcting clock recovery circuit, IEEE Journal of Lightwave techniques, pp , Dec [11] J. M. Hsu, Design and Application of CMOS PLL/DLL, MS Thesis, Dpt. of Electrical Engineering, National Taiwan University, June [12] National Semiconductor, LM117/LM317A/LM317 3-Terminal Adjustable Regular Data Sheet, National Semiconductor, Inc., [13] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Kluwer Academic Publishers, [14] A. Chnadrakasan, W. J. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, [15] N. Miki and K. Okada, Access flexibility with passive double star system, IEEE 5 th Conf. Opt./Hybrid Access Network Proc., [16] K. Yukimatsu and Y. Shimazu, Optical interconnections in switching system, IEICE Trans. Electron., vol. E77-C, no. 1, pp. 2-8, Jan [17] J. Savoj, A 10-Gb/s CMOS Clock and Data Recovery Circuit, Ph.D. Thesis, 26

27 University of California, Los Angeles,