Evaluation of Architectural Alternatives to Reduce Power Consumption in a Network-on-Chip

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1 Evaluation of Architectural Alternatives to Reduce Power Consumption in a Network-on-Chip Jaison Valmor Bruch, Cesar Albenes Zeferino University of Vale do Itajaí UNIVALI Laboratory of Embedded and istributed Systems LES Itajaí, Brazil {jaison, zeferino}@univali.br 4 : ma address if desired Abstract This work aimed at improving energy efficiency of a Network-on-Chip by applying and evaluating techniques to reduce the dynamic power dissipated by the network. Clock gating and data encoding techniques were applied in experiments based on SystemC simulation and synthesis in FPGA. Results confirmed the effectiveness of these techniques in reducing the switching activity, and identified limitations of the FPGA technology for the implementation of the evaluated techniques. Keywords-Power consumption; Network-on-Chip; FPGA. I. INTROUCTION Power consumption is one of the most critical issues in the design of digital systems, and the growing market for portable products and the inefficiency of the batteries exacerbate this issue [1]. Therefore, energy efficiency should be considered at each stage of the development process [2]. The power dissipation is also among the main causes for the shift from a single core paradigm to the multicore paradigm, in which the addition of cores to the chip, instead of increasing the operating frequency, allows an increasing in performance [2]. A multicore system, also known as SoC (System-on-Chip), comprises a computer system fully integrated into a single chip. Future SoCs will integrate from dozens to hundreds of cores and will present critical requirements for communication, including scalable performance and parallelism in communication. Bus-based architectures, commonly used in SoCs with few cores, will not meet these requirements. The Network-on-Chip (NoC) approach was proposed as an alternative to shared busses. These networks use point-to-point connections and present advantageous features regarding parallelism, operating frequency, power consumption, scalability and reusability [3]. The Laboratory of Embedded and istributed Systems of the University of Vale do Itajaí has a project in the area of NoCs called SoCIN (System-on-Chip Interconnection Network). This project aims at exploring NoC architectures with low silicon costs for the implementation of scalable embedded systems with high demand for communication. In systems using NoCs, the power consumption due to the mechanisms necessary for its implementation and the flow of information between the cores cannot be trivial. Therefore, it is necessary to use techniques that allow improve the energy efficiency. The network used in SoCIN Project was not originally designed considering these requirements. Aiming at improving its energy efficiency, this study applied techniques to reduce the power consumption in this NoC, so by reducing the dynamic power dissipation. We applied the techniques of clock gating and data encoding in experiments based on SystemC simulation and synthesis in FPGA. Simulation results confirmed the effectiveness of these techniques in reducing the switching activity, but the techniques applied to reduce the power dissipation resulted in silicon overhead and degradation of the maximum operating frequency. This paper is organized in five sections, including this one. Section II presents the types of power consumption inherent in CMOS technology and some techniques used to reduce this consumption. Following, Section III discusses some works that address the issue of power consumption in Networks-on-Chip. Section IV describes SoCIN, reference to this work, and discusses the implementation and evaluation of techniques for reducing power dissipation. Section V presents the final conclusions. II. REUCING POWERCONSUMPTION IN CMOS CIRCUITS Power consumption affects a large number of critical design decisions, such as cooling requirements, size of supply lines, supply capacity and the number of integrated circuits on a single chip [4]. According to [5], there are three main sources of power dissipation in CMOS circuits: ynamic power: when the device is switching, it dissipates dynamic power. The main source of dissipation is the switching activity due to charging and discharging of capacitances [6]; Static power: even when the device has no switching activity, leakage currents in CMOS circuits dissipate static power [2]; Short-circuit currents: it occurs in CMOS circuits due to the switching activity when both n-channel and p- channel conduct electricity for a short period. This results in a short-circuit, which is due to a pulse of current from V to GN [7]. Several techniques are applied to reduce the power dissipation in CMOS circuits. Among the most widely used, we highlight clock gating, data encoding, voltage and frequency adjustment, and power gating. We used the first two techniques and describe then in the next paragraphs.

2 The clock gating technique consists in disable the clock signal in circuits when the operation performed by these is irrelevant to the current state of the system. This shutdown causes a decrease in dynamic power dissipation by reducing the switching activity [6]. The data transfer lines account for a significant amount of the total energy consumed by a chip. One of the factors that cause this consumption is the transition of signals on the wires, which depends on the characteristics of the transferred data. The reduction in the number of transitions is obtained with data encoding technique [2]. Some of the existing encoding techniques include: Bus-Invert [8], T-Bus-Invert [9]; SILENT [1] and Gray [11]. III. RELATE WORKS This section presents some works that address the reduction of power consumption in Networks-on-Chip with the use of some of the techniques aforementioned. In [12], the Authors applied the clock gating technique to the internal components of a router and to the entire router. In the first case, the buffers are driven by the clock signal only when it is necessary to store a new data value and the arbiter is only updated when the last valid request is delivered. In the second case, when the router is idle, it is decoupled from the clock tree. The uniform traffic pattern and stream flows were applied in the experiments. The reductions in power dissipation were 72% and 58%, respectively. In [13], the Authors applied the following techniques for data encoding in a NoC: adaptive [14], Bus Invert, Gray and Transition [15] coding. The experiments were based on traffic patterns of real applications (HTML, WAV, MP3 and JPG) and demonstrated that the effectiveness of the encoding schemes is highly dependent on the traffic pattern applied to the network. In this work, we applied the techniques of clock gating (applied in [12]) and of Bus-Invert data encoding (applied in [13]) to SoCIN, as discussed in the next session. IV. REUCING POWER CONSUMPTION IN SOCIN A. SoCIN architecture SoCIN is a customizable Network-on-Chip based on a parameterizable router that can be configured in order to meet performance and costs requirements of a target application. The following features can be customized: channel width, buffers depth and the techniques used for switching, routing, arbitration and flow control. SoCIN uses a 2- mesh topology in which each router has a communication port named Local, at which can be attached a single core or a subsystem. Besides this port, there are from two to four communication ports for connection with the neighbor routers. Each communication link is composed of two point-to-point simplex channels composed of wires for data, packet framing and link flow control [16]. The communication ports are composed of two communication channels: Input Channel and Output Channel, and each one includes one parameterizable FIFO buffer (the FIFO at the output channels is optional). In this work, we applied the techniques of clock gating and Bus-Invert data encoding in order to reduce the dynamic power dissipated by the transference of data through wires and the storage of data at the FIFOs. B. Applying clock gating to the FIFO buffers Clock gating (CG) was applied to the circuitry of the FIFOs. These elements consist of flip-flop-based registers that store the flits blocked in the router. Buffers are synchronous circuits. Their registers are updated at each clock cycle, even if there is no writing operation. Therefore, each register adds a capacitive load to the clock tree and causes power consumption. The clock gating mechanism was applied to the buffer registers in order to avoid unnecessary loading and discharging of capacitances. This approach allows enabling the clock signal only for the register that stores a new value in a writing operation. The circuit shown in Figure 1 was the first one used in this work. Ena CLK C GCLK Figure 1. Clock gating circuit. According to [17], the circuit shown above is the clock gating solution traditionally implemented in ASIC (Application-Specific Integrated Circuit) technologies. In this circuit, the gated clock signal (GCLK) is derived from an AN operation between the enable signal (Ena) and the clock signal (CLK). The latch shown in Figure 1 is necessary to avoid the appearance of glitches at the output of the AN gate. 1) Evaluation of switching activity reduction In order to evaluate the effectiveness of the clock gating solution in reducing the switching activity at the FIFOs of SoCIN, experiments were performed starting from two different buffers implemented in SystemC. The first model includes the buffer modeled with registers that can calculate the switching activity of the clock signal, but with no clock gating. In the second type of buffer, the clock gating solution (Figure 1) was implemented in the registers of the FIFO. The experiments consisted in injecting a stream composed of 5 1-flit packets in a FIFO buffer of 8 34-bit positions in each buffer aforementioned. Table I shows the values obtained in the experiments. Compared to the original buffer, the clock gating technique allows obtaining a reduction of 87.57% in the switching activity. TABLE I. SWITCHING ACTIVITY IN FIFO BUFFERS Original buffer Buffer with gated clock Variation 8,32 transitions 998 transitions % 2) Synthesis in FPGA The evaluation of the use of clock gating in SoCIN was also done in silicon, and based on FPGA synthesis. The clock gating solution was described in VHL and synthesized to the Altera Cyclone II EP2C35672C6 device by using Altera uartus II (version 9.1, service pack 2). We obtained the

3 following metrics: (i) the silicon costs (expressed as the number of Lock-Up Tables LUTs and flip-flops FFs); (ii) the dynamic power dissipation (in mw); and (iii) the maximum operating frequency (in MHz). The experiments were performed in a single router with FIFO buffers at each input channel, each FIFO with 8 positions of 34 bits. The dynamic power consumption was obtained with a simulation of the NoC working at 1 MHz for a simulated time of 1 microseconds (1 us). Two traffic scenarios were used. In the first one, a zero-load traffic (with no data) was applied to the router with the purpose of identifying the power dissipated by the clock switching. In the second one, a flow composed of 5 1-flit packets was injected at the Local port in the direction of the East port. It was used an injection rate of 5% of the channel bandwidth and the data switching activity was of 1% (by toggling all the bits of adjacent flits in the packet payload). The network parameters were set to: wormhole switching, XY routing, round-robin arbitration and credit-based flow control. The clock gating (CG) solution depicted in Figure 1 presented a reduction in power dissipation. However, due to clock skew effect in the FPGA, data integrity was lost, as it was observed by simulation. Table II presents the results obtained in the experiments. For the zero-load scenario, the reduction in the dynamic power dissipation was of 24.53%. For the second scenario, the reduction was of 14.8%. Furthermore, there was a decrease in the operating frequency in 22.81% and an overhead of 5.24% in LUTs when comparing with the original implementation (with no clock gating). TABLE II. RESULTS FOR ASIC CLOCK GATING Silicon costs Fmax Pdin 1 MHz LUTs FFs (MHz) Scenario 1 Scenario 2 Original 1,59 1, ASIC CG 1,588 1, Variation (%) According to [17], the clock gating approach recommended for FPGA devices is implemented with a method different from the one typically adopted with ASIC technologies. A feedback multiplexer is used to emulate the functionality of a gated clock. As Figure 2 shows, the enable signal (Ena) controls the selector of a multiplexer. If Ena equals, is feedbacked to the. If Ena equals 1, the input of the flip-flop receives the current value of the input of the circuit. Ena CLK 1 Figure 2. Clock gating in FPGA (as recommended by [17]). We applied this model of clock gating in the buffers and obtained a reduction of 14.17% in the power dissipation for the first scenario (zero-loaded), but an increasing of 8.21% in the second scenario. The silicon overhead and the reduction in performance were minimal. Besides the increase in power dissipation in the second scenario, this technique also corrupted the data injected into the router and, therefore, it did not solve the problem found in the first clock gating implementation. Table III presents the values obtained in the experiments. TABLE III. RESULTS FOR FPGA CLOCK GATING Silicon costs Fmax Pdin 1 MHz LUTs FFs (MHz) Scenario 1 Scenario 2 Original 1,59 1, FPGA CG 1,51 1, Variation (%) The traditional clock gating circuits discussed so far were inefficient when synthesized to the target FPGA, increasing power dissipation or loosing the data integrity. Then, we applied an alternative circuit derived from the traditional approach used in ASIC technology, as it is shown in Figure 3. It follows the basic idea of clock gating: the register is synchronized by the clock signal only when Ena equals 1 and CLK equals. Ena CLK GCLK Figure 3. Alternative approach for clock gating in FPGA The previous clock gating techniques store the flits that compose the data packet during the rising edge of the clock signal. The alternative clock gating circuit inverts the clock signal that reaches the router, and, therefore, the flits are written to the buffer in the falling edge of the clock. This solves the problem of clock skew because all the data bits are already stable as the time of writing in the buffer. In the other implementations, different propagation delays of data signals and clock signals resulted in the lost of synchronization and data integrity. This approach showed a reduction of power dissipation in the two scenarios: 3.5% for Scenario 1 and 16.72% for Scenario 2, with a minimal silicon overhead (less than 1%). However, there was a considerable reduction in the maximum operating frequency, from MHz to 92.4 MHz. Table IV summarizes these values. TABLE IV. RESULTS FOR THE ALTERNATIVE CLOCK GATING Silicon costs Fmax Pdin 1 MHz LUTs FFs (MHz) Scenario 1 Scenario 2 Original 1,59 1, Alternative CG 1,519 1, Variation (%) Figure 4 shows a comparison of both implementations of clock gating for the two scenarios. It shows the efficiency of the alternative technique compared to other classical solutions to reduce the dynamic power dissipation. In contrast, Figure 5 illustrates the maximum operating frequency obtained with

4 each approach. The implementation that saves more energy power is the one that more degrades the operating frequency. Although this could be considered a drawback, it allows reaching better energy efficiency for systems that can operate at lower clock frequency. Furthermore, the network is parameterizable and offers other resources to meet the performance requirements of a target application, like different alternatives for switching, routing, flow control and arbitration. ynamic Power (mw) 4, 3,5 3, 2,5 2, 1,5 1,,5, Scenario 1 Scenario 2 Original ASIC CG FPGA CG Alternative CG Figure 4. Comparison between the clock gating implementations Maximum Operating Frequency (MHz) Original ASIC CG FPGA CG Alternative CG Figure 5. Performance comparison between the clock gating alternatives C. Applying data encoding to the NoC links In order to implement data encoding in SoCIN, we selected the Bus-Invert technique due to its simplicity. This technique is based on the inversion of the bits of a data to be transferred through a channel when there is a variation greater than 5% between their bits and bits of the last data transferred, thereby to reduce the switching activity along the channel. Typically, an additional wire is used to indicate when an inverted data is being transferred. When this bit is '1', it is because the bits that comprise the data transferred through the channel had to have their values inverted again by the receiver do recover its original value. To determine when data is to undergo the inversion operation, it is calculated the number of different bits (Hamming distance) between the current data in the channel and the next one to be sent. If Hamming distance is greater than half of data channel width, all the data bits must be inverted. The NoC used in this work uses a pair of bits for packet framing (the frame field). Originally, only three of the four combinations of the framing bits were defined (the first three rows of Table V). In order to avoid the addition of an extra wire to the data channel, the fourth combination of the framing bits ( 11 ) was chosen to signal when the inversion is applied to the payload flits. None inversion can be done to the header flit because it carries the routing information, and it would be necessary to add a decoder to each router port (what would be too expensive). Also, the trailer flit cannot be inverted because there is no way to signal when it is inverted without the addition of another bit to the channel. Frame field TABLE V. FRAMING COES Meaning Payload flit (Packet body) 1 Header flit (Packet head) 1 Trailer flit (Packet tail) 11 Inverted payload flit (packet body) 1) Evaluation of switching activity The evaluation of the effectiveness of the Bus-Invert technique in reducing the switching activity due to transference and storage of packets was performed with the implementation of SystemC RTL models of a FIFO buffer, a data encoder and a data decoder. The experiments were based on two SystemC simulation models. The first model included only the FIFO, which was implemented with registers able to measure the switching activity of data that they store. The second system includes the encoder and the decoder as it is shown in Figure 6. Encoder din wr wok FIFO dout rok rd ecoder Figure 6. Buffer FIFO with encoder and decoder The switching activity evaluation was performed with the injection of flit packets (each flit was 34-bit wide). Two traffic patterns were used. In the first one (Scenario 1), switching activity equals 1% of the bits between the header and the first payload flit and between each pair of adjacent flits of the payload. In the second traffic pattern (Scenario 2), switching equals 5% of the data bits plus 1 bit. The aim of this approach is to identify the reduction in switching activity for the best case (1%) and the minimal reduction (5% + 1 bit). Table VI shows the results obtained in each experiment. One can see that, in Scenario 1, the reduction in switching activity is 9.91% when employed the Bus-Invert encoding technique. For Scenario 2, the reduction in switching activity is 1.53%. Therefore, the experiment points to an improvement in the switching activity in order to reduce dynamic power dissipated by the buffers. However, the results do not consider the impact of the circuits necessary for encoding and decoding processes. This issue was evaluated with the synthesis in FPGA, described in the next sub-section.

5 TABLE VI. System Without Bus-Invert With Bus-Invert REUCTION OF THE FIFOS SWITCHING ACTIVITY Scenario 1 (1% of switching) Scenario 2 (5% + 1 bit of switching) 421,336 transitions 242,584 transitions 38,296 transitions 217,48 transitions Variation -9.91% -1.53% 2) Synthesis in FPGA The evaluation of the use of the Bus-Invert technique in SoCIN was performed with the implementation of VHL models of the encoder and decoder, and the integration of them in a system also composed of a mesh (Figure 7) with 34-bit channels (32 bits for data and 2 bits for packet framing) and 8-flit FIFOs operating at 1 MHz. The models were synthesized to the Altera Cyclone II EP2C35672C6 device under two levels of optimization to reduce power dissipation: off (with no optimization) and extra-effort (the synthesis tool applies the maximum effort in the optimization process, but can cause degradation in operating frequency). The obtained metrics were: (i) the silicon costs, (ii) the maximum operating frequency; and (iii) the dynamic power dissipation. ecoder W Encoder N N N N S S S S Figure 7. A 4 1 NoC with Bus-Invert encoder and decoder The silicon overhead of using the encoder and the decoder (in comparison with a system composed only of the NoC 4 1) was of 5% in LUTs and 1% in flip-flops. The maximum operating frequency suffered a degradation of 34.7 (%) when none power optimization was done by uartus II. With extraeffort, the reduction in operating frequency was of 41.9 (%). The evaluation experiments to obtain the power dissipation were based on the simulation of the the sending of a single packet containing 1Kbytes of data from 3 (the rightmost router in Figure 7) destined to the (the leftmost router in the figure), varying the amount of switching bits between successive flits: from only 1 bit (3.1%) to 32 bits (1%). The power evaluation of Bus-Invert technique was performed for the following configurations: 1. NoC 4 1: injection of a packet in a system including only the NoC (with no encoder or decoder). This allowed us to determine the power dissipated by the transference of packets without the influence of coding technique; 2. NoC 4 1 (Manual encoding): injection of a packet manually encoded in the NoC-only system. With this, we identified the effect of the encoding in power dissipation without the extra costs caused by the encoding and decoding process; E 3. NoC Encoder: injection of a non-encoded packet in a system composed of the NoC and the encoder in order to identify the power dissipation added by the encoder; and 4. NoC Encoder + ecoder: injection of a nonencoded packet in the system of Figure 7 to measure the total cost of implementing the Bus-Invert technique. Figure 8 shows the results of the experiments performed to evaluate the Bus-Invert coding technique without the use of automatic power optimization carried out by the synthesis tool. Pdin (nw) NoC 4x1 NoC 4x1 + Encoder Switching bits NoC 4x1 (Manual encoding) NoC 4x1 + Encoder + ecoder Figure 8. ynamic power without automatic power optimization Curve NoC 4 1 indicates the power dissipated by the network when the injected packet is not encoded or decoded. As one can see, the power dissipation increases linearly with the number of switching bits. Curve NoC 4 1 (Manual encoding) indicates the dynamic power dissipation when the coding technique is employed. In this case, data injected in the network is already encoded. One can see, the reduction in power dissipation when there are more than 17 switching bits. This occurs because each flit is composed of 34 bits, and 5% + 1 bit equal 18 bits. In the configurations in which the encoder and the decoder were added to the NoC (configurations 3 and 4), there is an increasing in power dissipation due to these components. However, when the encoder starts the process of inversion of bits (with 18 switching bits), the increasing in the dynamic power dissipation is even more significant. This power overhead is due to the encoding and decoding processes, but it was expected at least some power reduction. This did not occur due to the placement done by the synthesis tool when performing the technological mapping to the FPGA with no power optimization. By applying extra-effort for power optimization, we obtained better results, which are shown in Figure 9. However, the reduction of the dynamic power consumption in the fourth configuration (the complete system) occurs just when there are more than 26 switching bits. When applying the coding mechanisms, the power dissipation is lower than the one of the original structure when the encoder begins the process of inversion. With 17 switching bits, the power dissipation

6 increases, and a power reduction occurs just with 28 switching bits. REFERENCES Pdin (mw) NoC 4x1 NoC 4x1 (Manual encoding) NoC 4x1 + Encoder NoC 4x1 + Encoder + ecoder Switching bits [1] J. M. Rabaey and M. Pedram (Eds.), Low Power esign Methodologies. Norwell, MA: Kluwer, 1996, pp [2] S. Kaxiras and M. Martonosi, Computer Architecture Techniques for Power-Efficiency. Morgan and Claypool, 28. [3] C. A. Zeferino, Redes-em-Chip: arquiteturas e modelos para avaliação de área e desempenho, Ph Thesis, UFRGS, Brazil, 23. (in portuguese) [4] J. M. Rabaey, igital Integrated Circuits. Englewood Cliffs, NJ: Prentice-Hall, [5] A.P. Chandrakasan and R. Brodersen, Minimizing power consumption in digital CMOS circuits, Proceedings of the IEEE, 83(4): , Apr [6] M. Keating,. Flynn, R. Aitken, A. Gibbons, K. Shi, Low Power Methodology Manual, Springer 27. Figure 9. ynamic power with automatic power optimization V. CONCLUSIONS Based on the studies performed in this work, it was possible to identify several techniques for reducing power consumption in CMOS circuits that can be applied in a Network-on-Chip. Among these techniques, we had chosen to implement clock gating and data encoding based on the Bus-Invert approach. The experiments performed in SystemC confirmed the effectiveness of the chosen techniques in reducing the switching activity. However, the synthesis of these techniques in FPGA did not produce the expected results. The clock gating solutions described in the literature reduced the dynamic power dissipation. However, they presented problems related to the loss of data integrity. Then, we applied a solution that ensured data integrity and reduced the dynamic power dissipation at minimal silicon overhead. However, it reduced the maximum operating frequency. When applying data encoding, the Bus-Invert encoder and decoder were not effective in reducing the dynamic power dissipation, and, in many cases, leaded to increase the power dissipation. Although the silicon overhead was minimal, they resulted in an expressive reduction of the maximum operating frequency. As a final conclusion, we can state that the evaluated techniques are effective for reducing the switching activity, but the use of FPGA technology to obtain the silicon results did not allow a definitive evaluation of these techniques. Because of this, as future works, we intend to use ASIC technologies in order to overcome the constraints of FPGA technology. ACKNOWLEGMENTS This research was funded by UNIVALI (University of Vale do Itajaí), INCT NAMITEC (National Institute for Science and Technology on Micro and Nanoelectronic Systems) and CNPq Brazilian funding agency (grant number /28-4). [7] J.P. Colinge and C. A. Colinge, Physics of Semiconductor evices Boston, MA: Kluwer, 22. [8] M. R. Stan and W. P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on VLSI Systems, Vol. 3, no. 1, pp , [9] J. C. S. Palma, Reduzindo o consumo de potência em redes intra-chip através de esquemas de codificação de dados, Ph Thesis, UFRGS, Brazil, 27. (in portuguese) [1] K. Lee et al., SILENT: Serialized Low-Energy Transmission Coding for On-Chip Interconnection Networks, In: Proceedings of IEEE International Conference on Computer Aided esign, Nov. 24, pp [11] C. L. Su, C. Y. Tsui, and A. M. espain, Low power architecture design and compilation techniques for high-performance processors, In: Proceedings of IEEE COMPCON, Feb [12] R. Mullins, Minimising dynamic power consumption in on-chip networks, In: Proceedings of International Symposium on System-on- Chip, Tampere, Finland, Nov. 26. [13] J. Palma, L. Indrusiak, F.G. Moraes, A. Garcia Ortiz, M. Glesner, R. Reis, Inserting ata Encoding Techniques into NoC-Based Systems In: Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Mar. 27. pp [14] L. Benini, A. Macii, E. Macii, M. Poncino, and R. Scarsi, Architectures and synthesis algorithm for power efficient bus interfaces, IEEE Transactions on Computer-Aided esign Integrated Circuits Systems, Vol. 19, no. 9, pp , Sep. 2. [15] P. Ramos and A. Oliveira. Low Overhead Encodings for Reduced Activity in ata and Address Buses, In: Proceedings of IEEE International Symposium on Signals, Circuits and Systems, July pp [16] C. A. Zeferino et al., Avaliação de esempenho de Rede-em-Chip Modelada em SystemC In: Proceedings of the 27rd Congress of Brazilian Computer Society - WPerformance, 27. pp (in portuguese) [17] Y. Zhang, J. Roivainen, and A. Mämmelä, Clock-gating in FPGAs: A novel and comparative evaluation, In: Proceedings of the 9th EUROMICRO Conference on igital System esign: Architectures, Methods and Tools, 26. pp