Introduction to Exploration and Optimization of Multiprocessor Embedded Architectures based on Networks On-Chip

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1 Introduction to Exploration and Optimization of Multiprocessor Embedded Architectures based on Networks On-Chip Cristina SILVANO Politecnico di Milano, Milano (Italy)

2 Talk Outline Introduction Recent research at Politecnico di Milano: PIRATE Network-on-Chip (NoC) Architecture and Framework GRAPES Multiprocessor System-on-Chip (MPSoC) Exploration and Optimization Framework MPSoC Architecture Optimizations Conclusions and Future Works C. SILVANO Politecnico di Milano 2

3 Introduction and Motivation Multiprocessor System-on-Chip (MPSoC) platforms represent the dominating trend for embedded portable multimedia applications. To meet the communication requirements of large MPSoCs, the Network-on-Chip (NoC) paradigm is emerging as design methodology Increasing interest in NoC modeling and simulation frameworks to speed up power/performance exploration and to support flexible architecture specification C. SILVANO Politecnico di Milano 3

4 On-chip Buses Scalability limitation of shared-bus solutions IP1 IP2 IP3 IP4 SHARED BUS IP5 IP6 IP7 IP8 Other bus topologies IP1 IP2 IP3 IP4 Clustering and Bridging MultiLayer/MultiBus C. SILVANO Politecnico di Milano 4

5 Network-on-Chip: Basic Idea To derive from traditional large-scale multiprocessors and wide-area networks an on-chip micro-network on which packet-based communication occurs through routers (switches) and multi-hop routing paths. router C. SILVANO Politecnico di Milano 5

6 Network-on-Chip NoC definition: A flexible and scalable packetbased on-chip micro-network designed according to a layered methodology. NoC architecure: Characterized by higher scalability and bandwidth with respect to previous on-chip interconnections NoC methodology: To design and to explore communication-centric MPSoC platforms NoC approach compatible with IP core design for reuse philosophy. Does NoC represent evolution or revolution? C. SILVANO Politecnico di Milano 6

7 Why NoC Approach? Modularity and scalability High bandwidth Communication concurrency and resources sharing Energy efficiency Reliable Interconnect Quality-of-Service Support C. SILVANO Politecnico di Milano 7

8 Previous Works Several Network-on-Chip architectures have been recently proposed in literature: SPIN (A. Greiner - LIP) CLICHÉ (Royal Institute of Technology, Stockholm) STNoC (STMicroelectronics) ÆTHEREAL (Philips) MANGO (DTU) Xpipes (University of Bologna) Butterfly Fat Tree (University of British Columbia) Some commercial solutions: Arteris (Tool NoCexplorer and NoCcompiler based on Danube NOC IP Library) Sonics (Tool Smart Interconnect e Sonics Studio based on SonicsMX Micronetwork) C. SILVANO Politecnico di Milano 8

9 PIRATE NoC Politecnico di Milano PIRATE is a highly configurable Network-on- Chip architecture Composed of configurable interconnection components Topology-independent infrastructure PIRATE design and simulation framework for fast exploration of the interconnection design space SystemC TLM simulation models generator Synthesizable RTL models generator Energy estimation framework C. SILVANO Politecnico di Milano 9

10 PIRATE NoC Architecture NoC composed of parameterizable network components (routers, network interfaces, etc.) connected by arbitrary network topology (ring, mesh, octagon, etc.) IP1 IP2 IP3 IP4 NI NI NI NI Input Queues ROUTER Crossbar Output Queues NoC NI NI NI NI IP5 IP6 IP7 IP8 Router Controller C. SILVANO Politecnico di Milano 10

11 NoC Topology Selection Regular topologies Suitable for interconnecting homogeneous cores in MPSoCs Irregular (Custom) topologies Suitable for heterogeneous MPSoCs characterized by critical communication bottlenecks and non-uniform IPblock sizes C. SILVANO Politecnico di Milano 11

12 Examples of NoC Regular Topologies Ring Mesh Torus Router Resource Cube Fat Tree C. SILVANO Politecnico di Milano 12

13 Examples of NoC Regular Topologies Cube 4 5 STM Octagon Diameter (max # of hops between 2 nodes) = 2 STM Spidergon for N=16 nodes Diameter = 4 Regular and Symmetric Topologies Fixed Degree (# of link per node) = 3 C. SILVANO Politecnico di Milano 13

14 Spidergon Layout Spidergon layout for N = 16 Nodes Logical scheme far from physical floorplanning Bisection = 4 C. SILVANO Politecnico di Milano 14

15 Example of NoC Custom Topologies C. SILVANO Politecnico di Milano 15

16 Network Interface NI Kernel is resourceindependent and it depends on network protocol NI Shell is resourcedependent C. SILVANO Politecnico di Milano 16

17 Network Interface: Main Tasks Communication protocol conversion (from resource protocol to network protocol and viceversa) To hide details on network protocol to IP cores (so they can be developed independently of the communication infrastructure) Data packetization: packet assembly, delivery and disassembly Packet TAIL PAYLOAD HEADER C. SILVANO Politecnico di Milano 17

18 PIRATE NoC Router Input Queues Output Queues LC LC from NI to NI Input Ports from R. LC LC Crossbar Switch LC LC to R. Output Ports LC LC from L VCC Routing & Arbitration VCC to L C. SILVANO Politecnico di Milano 18

19 PIRATE NoC Router 3-stage pipeline architecture: INPUT, CROSSBAR, OUTPUT Router parameterizable in terms of: Number of I/O ports Number of virtual channels for each physical link Length of I/O buffer queues Datapath size Link Controller: To synchronize the flow on the physical channel between adjacent routers Virtual Channel Controller: To multiplex/demultiplex virtual channels to the time-shared physical channel Crossbar Switch: To fully connect input buffers to output buffers in one-stage C. SILVANO Politecnico di Milano 19

20 PIRATE NoC Switching and Routing Wormhole switching Packets are in turns divided into flits Pipelining on a flit basis Small buffers (flit granularity fits better on-chip needs) Packet TAIL PAYLOAD HEADER Flit Type: last subsequent first Distributed routing with Best Effort service level Deterministic routing (No adaptive schemes) Fully static routing paths (table-based) Round-robin priority-based arbitration C. SILVANO Politecnico di Milano 20

21 Example of Virtual Channels The physical channel is time-shared by virtual channels Example of virtual channels composed of a pair of flit buffers connected to a shared physical channel R0 R1 R2 Packet Packet < R3 C. SILVANO Politecnico di Milano 21

22 Layered Approach: TCP/IP Stack vs NoC Stack TCP/IP STACK Application (FTP, HTTP, ) Transport (TCP, UDP) Network (IP) Physical (Ethernet, ATM, ) NoC STACK Application (System and Application) Transport (Network Interface) Network (Router) Physical (Physical Links) C. SILVANO Politecnico di Milano 22

23 Summary Network-on-Chip represents a new communication paradigm: Wide open area for research! Future works: Think about power, performance, fault-tolerance, quality-of-service and thermal aspects MPSoC architecture optimizations exploiting NoC features C. SILVANO Politecnico di Milano 47

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