October 20, 1998 (Version 1.0) Advance Product Specification. Description. Maximum Available I/O. XCV50 57,906 16x24 1, ,768 24,576

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1 Vitex 2.5 V Field Pogammable ate Aays ctobe 20, 1998 (Vesion 1.0) Advance Poduct Specification Featues Fast, high-deity Field-Pogammable ate Aays - Deities fom 50k to 1M system gates - System pefomance up to 150 MHz - 66-MHz PCI Compliant - Hot-swappable fo Compact PCI Multi-standad SelectI intefaces - 16 high-pefomance inteface standads - Connects diectly to ZBTAM devices Built-in clock-management cicuity - Fou dedicated delay-locked loops (DLLs) fo advanced clock contol - Fou pimay low-skew global clock distibution nets, plus 24 seconday global nets Hieachical memoy system - LUTs configuable as 16-bit AM, 32-bit AM, 16-bit dual-poted AM, o 16-bit Shift egiste - Configuable synchonous dual-poted 4k-bit AMs - Fast intefaces to extenal high-pefomance AMs Flexible achitectue that balances speed and deity - Dedicated cay logic fo high-speed aithmetic - Dedicated multiplie suppot - Cascade chain fo wide-input functio - Abundant egistes/latches with clock enable, and dual synchonous/asynchonous set and eset - Intenal 3-state bussing - IEEE bounday-scan logic - Die-tempeatue seing device Table 1: Vitex Field-Pogammable ate Aay Family Membes. Suppoted by FPA Foundation and Alliance Development Systems - Complete suppot fo Unified Libaies, elationally Placed Macos, and Design Manage - Wide selection of PC and wokstation platfoms SAM-based in-system configuation - Unlimited epogammability - Fou pogamming modes 0.25-µm five-laye metal pocess 100% factoy tested Desciption The Vitex FPA family delives high-pefomance, highcapacity pogammable logic solutio. Damatic inceases in silicon efficiency esult fom optimizing the new achitectue fo place-and-oute efficiency and exploiting an aggessive 5-laye-metal 0.25-µm CMS pocess. These advances make Vitex FPAs poweful and flexible altenatives to mask-pogammed gate aays. The Vitex family compises the nine membes shown in Table 1. Building on expeience gained fom pevious geneatio of FPAs, the Vitex family epesents a evolutionay step fowad in pogammable logic design. Combining a wide vaiety of pogammable system featues, a ich hieachy of fast, flexible inteconnect esouces, and advanced pocess technology, the Vitex family delives a high-speed and high-capacity pogammable logic solution that enhances design flexibility while educing time-to-maket. Device System ates CLB Aay Logic Cells Maximum Available I/ BlockAM Bits Max Select AM Bits XCV50 57,906 16x24 1, ,768 24,576 XCV ,904 20x30 2, ,960 38,400 XCV ,674 24x36 3, ,152 55,296 XCV ,666 28x42 5, ,344 75,264 XCV ,970 32x48 6, ,536 98,304 XCV ,252 40x60 10, , ,600 XCV ,111 48x72 15, , ,184 XCV ,439 56x84 21, , ,056 XCV1000 1,124,022 64x96 27, , ,216 ctobe 20, 1998 (Vesion 1.0) 1

2 Vitex 2.5 V Field Pogammable ate Aays Vitex Achitectue Vitex devices featue a flexible, egula achitectue that compises an aay of configuable logic blocks (CLBs) suounded by pogammable input/output blocks (IBs), all inteconnected by a ich hieachy of fast, vesatile outing esouces. The abundance of outing esouces pemits the Vitex family to accommodate even the lagest and most complex desig. Vitex FPAs ae SAM-based, and ae customized by loading configuation data into intenal memoy cells. In some modes, the FPA eads its own configuation data fom an extenal PM (maste seial mode). thewise, the configuation data is witten into the FPA (Select- MAP and slave seial modes). The standad Xilinx Foundation and Alliance Seies Development systems delive complete design suppot fo Vitex, coveing evey aspect fom behavioal and schematic enty, though flooplanning, simulation, automatic design talation and implementation, to the ceation, downloading, and eadback of a configuation bit steam. Highe Pefomance Vitex devices povide bette pefomance than pevious geneatio of FPA. Desig can achieve synchonous system clock ates ove 100 MHz including I/; intenal clock ates can easily exceed 100 MHz. Table 2: Pefomance fo Common Cicuit Functio Function Bits Vitex -6 egiste-to-egiste Adde Pipelined Multiplie Addess Decode x 8 16 x :1 Multiplexe 5.4 Paity Tee Chip-to-Chip HSTL Class IV LVTTL,16mA, fast slew MHz 180 MHz Achitectual Desciption Vitex Aay The Vitex use-pogammable gate aay, shown in Figue 1, compises two majo configuable elements: configuable logic blocks (CLBs) and input/output blocks (IBs). CLBs povide the functional elements fo cotucting logic IBs povide the inteface between the package pi and the CLBs CLBs inteconnect though a geneal outing matix (M). The M compises an aay of outing switches located at the intesectio of hoizontal and vetical outing channels. Each CLB nests into a VesaBlock that also povides local outing esouces to connect the CLB to the M. The Vesaing I/ inteface povides additional outing esouces aound the peiphey of the device. This outing impoves I/ outability and facilitates pin locking. The Vitex achitectue also includes the following cicuits that connect to the M. Dedicated block memoies of 4096 bits each Clock DLLs fo clock-distibution delay compeation and clock domain contol 3-State buffes (BUFTs) associated with each CLB that dive dedicated segmentable hoizontal outing esouces Values stoed in static memoy cells contol the configuable logic elements and inteconnect esouces. These values load into the memoy cells on powe-up, and can eload if necessay to change the function of the device. DLL IBs Vesaing BAMs IBs Vesaing CLBs BAMs Vesaing DLL IBs Vitex inputs and outputs comply fully with PCI specificatio, and intefaces can be implemented that opeate at 33 MHz o 66 MHz. Additionally, Vitex suppots the hot-swapping equiements of Compact PCI. Xilinx thooughly benchmaked the Vitex family. While pefomance is design-dependent, many tested desig opeated intenally at speeds in excess of 100 MHz. Table 2 shows pefomance data fo epesentative cicuits, using wost-case timing paametes. Vesaing IBs DLL Figue 1: Vitex Achitectue veview DLL vao_b.eps 2 ctobe 20, 1998 (Vesion 1.0)

3 A set of Supplementay Desciption documents published sepaately augment the following desciption of the vaious Vitex-achitectue components. The Supplementay Desciptio povide moe detailed infomation and cove the following topics. Input/utput Block Configuable Logic Block Memoy esouces Clock Distibution outing esouces Configuation and eadback Bounday Scan Powe Coumption Input/utput Block The Vitex IB, Figue 2, featues SelectI inputs and outputs that suppot a wide vaiety of I/ signalling standads, see Table 3. These high-speed inputs and outputs ae capable of suppoting PCI intefaces up to 66 MHz. The thee IB stoage elements function eithe as edgetiggeed D-type flip-flops o as level seitive latches. Each IB has a clock signal (CLK) shaed by the thee flipflops and independent clock enable signals fo each flipflop. In addition to the CLK and CE contol signals, the thee flipflops shae a Set/eset (S). Fo each flip-flop, this signal can be independently configued as a synchonous Set, a synchonous eset, an asynchonous Peset, o an asynchonous Clea. The input and output buffes and all of the IB contol signals have independent polaity contols. All pads ae potected agait damage fom electostatic dischage (ESD) and fom ove-voltage taients. Two foms of ove-voltage potection ae povided, one that pemits 5-V compliance, and one that does not. Fo 5-V compliance, a zene-like stuctue connected to gound tu on when the output ises to appoximately 6.5 V. When 5-V compliance is not equied, a conventional clamp diode may be connected to the output supply voltage, V CC. The type of ove-voltage potection can be selected independently fo each pad. ptional pull-up and pull-down esistos and an optional weak-keepe cicuit ae attached to each pad. Pio to configuation all outputs ae foced into thei high-impedance state. The pull-up and pull-down esistos and the weakkeepe cicuit ae inactive, and input floats. If the design equies a defined input logic level pio to configuation, an extenal esisto must be used. All Vitex IBs suppot IEEE compatible bounday scan testing. PS T TCE D EC Q L Weak Keepe S CE PS D Q EC L BUF PAD S I IQ PS Q D EC L Pogammable Delay IBUF S Vef S CLK ICE iob_c.eps Figue 2: Vitex Input/utput Block (IB) ctobe 20, 1998 (Vesion 1.0) 3

4 Vitex 2.5 V Field Pogammable ate Aays Table 3: Suppoted Select I/ Standads I/ Standad Input Path Input efeence Voltage (V EF ) utput Souce Voltage (V CC ) Boad Temination Voltage (V TT ) LVTTL N/A 3.3 N/A LVCMS2 N/A 2.5 N/A PCI N/A 3.3 N/A TL 0.8 N/A 1.2 TL+ 1.0 N/A 1.5 HSTL Class I HSTL Class III HSTL Class IV SSTL3 Class I and II SSTL2 Class I and II CTT AP N/A A buffe In the Vitex IB input path outes the input signal eithe diectly to intenal logic o though an optional input flip-flop. An optional delay element at the D-input of this flip-flop eliminates pad-to-pad hold time. The delay is matched to the intenal clock-distibution delay of the FPA, and when used, assues that the pad-to-pad hold time is zeo. Each input buffe can be configued to confom to any of the low-voltage signalling standads suppoted. In some of these standads the input buffe utilizes a use-supplied theshold voltage, V EF. The need to supply V EF imposes cotaints on which standads can used in close poximity to each othe. See I/ Banking on page 4. ptional pull-up and pull-down esistos exist at each input with a value of appoximately kohms. utput Path The output path includes a 3-state output buffe that dives the output signal onto the pad. The output signal can be outed to the buffe diectly fom the intenal logic o though an optional IB output flip-flop. The 3-state contol of the output can also be outed diectly fom the intenal logic o though a flip-flip that povides synchonous enable and disable. Each output dive can be individually pogammed fo a wide ange of low-voltage signalling standads. Each output buffe can souce up to 24 ma and sink up to 40mA. Dive stength and slew ate contols minimize bus taients. In most signalling standads, the output High voltage depends on an extenally supplied V CC voltage. The need to supply V CC imposes cotaints on which standads can be used in close poximity to each othe. See I/ Banking on page 4. An optional weak-keepe cicuit is connected to each output. When selected, the cicuit monitos the voltage on the pad and weakly dives the pin High o Low to match the input signal. If the pin is connected to a multiple-souce signal, the weak keepe holds the signal in its last state if all dives ae disabled. Maintaining a valid logic level in this way eliminates bus chatte. Because the weak-keepe cicuit uses the IB input buffe to monito the input level, an appopiate V EF voltage must be povided if the signalling standad equies one. The povision of this voltage must comply with the I/ banking ules. I/ Banking Some of the I/ standads descibed above equie V CC and/o V EF voltages. These voltages extenally and connected to device pi that seve goups of IBs, called banks. Coequently, estictio exist about which I/ standads can be combined within a given bank. Eight I/ banks esult fom sepaating each edge of the FPA into two banks, as shown in Figue 3. Each bank has multiple V CC pi, all of which must be connected to the same voltage. This voltage is detemined by the output standads in use. 4 ctobe 20, 1998 (Vesion 1.0)

5 Bank 7 Bank 6 Bank 0 Bank 1 CLK3 CLK2 Vitex Device CLK1 CLK0 Bank 5 Bank 4 Figue 3: Vitex I/ Banks X8778_b Within a bank, output standads may be mixed only if they use the same V CC. Compatible standads ae shown in Table 4. TL and TL+ appea unde all voltages because thei open-dain outputs do not depend on V CC. Table 4: Compatible utput Standads V CC Compatible Standads 3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AP, TL, TL+ 2.5 V SSTL2 I, SSTL2 II, LVCMS2, TL, TL+ 1.5 V HSTL I, HSTL III, HSTL IV, TL, TL+ Some input standads equie a use-supplied theshold voltage, V EF. In this case, cetain use-i/ pi ae automatically configued as inputs fo the V EF voltage. Appoximately one in six of the I/ pi in the bank assume this ole. The V EF pi within a bank ae inteconnected intenally and coequently only one V EF voltage can be used within each bank. All V EF pi in the bank, howeve, must be connected to the extenal voltage souce fo coect opeation. Within a bank, inputs that equie V EF can be mixed with those that do not. Howeve, only one V EF voltage may be used within a bank.input buffes that use V EF ae not 5Vtoleant. The V CC and V EF pi fo each bank appea in the device pin-out tables and diagams. The diagams also show the bank affiliation of each I/. Within a given package, the numbe of V EF and V CC pi can vay depending on the size of device. In lage devices, moe I/ pi convet to V EF pi. Since these ae always a supeset of the V EF pi used fo smalle devices, it is possible to design a PCB that pemits migation to a lage Bank 2 Bank 3 device if necessay. All the V EF pi fo the lagest device anticipated must be connected to the V EF voltage, and not used fo I/. In smalle devices, some V CC pi used in lage devices do not connect connected within the package. These unconnected pi may be left unconnected extenally, o may be connected to the V CC voltage to pemit migation to a lage device if necessay. In HQ and PQ packages, all V CC pi ae bonded togethe intenally, and coequently the same V CC voltage must be connected to all of them. The V EF pi emain intenally connected as eight banks, and may be used as descibed peviously. Configuable Logic Block The basic building block of the Vitex CLB is the logic cell (LC). An LC includes a 4-input function geneato, cay logic, and a stoage element. The output fom the function geneato in each LC dives both the CLB output and the D input of the flip-flop. Each Vitex CLB contai fou LCs, oganized in two simila slices, as shown in Figue 4. Figue 5 shows a moe detailed view of a single slice. In addition to the fou basic LCs, the Vitex CLB contai logic that combines function geneatos to povide functio of five o six inputs. Coequently, when estimating the numbe of system gates povided by a given device, each CLB counts as 4.5 LCs. Look-Up Tables Vitex function geneatos ae implemented as 4-input lookup tables (LUTs). In addition to opeating as a function geneato, each LUT can povide a 16 x 1-bit synchonous AM. Futhemoe, the two LUTs within a slice can be combined to ceate a 16 x 2-bit o 32 x 1-bit synchonous AM, o a 16x1-bit dual-pot synchonous AM. The Vitex LUT can also povide a 16-bit shift egiste that is ideal fo captuing high-speed o bust-mode data. This mode can also be used to stoe data in applicatio such as Digital Signal Pocessing. Stoage Elements The stoage elements in the Vitex slice can be configued eithe as edge-tiggeed D-type flip-flops o as level-seitive latches. The D inputs can be diven eithe by the function geneatos within the slice o diectly fom slice inputs, bypassing the function geneatos. In addition to Clock and Clock Enable signals, each Slice has synchonous Set and eset signals (S and BY). Altenatively, these signals may be configued as asynchonous Peset and Clea All of the contol signals ae independently invetible, and ae shaed by the two flip-flops within the slice. ctobe 20, 1998 (Vesion 1.0) 5

6 Vitex 2.5 V Field Pogammable ate Aays CUT CUT LUT Cay & Contol SP D Q EC YB Y YQ LUT Cay & Contol SP D Q EC YB Y YQ BY F4 F3 F2 F1 LUT Cay & Contol C SP D Q EC XB X XQ BY F4 F3 F2 F1 LUT Cay & Contol C SP D Q EC XB X XQ BX C BX C Slice 1 Slice 0 CIN CIN slice_b.eps Figue 4: Vitex CLB Additional Logic The F5 multiplexe in each slice combines the function geneato outputs. This combination povides eithe a function geneato that can implement any 5-input function, a 4:1 multiplexe, o selected functio of up to nine inputs. Similaly, the F6 multiplexe combines the outputs of all fou function geneatos in the CLB. This pemits the implementation of any 6-input function, an 8:1 multiplexe, o selected functio of up to 19 inputs. Each CLB has fou diect feedthough paths, one pe LC. These paths povide exta data input lines o additional local outing that does not coume logic esouces. Aithmetic Logic Dedicated cay logic povides fast aithmetic cay capability fo high-speed aithmetic functio. The Vitex CLB suppots two sepaate cay chai, one pe Slice. The height of the cay chai is two bits pe CLB. The aithmetic logic includes an X gate that allows a 1- bit full adde to be implemented within an LC. In addition, a dedicated AND gate impoves the efficiency of multiplie implementation. The dedicated cay path can also be used to cascade function geneatos fo implementing wide logic functio. BUFTs Each Vitex CLB contai two 3-state dives (BUFTs) that can dive on-chip busses. See Dedicated outing on page 9. Each Vitex BUFT has an independent 3-state contol pin and an independent input pin. Block AM Vitex FPAs incopoate seveal lage BlockSelectAM+ memoies. These complement the distibuted SelectAM+ LUTAMs that povide shallow AM stuctues implemented in CLBs. BlockSelectAM+ memoy blocks ae oganized in colum. All Vitex devices contain two such colum, one along each vetical edge. These colum extend the full height of the chip. Each memoy block is fou CLBs high, and coequently, a Vitex device 64 CLBs high will contain16 memoy blocks pe column, and a total of 32 blocks. 6 ctobe 20, 1998 (Vesion 1.0)

7 CUT CY YB I3 I2 I1 I0 WE LUT DI 0 INIT D Q EC Y YQ BY F5IN 1 F6 EV XB CY F5 F5 BX CK WE A4 WS WSH BY D BX DI INIT D Q EC X XQ F4 F3 F2 F1 I3 I2 I1 I0 WE LUT DI EV 0 1 S CLK CE Figue 5: Detailed View of Vitex Slice CIN viewslc4.eps Table 5 shows the amount of Block SelectAM+ memoy that is available in each Vitex device. Each BlockSelectAM+ cell, as illustated in Figue 6, is a fully synchonous dual-poted 4096-bit AM with independent contol signals fo each pot. The data widths of the two pots can be configued independently, poviding builtin bus-width convesion. Table 5: Vitex Block SelectAM+ Amounts Vitex Device # of Blocks Total Block SelectAM+ Bits XCV ,768 XCV ,960 XCV ,152 XCV ,344 XCV ,536 XCV ,920 XCV ,304 XCV ,688 XCV ,072. WEA ENA STA CLKA ADD<#:0> DIA<#:0> WEB ENB STB CLKB ADDB<#:0> DINB<#:> AM4_S#_S# DA<#:0> DB<#:0> amb_a.eps Figue 6: Dual-Pot Block Select am+ ctobe 20, 1998 (Vesion 1.0) 7

8 Vitex 2.5 V Field Pogammable ate Aays Table 6 shows the depth and width aspect atios fo the Block SelectAM+ Table 6: Block SelectAM+ Pot Aspect atios Width Depth ADD Bus Data Bus ADD<11:0> DATA<0> ADD<10:0> DATA<1:0> ADD<9:0> DATA<3:0> ADD<8:0> DATA<7:0> ADD<7:0> DATA<15:0> The Vitex block AM also includes dedicated outing to povide an efficient inteface with both CLBs and othe block AMs. Pogammable outing Matix It is the longest delay path that limits the speed of any wost-case design. Coequently, the Vitex outing achitectue and its place-and-oute softwae wee defined in a single optimization pocess. This joint optimization minimizes long-path delays, and coequently, yields the best system pefomance. The joint optimization also educes design compilation times because the achitectue is softwae-fiendly. Design cycles ae coespondingly educed due to shote design iteation times. Local outing The VesaBlock povides local outing esouces, as shown in Figue 7, poviding the following thee types of connectio. Inteconnectio among the LUTs, flip-flops, and M Intenal CLB feedback paths that povide high-speed connectio to LUTs within the same CLB, chaining them togethe with minimal outing delay Diect paths that povide high-speed connectio between hoizontally adjacent CLBs, eliminating the delay of the M. eneal Pupose outing Most Vitex signals ae outed on the geneal pupose outing, and coequently, the majoity of inteconnect esouces ae associated with this level of the outing hieachy. The geneal outing esouces ae located in hoizontal and vetical outing channels associated with the ows and colum CLBs. The geneal-pupose outing esouces ae listed below. Adjacent to each CLB is a eneal outing Matix (M). The M is the switch matix though which hoizontal and vetical outing esouces connect, and is also the mea by which the CLB gai access to the geneal pupose outing. 24 single-length lines oute M signals to adjacent Ms in each of the fou diectio. 96 buffeed Hex lines oute M signals to anothe Ms six-blocks away in each one of the fou diectio. ganized in a staggeed patten, Hex lines may be diven only at thei endpoints. Hex-line signals can be accessed eithe at the endpoints o at the midpoint (thee blocks fom the souce). ne thid of the Hex lines ae bidiectional, while the emaining ones ae uni-diectional. 12 Longlines ae buffeed, bidiectional wies that distibute signals acoss the device quickly and efficiently. Vetical Longlines span the full height of the device, and hoizontal ones span the full width of the device. I/ outing Vitex devices have additional outing esouces aound thei peiphey that fom an inteface between the CLB aay and the IBs. This additional outing, called the Vesaing, facilitates pin-swapping and pin-locking, such that logic edesig can adapt to existing PBC layouts. Time-tomaket is educed, since PCBs and othe system components can be manufactued while the logic design is still in pogess. 8 ctobe 20, 1998 (Vesion 1.0)

9 To Adjacent M To Adjacent M M To Adjacent M To Adjacent M Diect Connection To Adjacent CLB CLB Diect Connection To Adjacent CLB X8794b Figue 7: Vitex Local outing Dedicated outing Some classes of signal equie dedicated outing esouces to maximize pefomance. In the Vitex achitectue, dedicated outing esouces ae povided fo two classes of signal. Hoizontal outing esouces ae povided fo on-chip 3- state busses. Fou patitionable bus lines ae povided pe CLB ow, pemitting multiple busses within a ow, as shown in Figue 8. Two dedicated nets pe CLB popagate cay signals vetically to the adjacent CLB. lobal outing lobal outing esouces distibute clocks and othe signals with vey high fanout thoughout the device. Vitex devices include two ties of global outing esouces efeed to as pimay and seconday global outing esouces. The pimay global outing esouces ae fou dedicated global nets with dedicated input pi that ae designed to distibute high-fanout clock signals with minimal skew. Each global clock net can dive all CLB, IB, and block AM clock pi. The pimay global nets may only Ti-State Lines CLB CLB CLB CLB buft_c.eps Figue 8: BUFT Connectio to Dedicated Hoizontal Bus Lines ctobe 20, 1998 (Vesion 1.0) 9

10 Vitex 2.5 V Field Pogammable ate Aays be diven by global buffes. Thee ae fou global buffes, one fo each global net. The seconday global outing esouces coist of 24 backbone lines, 12 acoss the top of the chip and 12 acoss bottom. Fom these lines, up to 12 unique signals pe column can be distibuted via the 12 longlines in the column. These seconday esouces ae moe flexible than the pimay esouces since they ae not esticted to outing only to clock pi. Clock Distibution Vitex povides high-speed, low-skew clock distibution though the pimay global outing esouces descibed above. A typical clock distibution net is shown in Figue 9. Fou global buffes ae povided, two at the top cente of the device and two at the bottom cente. These dive the fou pimay global nets that in tun dive any clock pin. Fou dedicated clock pads ae povided, one adjacent to each of the global buffes. The input to the global buffe is selected eithe fom these pads o fom signals in the geneal pupose outing. Delay-Locked Loop (DLL) Associated with each global clock input buffe is a fully digital Delay-Locked Loop (DLL) that can eliminate skew between the clock input pad and intenal clock-input pi thoughout the device. Each DLL can dive two global clock netwoks.the DLL monitos the input clock and the distibuted clock, and automatically adjusts a clock delay element. Additional delay is intoduced such that clock edges each intenal flip-flops exactly one clock peiod afte they aive at the input. This closed-loop system effectively eliminates clock-distibution delay by euing that clock edges aive at intenal flip-flops in synchonism with clock edges aiving at the input. In addition to eliminating clock-distibution delay, the DLL povides advanced contol of multiple clock domai. The DLL povides fou quadatue phases of the souce clock, can double the clock, o divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, o 16. It has six outputs.+ The DLL also opeates as a clock mio. By diving the output fom a DLL off-chip and then back on again, the DLL can be used to deskew a boad level clock among multiple Vitex devices. In ode to guaantee that the system clock is opeating coectly pio to the FPA stating up afte configuation, the DLL can delay the completion of the configuation pocess until afte it has achieved lock. CLKPAD3 CLKBUF3 CLKPAD2 CLKBUF2 lobal Clock ows lobal Clock Column lobal Clock Spine CLKBUF1 CLKPAD1 CLKBUF0 CLKPAD0 gclkbu_2.eps Figue 9: lobal Clock Distibution Netwok 10 ctobe 20, 1998 (Vesion 1.0)

11 Bounday Scan Vitex devices suppot all the mandatoy bounday-scan ituctio specified in the IEEE standad A Test Access Pot (TAP) and egistes ae povided that implement the EXTEST, SAMPLE/PELAD, and BYPASS ituctio. The TAP also suppots two USECDE ituctio and intenal scan chai Bounday-scan opeation is independent of individual IB configuatio, and unaffected by package type. All IBs, including unbonded ones, ae teated as independent 3- state bidiectional pi in a single scan chain. etention of the bidiectional test capability afte configuation facilitates the testing of extenal inteconnectio. Table 7 lists the bounday-scan ituctio suppoted in Vitex FPAs. Intenal signals can be captued duing EXTEST by connecting them to unbonded o unused IBs. They may also be connected to the unused outputs of IBs defined as unidiectional input pi. This technique patially compeates fo the absence of INTEST suppot. Table 7: Bounday-Scan Ituctio Bounday-Scan Command Binay Code(4:0) Desciption EXTEST Enables bounday-scan EXTEST opeation SAMPLE Enables bounday-scan SAMPLE opeation US Access use-defined egiste 1 US Access use-defined egiste 2 CF_UT Access the configuation bus fo eadback CF_IN Access the configuation bus fo Configuation INTEST Enables bounday-scan intest opeation USCDE Enables shifting out USE code IDCDE Enables shifting out of ID Code HIZ Ti-states output pi while enabling the Bypass egiste BUS_ST eset the Configuation Bus JSTAT Clock the statup sequence when StatupClk is TCK BYPASS Enables BYPASS ESEVED All othe codes Xilinx eseved ituctio The public bounday-scan ituctio ae available pio to configuation. Afte configuation, the public ituctio emain available togethe with any USECDE ituctio italled duing the configuation. While the SAMPLE and BYPASS ituctio ae available duing configuation, it is ecommended that bounday-scan opeatio not be pefomed duing this taitional peiod. In addition to the test ituctio outlined above, the bounday-scan cicuity can be used to configue the FPA, and also to ead back the configuation data. To facilitate intenal scan chai, the Use egiste povides thee outputs (eset, Update, and Shift) that epesent the coesponding states in the bounday-scan intenal state machine. Fo details on bounday scan, efe to the Application Note Bounday Scan in XC4000 Devices on the Xilinx web site. Development System Vitex FPAs ae suppoted by the Xilinx Foundation and Alliance CAE tools. The basic methodology fo Vitex design coists of thee inteelated steps: design enty, implementation, and veification. Industy-standad tools ae used fo design enty and simulation (fo example, Synopsys FPA Expess), while Xilinx povides popietay achitectue-specific tools fo implementation. The Xilinx development system is integated unde the Xilinx Design Manage (XDM ) softwae, poviding designes with a common use inteface egadless of thei choice of enty and veification tools. The XDM softwae simplifies the selection of implementation optio with pull-down menus and on-line help. Application pogams anging fom schematic captue to Placement and outing (PA) can be accessed though the XDM softwae. The pogam command sequence is geneated pio to execution, and stoed fo documentation. Seveal advanced softwae featues facilitate Vitex design. PMs, fo example, ae schematic-based macos with elative location cotaints to guide thei placement. They help eue optimal implementation of common functio. Fo HDL design enty, the Xilinx FPA Foundation development system povides intefaces to the following synthesis design envionments. Synopsys (FPA Compile, FPA Expess) Exempla (Leonado) Synplicity (Synplify) Fo schematic design enty, the Xilinx FPA Foundation and alliance development system povides intefaces to the following schematic-captue design envionments. Mento aphics V8 (Design Achitect, QuickSim II) Viewlogic Systems (Viewdaw) Thid-paty vendos suppot many othe envionments. ctobe 20, 1998 (Vesion 1.0) 11

12 Vitex 2.5 V Field Pogammable ate Aays A standad inteface-file specification, Electonic Design Intechange Fomat (EDIF), simplifies file tafes into and out of the development system. Vitex FPAs suppoted by a unified libay of standad functio. This libay contai ove 400 pimitives and macos, anging fom 2-input AND gates to 16-bit accumulatos, and includes aithmetic functio, compaatos, countes, data egistes, decodes, encodes, I/ functio, latches, Boolean functio, multiplexes, shift egistes, and bael shiftes. The soft maco potion of the libay contai detailed desciptio of common logic functio, but does not contain any patitioning o placement infomation. The pefomance of these macos depends, theefoe, on the patitioning and placement obtained duing implementation. PMs, on the othe hand, do contain pedetemined patitioning and placement infomation that pemits optimal implementation of these functio. Uses can ceate thei own libay of soft macos o PMs based on the macos and pimitives in the standad libay. The design envionment suppots hieachical design enty, with high-level schematics that compise majo functional blocks, while lowe-level schematics define the logic in these blocks. These hieachical design elements ae automatically combined by the implementation tools. Diffeent design enty tools can be combined within a hieachical design, thus allowing the most convenient enty method to be used fo each potion of the design. Design Implementation The place-and-oute tools (PA) automatically povide the implementation flow descibed in this section. The patitione takes the EDIF netlist fo the design and maps the logic into the achitectual esouces of the FPA (CLBs and IBs, fo example). The place then detemines the best locatio fo these blocks based on thei inteconnectio and the desied pefomance. Finally, the oute inteconnects the blocks. The PA algoithms suppot fully automatic implementation of most desig. Fo demanding applicatio, howeve, the use can execise vaious degees of contol ove the pocess. Use patitioning, placement, and outing infomation is optionally specified duing the design-enty pocess. The implementation of highly stuctued desig can benefit geatly fom basic flooplanning. The implementation softwae incopoates Timing Wizad timing-diven placement and outing. Designes specify timing equiements along entie paths duing design enty. The timing path analysis outines in PA then ecognize these use-specified equiements and accommodate them. Timing equiements ae enteed on a schematic in a fom diectly elating to the system equiements, such as the tageted clock fequency, o the maximum allowable delay between two egistes. In this way, the oveall pefomance of the system along entie signal paths is automatically tailoed to use-geneated specificatio. Specific timing infomation fo individual nets is unnecessay. Design Veification In addition to conventional softwae simulation, FPA uses can use in-cicuit debugging techniques. Because Xilinx devices ae infinitely epogammable, desig can be veified in eal time without the need fo exteive sets of softwae simulation vectos. The development system suppots both softwae simulation and in-cicuit debugging techniques. Fo simulation, the system extacts the post-layout timing infomation fom the design database, and back-annotates this infomation into the netlist fo use by the simulato. Altenatively, the use can veify timing-citical potio of the design using the TACE static timing analyze. Fo in-cicuit debugging, the development system includes a download and eadback cable. This cable connects the FPA in the taget system to a PC o wokstation. Afte downloading the design into the FPA, the designe can single-step the logic, eadback the contents of the flip-flops, and so obseve the intenal logic state. Simple modificatio can be downloaded into the system in a matte of minutes. Configuation Vitex devices ae configued by loading configuation data into the intenal configuation memoy. Some of the pi used fo this ae dedicated configuation pi, while othes may be e-used as geneal pupose inputs and outputs once configuation is complete. The dedicated pi ae the mode pi (M2, M1, M0), the configuation clock pin (CCLK), the PAM pin, the DNE pin and the bounday-scan pi (TDI, TD, TMS, TCK). Depending on the configuation mode chosen, CCLK may be an output geneated by the FPA, o may be geneated extenally, and povided to the FPA as an input. Fo a moe detailed desciption than that given below, see the Supplementay Desciption on Configuation and eadback. Configuation Modes Vitex suppots the following fou configuation modes. Slave-seial mode Maste-seial mode SelectMAP mode Bounday-scan mode 12 ctobe 20, 1998 (Vesion 1.0)

13 The Configuation mode pi (M2, M1, M0) select these configuation modes. The selection codes ae listed in Table 8. Note that unlisted selection codes ae eseved. Table 8: Configuation Codes Configuation though the bounday-scan pot is always available, independent of the mode selection. Selecting the bounday-scan mode simply tu off the othe modes. The thee mode pi have intenal pull-up esistos, and default to a logic High if left unconnected. Configuation Mode M2 M1 M0 CCLK Diection Data Width Seial D out Maste-seial mode ut 1 Yes Bounday-scan mode N/A 1 No SelectMAP mode In 8 No Slave-seial mode In 1 Yes Slave Seial Mode In slave seial mode, the FPA eceives configuation data in bit-seial fom fom a seial PM o othe souce of seial configuation data. The seial bitsteam must be setup at the DIN input pin a shot time befoe each ising edge of an extenally geneated CCLK. Multiple FPAs can be daisy-chained fo configuation fom a single souce. Afte a paticula FPA has been configued, the data fo the next device is outed to the DUT pin. The data on the DUT pin changes on the ising edge of CCLK. The captue of DIN on the ising edge of CCLK diffes fom pevious families, but will not cause a poblem fo mixed. NTE: M2, M1, M0 can be shoted to ound if not used as I/ configuation chai. This change was made to impove seial-configuation ates fo Vitex only chai. Figue 10 shows a full maste/slave system. A Vitex device in slave seial mode should be connected as shown in the thid device fom the left Slave-seial mode is selected by applying <111> to the mode pi (M2, M1, M0). A weak pull-up on the mode pi makes slave seial the default mode if the pi ae left unconnected. Figue 11 shows slave-seial configuation timing. Table 9 povides moe detail about the chaacteistics shown in Figue 11. Configuation must be delayed until the INIT pi of all daisy-chained FPAs ae High. 4.7 K 4.7 K 4.7 K VCC N/C M0 M2 M1 4.7 K N/C M0 M2 M1 DUT DIN DUT VITEX MASTE SEIAL CCLK DIN XC1700E CLK VPP DATA +5 V CCLK VITEX, XC4000XL, SLAVE PAM CE CE PAM DNE INIT ESET/E DNE INIT (Low eset ption Used) PAM X9025_b Figue 10: Maste/Slave Seial Mode Cicuit Diagam ctobe 20, 1998 (Vesion 1.0) 13

14 Vitex 2.5 V Field Pogammable ate Aays DIN 1 T DCC 2 T CCD 5 T CCL CCLK 4 T CCH 3 T CC DUT (utput) X5379_a Figue 11: Slave Seial Mode Pogamming Switch Table 9: Slave Seial Mode Pogamming Switching CCLK Desciption Symbol Units DIN setup/hold 1/2 T DCC /T CCD 2.0/0.0 DUT 3 T CC 9.0 High time 4 T CCH 5.0 Low time 5 T CCL 5.0 Maximum Fequency F CC 66 MHz, max Maste Seial Mode In maste seial mode, the CCLK output of the FPA dives a Xilinx Seial PM that feeds bit-seial data to the DIN input. The FPA accepts this data on each ising CCLK edge. Afte the FPA has been loaded, the data fo the next device in a daisy-chain is pesented on the DUT pin afte the ising CCLK edge. The peamble is also fowaded to othe devices in the daisy-chain. The inteface is identical to slave seial except that an intenal oscillato is used to geneate the configuation clock (CCLK). A wide ange of fequencies can be selected fo CCLK which always stats at a slow default fequency. Configuation bits then switch CCLK to a highe fequency fo the emainde of the configuation. Switching to a lowe fequency is pohibited. The CCLK fequency is set using the Configate option in the bitsteam geneation softwae. When selecting a CCLK fequency, eue that the seial PM and any daisychained FPAs ae fast enough to suppot this ate. Figue 10 shows a full maste/slave system. In this system, the leftmost device opeates in maste-seial mode. The emaining devices opeate in slave-seial mode. The SPM ESET pin is diven by INIT, and CE input is diven by DNE. Thee is, theefoe, the potential fo contention on the DNE pin, depending on the stat-up sequence optio chosen. The sequence of opeatio necessay to configue a Vitex FPA seially appeas in Figue 12. Figue 13 shows the timing of maste-seial configuation. Maste seial mode is selected by a <000> on the mode pi (M2, M1, M0). Table 10 shows the timing infomation fo Figue 13 At powe-up, Vcc must ise fom 2.0 V to Vcc min in less than 25 ms, othewise delay configuation by pulling P- AM Low until Vcc is valid. Table 10: Maste Seial Mode Pogamming Switching Desciption Symbol Units CCLK DIN setup/hold 1/2 T DSCK /T SCKD 2.0/0.0 Note: Maste seial mode timing is based on testing in slave mode. SelectMAP Mode The SelectMAP mode is the fastest configuation option. Byte-seial data is witten into the FPA with a BUSY flag contolling the flow of data. An extenal data souce povides a byte steam, CCLK, a Chip Select (CS) signal and a Wite signal (WITE). If BUSY is asseted (High) by the FPA, the data must be held until BUSY goes Low. Data can also be ead using the SelectMAP mode. If WITE is not asseted, configuation data is ead out of the FPA as pat of a eadback opeation. 14 ctobe 20, 1998 (Vesion 1.0)

15 FPA stats to clea configuation memoy. FPA makes a final cleaing pass and eleases INIT when finished. Apply Powe Set PAM = High elease INIT If used to delay configuation If used to delay configuation INIT? Low High Load a Configuation Bit nce a Fame, FPA checks data using CC and pulls INIT Low on eo. End of Bitsteam? No If no CC eos found, FPA entes stat-up phase causing DNE to go High. Yes Configuation Completed X8793_a Figue 12: Seial Configuation Flowchat. CCLK (utput) 2 T CKDS 1 T DSCK Seial Data In Seial DUT (utput) X3223_a Figue 13: Maste Seial Mode Pogamming Switching Chaacteistics ctobe 20, 1998 (Vesion 1.0) 15

16 Vitex 2.5 V Field Pogammable ate Aays Afte configuation, the pi of the SelectMAP pot can be used as additional use I/. Altenatively, the pot may be etained to pemit high-speed 8-bit eadback. etention of the SelectMAP pot is selectable on a designby-design basis when the bitsteam is geneated. If etention is selected, PHIBIT cotaints ae equied to pevent the SelectMAP-pot pi fom being used as use I/. Multiple Vitex FPAs can be configued using the Select- MAP mode, and be made to stat-up simultaneously. To configue multiple devices in this way, wie the individual CCLK, Data, WITE, and BUSY pi of all the devices in paallel. The individual devices ae loaded sepaately by asseting the CS pin of each device in tun and witing the appopiate data.. CCLK CS 3 4 WITE DATA[7:0] BUSY 7 No Wite Wite No Wite Wite X8796_b Figue 14: SelectMAP Wite Wavefoms Wite Wite opeatio send packets of configuation data into the FPA. The sequence of opeatio fo a multi-cycle wite opeation is shown below. Note that a configuation packet can be split into many such sequences. The packet does not have to complete within one assetion of CS, illustated in Figue Asset WITE and CS Low. Note that when CS is asseted on successive CCLKs, WITE must emain eithe asseted o deasseted. thewise an abot will be initiated, as descibed below. 2. Dive data onto D[7:0]. Note that to avoid contention, the data souce should not be enabled while CS is Low and WITE is High. Similaly, while WITE is High, no moe that one CS should be asseted. 3. At the ising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High fom a pevious wite, the data is not be accepted. Acceptance will itead occu on the fist clock afte BUSY goes Low, and the data must be held until this has happened. 4. epeat steps 2 and 3 until all the data has been sent. 5. Deasset CS and WITE. A flowchat fo the wite opeation appeas in Figue 14. Note that if CCLK is slowe than f CCNH, the FPA will neve asset BUSY, In this case, the above handshake is unnecessay, and data can simply be enteed into the FPA evey CCLK cycle. Table 11: SelectMAP Wite Timing Chaacteistics CCLK Desciption Symbol Units D 0-7 Setup/Hold 1/2 T SMDCC /T SMCCD 2.0/0.0 CS Setup/Hold 34 T SMCSCC /T SMCCCS 2.0/0.0 WITE Setup/Hold 5/6 T SMCCW /T SMWCC 2.0/0.0 BUSY Popagation Delay 7 T SMCKBY 9.0 Maximum Fequency f CCNH 50 MHz, max with no handshake 16 ctobe 20, 1998 (Vesion 1.0)

17 FPA stats to clea configuation memoy. FPA makes a final cleaing pass and eleases INIT when finished. Apply Powe Set PAM = High elease INIT If used to delay configuation If used to delay configuation INIT? Low High Set WITE = Low Ente Data Souce Sequence A Set CS = Low n fist FPA Apply Configuation Byte nce a Fame, FPA checks data using CC and pulls INIT Low on eo. Busy? High Low End of Data? No If no eos, fist FPAs ente stat-up phase eleasing DNE. Yes Set CS = High n fist FPA If no eos, late FPAs ente stat-up phase eleasing DNE. epeat Sequence A Fo any othe FPAs Disable Data Souce When all DNE pi ae eleased, DNE goes High and stat-up sequences complete. Set WITE = High Configuation Completed X8795_a Figue 14: SelectMAP Flowchat fo Wite peation ctobe 20, 1998 (Vesion 1.0) 17

18 Vitex 2.5 V Field Pogammable ate Aays Abot Duing a given assetion of CS, the use cannot switch fom a wite to a ead, o vice-vesa. This action causes the cuent packet command to be aboted. The device will emain BUSY until the aboted opeation has completed. Following an abot, data is assumed to be unaligned to wod boundaies, and the FPA equies a new synchonization wod pio to accepting any new packets. To initiate an abot duing a wite opeation, deasset WITE. At the ising edge of CCLK, an abot is initiated, as shown in Figue 15. CCLK CC WITE DATA[7:0] FPA BUSY Figue 15: SelectMAP Wite Abot Wavefoms Abot X8797_b Bounday-Scan Mode In the bounday-scan mode, no non-dedicated pi ae equied, configuation being done entiely though the IEEE Test Access Pot. Configuation though the TAP uses the special CF_IN ituction. This ituction allows data input on TDI to be conveted into data packets fo the intenal configuation bus. The following steps ae equied to configue the FPA though the bounday-scan pot. 6. Load the CF_IN ituction into the bounday-scan ituction egiste (I) 7. Ente the Shift-D (SD) state 8. Shift a standad configuation bitsteam into TDI 9. etun to un-test-idle (TI) 10.Load the JSTAT ituction into I 11.Ente the SD state 12.Clock TCK fo the length of the sequence (the length is pogammable) 13.etun to TI As noted above, configuation and eadback is always available. The bounday-scan mode simply locks out the othe modes. The bounday-scan mode is selected by a <101> on the mode pi (M2, M1, M0). Configuation Sequence The configuation of Vitex devices is a thee-phase pocess. Fist, the configuation memoy is cleaed. Next, configuation data is loaded into the memoy, and finally, the logic is activated by a stat-up pocess. Configuation is automatically initiated on powe-up unless it is delayed by the use, as descibed below. The configuation pocess may also be initiated by asseting P- AM. The end of the memoy-cleaing phase is signalled by INIT going High, and the completion of the entie pocess is signalled by asseting DNE. Delaying Configuation Configuation of the FPA can be delayed by holding the PAM pin Low until the system is eady fo the device to configue. Duing the memoy cleaance phase, the configuation sequences continuously cycles though the configuation memoy cleaing all addesses. This activity continues until the completion of one full addess cycle afte the PAM pin goes High. Thus, configuation is delayed by extending the memoy cleaance phase. 18 ctobe 20, 1998 (Vesion 1.0)

19 Altenatively, INIT can be held Low using an open-dain dive. An open-dain is equied since INIT is a bidiectional open-dain pin that is held Low by the FPA while the configuation memoy is being cleaed. Extending the time that the pin is Low causes the configuation sequence to act as if the configuation memoy is still being cleaed. Thus, configuation is delayed by peventing enty into the phase whee data is loaded. Stat-Up Sequence The default Stat-up sequence is that one CCLK cycle afte DNE goes High, the global ti-state signal (TS) is eleased. This pemits device outputs to tun on as necessay. ne CCLK cycle late, the lobal Set/eset (S) and lobal Wite Enable (WE) signals ae eleased. This pemits the intenal stoage elements to begin changing state in espoe to the logic and the use clock. The elative timing of these events may be changed. In addition, the TS, S, and WE events may be made dependent on the DNE pi of multiple devices all going High, focing the devices to stat in synchonism. The sequence may also be paused at any stage until DLL lock has been achieved. Data Steam Fomat Vitex devices ae configued by sequentially loading fames of data.that have been concatenated into a bitsteam. Table 12 lists the total numbe of bits equied to configue each device. Table 12: Vitex Bit-steam Lengths Device eadback # of Configuation Bits XCV50 559,232 XCV ,248 XCV150 1,041,128 XCV200 1,335,872 XCV300 1,751,840 XCV400 2,546,080 XCV600 3,608,000 XCV800 4,715,584 XCV1000 6,127,772 The configuation data stoed in the Vitex configuation memoy can be eadback fo veification. Along with the configuation data it is possible to eadback the contents all flip-flops/latches, LUTAMs, and block AMs. This capability is used fo eal-time debugging. Fo a detailed desciption, see the Supplementay Desciption on Configuation and eadback. ctobe 20, 1998 (Vesion 1.0) 19

20 Vitex 2.5 V Field Pogammable ate Aays Pin Definitio Table 13: Special Pupose Pi Pin Name Dedicated Pin Diection Desciption CK0, CK1, CK2, CK3 Yes Input Clock input pi that connect to lobal Clock Buffes. These pi become use inputs when not needed fo clocks. M0, M1, M2 Yes Input Mode ae pi used to specify the configuation mode. CCLK Yes Input o utput The configuation Clock I/ pin: it is an input fo SelectAM and slave-seial modes, and output in maste-seial mode PAM Yes Input Initiates a configuation sequence when asseted Low. DNE Yes utput Indicates that configuation loading is complete, and that the stat-up sequence is in pogess. INIT No Bidi (open-dain) When Low, indicates that the configuation memoy is being cleaed. The pin becomes a use I/ afte configuation. BUSY/ DUT D0/DIN, D1, D2, D3, D4, D5, D6, D7 No utput In SelectMAP mode, BUSY contols the ate at which configuation data is loaded. The pin becomes a use I/ afte configuation unless the SelectMAP pot is etained. In bit-seial modes, DUT povides peamble and configuation data to dowteam devices in a daisy-chain. The pin becomes a use I/ afte configuation. No Input In SelectMAP mode, D0-7 ae configuation data input pi. These pi become use I/s afte configuation unless the SelectMAP pot is etained. In bit-seial modes, DIN is the single data input. This pin becomes a use I/ afte configuation. WITE No Input In SelectMAP mode, the active-low Wite Enable signal. The pin becomes a use I/ afte configuation unless the SelectMAP pot is etained. CS No Input In SelectMAP mode, the active-low Chip Select signal. The pin becomes a use I/ afte configuation unless the SelectMAP pot is etained. TDI, TD, TMS, TCK Yes Mixed Bounday-scan Test-Access-Pot pi, as defined in IEEE DXN, DXP Yes N/A Tempeatue-seing diode pi. (Anode: DXP, Cathode: DXN) V CCINT Yes Input Powe-supply pi fo the intenal coe logic. V CC Yes Input Powe-supply pi fo the output dives (subject to banking ules) V EF No Input Input theshold voltage pi. Become use I/s when an extenal theshold voltage is not needed (subject to banking ules). ND Yes Input ound 20 ctobe 20, 1998 (Vesion 1.0)

21 Vitex DC Chaacteistics Definition of Tems Data sheets may be designated as Advance o Peliminay. The status of specificatio in these data sheets is as follows: Advance: Initial estimates based on simulation and/o extapolation fom othe speed gades, devices, o families. Values ae subject to change. Use as estimates, not fo poduction. Peliminay: Based on peliminay chaacteization. Futhe changes ae not expected. Unmaked: Data sheets not identified as eithe Advance o Peliminay ae to be coideed final. All specificatio ae epesentative of wost-case supply voltage and junction tempeatue conditio. The paametes included ae common to popula desig and typical applicatio. Fo design coideatio equiing moe detailed infomation, see the appopiate family supplements available on the Xilinx WEBLINX at All specificatio ae subject to change without notice. Vitex Absolute Maximum atings Symbol Desciption Units V CCINT Supply voltage elative to ND -0.5 to 3.0 V V CC Supply voltage elative to ND -0.5 to 4.0 V V EF Input efeence Voltage -0.5 to 3.6 V V IN Input voltage elative to ND, diffeential inputs -0.5 to 3.6 V V IN Input voltage elative to ND, othe pi -0.5 to 5.5 V V TS Voltage applied to 3-state output -0.5 to 5.5 V V CC Longest Supply Voltage ise Time fom 1 V to 3V 50 ms T ST Stoage tempeatue (ambient) -65 to +150 C T SL Maximum soldeing tempeatue (10 1/16 in. = 1.5 mm) +260 C Junction tempeatue Ceamic packages +150 C T J Plastic packages +125 C Notes: Stesses beyond those listed unde Absolute Maximum atings may cause pemanent damage to the device. These ae stess atings only, and functional opeation of the device at these o any othe conditio beyond those listed unde peating Conditio is not implied. Exposue to Absolute Maximum atings conditio fo extended peiods of time may affect device eliability. Vitex ecommended peating Conditio Symbol Desciption Min Max Units V CCINT Supply voltage elative to ND, T J = -40 C to +100 C Industial 2.5-5% % V Supply voltage elative to ND, T J = 0 C to +85 C Commecial 2.5-5% % V V CC Supply voltage elative to ND, T J = -40 C to +100 C Industial 3.6 V Supply voltage elative to ND, T J = 0 C to +85 C Commecial 3.6 V T IN Input signal taition time 250 Notes: Coect opeation is guaanteed with a minimum V CCINT of 2.25 V (Nominal V CCINT -10%). Below the minimum value stated above, all delay paametes incease by 3% fo each 50-mV eduction in V CCINT below the specified ange. At junction tempeatues above those listed as peating Conditio, all delay paametes incease by 0.35% pe C. Input and output measuement theshold is ~50% of V CC. ctobe 20, 1998 (Vesion 1.0) 21