System-on-Chip Design

Transcription

1 System-on-Chip Design Embedded System Design Challenges Pierre Boulet DaRT project-team Master recherche informatique

2 Embedded System Design Challenges Definition and Significance System-on-Chip Today Main Challenges on Design Some Answers Overview of the Course

4 Definition What is an embedded system? system set of components needed to perform a function hardware + software +... embedded main function not computing usually not autonomous usually computer inside a system specific purpose submitted to constraints

5 Examples very small electronic tags smartcards microcontrollers washing machine, microwave oven,... computer peripherals keyboard hard drive controller more complex controllers digital camera automotive air bags, ABS,... ESB, engine control,...

6 Examples continued communications mobile phones network routers, modems software radio multimedia set-top boxes cable, satellite TV HDTV, DVD players video games radar, sonar

7 Market Significance huge market estimation 2002 (VDC) : > 1.7 billion units estimation 2003 (VDC) : $760 million for embedded software number of HW and SW developpers increases becomes more important than general purpose computing number of units already number of developpers in a few years

8 term Years, and at three-year (node) intervals thereafter, called the Long-term years (2012, 2015, 2018), while retaining the previous 2001 ITRS long-term columns for ease of comparison and to retain the tracking of the three-year Technology cycle nodes. Trends 2003 ITRS Technology Trends - 1/2 Pitch 1000 DRAM 1/2 Pitch - Node Technology Node - DRAM Half-Pitch (nm) year Node Cycle hp90 3-year Node Cycle hp65 hp45 hp32 MPU M1 1/2 Pitch hp Year 2003 ITRS Period: Near-term: ; Long-term: Figure ITRS Half Pitch Trends

9 Generations 46 Overall Roadmap Technology Characteristics Table 1i High-Performance MPU and ASIC Product Generations and Chip Size Model Near-term Years Year of Production Technology Node hp90 hp65 DRAM ½ Pitch (nm) MPU/ASIC Metal 1 (M1) ½ Pitch (nm) MPU/ASIC ½ Pitch (nm) (Un-contacted Poly) MPU Printed Gate Length (nm) MPU Physical Gate Length (nm) Logic (Low-volume Microprocessor) High-performance Generation at production ** p03h -- p05h -- p07h -- p09h Functions per chip (million transistors) ,106 1,393 1,756 Chip size at production (mm 2 ) High-performance MPU Mtransistors/cm 2 at production (including on-chip SRAM) ASIC ASIC usable Mtransistors/cm 2 (auto layout) ASIC max chip size at production (mm 2 ) (maximum lithographic field size) ASIC maximum functions per chip at production (Mtransistors/chip) (fit in maximum lithographic field size) ,020 1,286 1,620 2,041 2,571 3,239

10 Design Productivity Gap Reuse r / day Moore s Law Engineering Productivity Productivity Gap Schematic Capture Logic Synthesis Design Reuse System Verification Behavioral Compilers 1980 productivity gap e opportunity to define a Conclusion

12 System-on-Chip definition (nearly) complete embedded system on a single chip usualy includes programmable processors memory accelerating function units I/O software

13 4 Technology System Drivers Integration Figure 9 SOC MULTI-TECHNOLOGY First Integration of Technologies in SOC with Standard CMOS Process The need to build heterogeneous systems on a single chip is driven by such considerations as cost, form-factor, connection speed/overhead, and reliability. Thus, process technologists seek to meld CMOS with MEMS, and other sensors. Process complexity is a major factor in the cost of SOC-MT applications, since more technologies assembled on a single chip requires more complex processing. The total cost of processing is difficult to predict for future new materials and combinations of processing steps. However, at present cost considerations limit the number of technologies on a given SOC: processes are increasingly modular (e.g., enabling a flash add-on to a standard low-power logic process), but the modules are not generally stackable. Figure 9 shows how first integrations of each technology within standard CMOS processes not necessarily together with other technologies, and not necessarily in volume production might

14 SoC Examples Canon Digic processor family image processor improved quality, power consumption, speed, cost STI Cell Sony+Toshiba+IBM aim at several TFlops at 65nm integration one PowerPC + 8 SIMD units TI OMAP platform dedicated to 2.5G and 3G mobile phones / PDA

15 STI Cell http: //

16 OMAP 9 Typical application using the OMAP1612 device Emulator Pod TNETw1130 Compact FLASH FLASH NAND FLASH GPS Fast IrDA Debug Messaging Serial JTAG/ Emulation I/F High Speed WLAN a/b/g EMIF/CF Mobile DDR UART/IrDA OMAP1612 I 2 C Keypad GPIO I 2 C Peripheral Keypad GPIO LPG LED BRF6100 Bluetooth Data TCS4105 TCS2100 TCS2010 Modem Chipset Voice Voice Control Data UART MCSI MCSI UART McBSP TMS320C55x DSP ARM926 Shared Memory Controller/DMA 2D Graphic Accelerator Timers, Interrupt Controller, RTC Frame Buffer/Internal SRAM (2 MBit) LPG PWT EMT9 Camera I/F Memory Stick MMC-SD Memory Stick MMC-SD HDQ/1Wire LED Buzzer Debugger CMOS Sensor Memory Stick Card, MMC-SD Card Memory Stick Card, MMC-SD Card Battery µwire McBSP Security: SHA-1/MD5 DES/3DES RNG USB OTG LCD Controller PWL Clock and Reset Mgt. 12 MHz 32 khz Reset TSC2301 TLC320AIC23 Audio CodecAudio Touch Screen Controller Audio Amplifier Client Host Liquid Crystal Display LCD Light Controller Audio In/Out ARM Peripherals Baseband Peripherals Shared ARM and DSP Peripherals Dedicated Ports

17 Layout densities for memory and logic fabrics are the same as for the MPU driver, with edram density assumed to be 3 SRAM density. Requirements Maximum on-chip clock frequency is approximately for 5 10% PDA of the MPU clock SOC-LP frequency at each node. Peak power dissipation is limited to 0.1 W at C, and standby power to 2.1 mw, due to battery life. Table 9 System Functional Requirements for the PDA SOC-LP Driver YEAR OF PRODUCTION Process Technology (nm) Supply Voltage (V) Clock Frequency (MHz) Application (maximum required performance) Still Image Processing Real Time Video Codec (MPEG4/CIF) Real Time Interpretation Application (other) Web Browser TV Telephone (1:1) TV Telephone (>3:1) Electric Mailer Scheduler Voice Recognition (Input) Authentication (Crypto Engine) Voice Recognition (Operation) Processing Performance (GOPS) Required Average Power (W) Required Standby Power (mw) Battery Capacity (Wh/Kg) SOC TRENDS SOC presents Design, Test, PIDS and other areas with a number of technology challenges, such as development of reusable analog IP. The most daunting SOC challenges are: design productivity improvement of > 100% per node, with needs including platform-based design 7 and integration of programmable logic fabrics (Design), 8 management of power especially for low-power, wireless, multimedia applications (Design, PIDS), system-level integration of heterogeneous technologies including MEMS and optoelectronics (PIDS, FEP, Design), and development of SOC test methodology, with needs including test reusability and analog/digital BIST. Since SOC is aimed at low-cost and rapid system implementation, and since power is one of the grand challenges in

19 Technology Challenges for SoC Design design productivity increase main challenge need >100% increase per technology node management of power especially for low-power, wireless, multimedia applications system-level integration of heterogeneous technologies development of SoC test methodology

20 Design Productivity Growth Target Design Freedom 100% of Design Productivity Improvement 90% % 70% 60% New Circuit Rat io Reuse Circuit Rat io Target Design Resource % 40% % % 10% % - 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% Memory Percentage

21 Logic vs Memory Insufficient (42% Per Node) Design Produc with Different Rates of Productivity Improvement 100% 90% 90% 80% 80% 70% 70% 60% Logic Area Content (%) 60% 50% 40% 30% Prod. 10% per node Prod. 50% per node Prod. 100% per node Prod. 200% per node 50% 40% 30% 20% 20% 10% 10% 0% Year 0% 0% 10%

22 2 Design SoC Design Cost Model $100,000,000,000 $10,000,000,000 In house P&R Tall Thin Engineer Small Block Reuse Large Block Reuse IC Implementation tools Intelligent Testbench ES Level Methodology Very Large Block Reuse $1,000,000,000 Total Design Cost $100,000,000 20,1 52, ,769,273 R TL Methodology Only W ith A ll Future Improvem ents $10,000, Year Figure 13 Impact of Design Technology on SOC LP-PDA Implementation Cost This chapter first presents silicon complexity and system complexity challenges, followed by five crosscutting challenges (productivity, power, manufacturing integration, interference, and error tolerance) that permeate all DT areas. The bulk of the chapter then sets out detailed challenges according to a traditional landscape of DT areas (see Figure 14): design process; system-level design; logical, circuit and physical design; design verification; and design test. 1 These challenges are discussed at a level of detail that is actionable by management, R&D, and academia in the target supplier community,

23 Design Cost Problem economy will limit the semiconductor industry before the end of Moore s law today design time 30% design 70% verification/test

24 Complexity Challenge silicon complexity impact of process scaling and new materials and architectures previously ignorable phenomena now have impact system complexity reuse verification and test cost-driven design optimization embedded software design reliable implementation platforms design process management together: superexponentially increasing complexity of the design process

25 Methodology Precepts ITRS exploit reuse evolve rapidly avoid iteration replace verification by prevention improve predictability orthogonalize concerns expand scope unify

27 Reuse IP IP = Intellectual Property HW or SW block designed for reuse need of standards (VSIA) platform based SoC design organized method to reduce cost and risk by heavy reuse of HW and SW IPs steps in reuse block IP integration architecture

28 Raising the Abstraction Level ESL (Electronic System Level) from RTL to TLM or higher from VHDL to SystemC to UML HW/SW co-design need new tools consider the whole system large optimization potential combination of formal, semi-formal and non formal techniques

29 Figure 10 shows the bottom-up lower bound for total chip power at an operating temperature of 100 C, assuming that all logic is implemented with LOP or LSTP devices and operates as described in Footnote 25. We say that this is a lower bound since in practice some logic would need to be implemented with faster, higher-current devices. The figure suggests that SOC-LP power levels will exceed the low-power requirements of the PDA application, and further provides a breakdown of power contributions for each case. As expected, LOP power is primarily due to standby power dissipation while LSTP power is primarily due to dynamic power dissipation 10. Total chip power using only LOP devices reaches 1.39 W in 2018, mostly due to a sharp rise in static power after Total chip power using only LSTP devices reaches Lower Bound for Fixed Chip Size 1.27 W in 2018; almost all of this is dynamic power. Other Problem: Power Consumption 1.60 Power Trend Dynamic Power LOP (W) - Dynamic Power LSTP (W) Static Power LOP (W ) Power (W) Static Power LSTP (W) - Memory Power LOP (W) Memory Power LSTP (W) Power for LOP Bottom-Up (W) - Power for LSTP Bottom-Up (W ) Year

30 Power Consumption power consumption model αcv dd 2 f + I off V dd necessary improvement of power management (in 2016) reduction by 20 for dynamic power reduction by 800 for standby power one possible direction: exploit parallelism allows to decrease f and thus decrease Vdd

31 Summary challenge of SoC design more complex faster cheaper more reliable with lower power consumption how to handle the complexity?

32 References International Technology Roadmap for Semiconductors Winning the SoC Revolution Experiences in Real Design Edited by Grant Martin & Henry Chang Kluwer Academic Publishers

34 Course Outline Embedded System Design Challenges (Pierre Boulet), 15 sept Codesign (Jean-Luc Dekeyser), 29 sept DaRT (Jean-Luc Dekeyser), 6 oct Models of Computation (Pierre Boulet), 13 oct MARTE UML profile (Pierre Boulet), 20 oct Model Driven Engineering (Anne Étien), 3 nov Validation (Abdoulaye Gamatié), 10 nov VHDL Synthezis (Philippe Marquet), 17 nov SystemC Simulation (Jean-Luc Dekeyser), 24 nov Applications (Jean-Luc Dekeyser et Frédéric Guyomarc h), 1 er déc

35 Course Evaluation research article synthezis exam