1 Simulation Practice and Theory 7 (1999) 107±123 Design and implementation of a hardware-in-theloop simulator for a semi-automatic guided missile system Kresimir Cosic, Ivica Kopriva *, Todor Kostic, Miroslav Slamic, Marijo Volarevic Institute for Defence Studies, Research and Development, Bijenicka 46, Zagreb, Croatia Received 1 July 1998; received in revised form 14 December 1998 Abstract Hardware in the loop (HIL) simulation based on modern digital signal processors is a coste ective technology for the design and evaluation of various sophisticated weapon and industrial systems. In this article a HIL simulation is presented through the very complex problem of modernisation of the semi-automatic command to line of sight (SACLOS) missile system. The presented examples illustrate the importance of the HIL simulation technology for the cost-e ective, non-destructive prototype development of such SACLOS systems. The key role of a exible simulation platform consisting of 4 TMS320C40 digital signal processors for ef- cient real-time simulation of the implemented SACLOS subsystem models is also emphasised in this paper. Ó 1999 Elsevier Science B.V. All rights reserved. Keywords: Hardware in the loop simulation; Semi-automatic guided missile system; Digital signal processors; Parallel processing 1. Introduction Hardware-in-the loop (HIL) simulation has been proven as a cost-e ective method in design, development, modi cation and testing of a various sophisticated weapon and industrial systems. Developed primarily for military [1,2,12] and space  applications, HIL technology was historically based on the expensive vector computers such as AD 100 [1,2,12] or even the Cray-type supercomputers. The main bene t * Corresponding author /99/$ ± see front matter Ó 1999 Elsevier Science B.V. All rights reserved. PII: S ( 9 8 )
2 108 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107±123 of the HIL technology is repeatable non-destructive and non-hazardous prototype testing, veri cation and validation. This makes it of interest to industrial applications, primarily for the automotive industry [3,4,6,10,14]. The main event that enabled the transfer of the HIL technology into the industrial area was the development of cost-e ective, computationally powerful microprocessors. In particular, digital signal processors (DSPs) with advanced capabilities necessary for e cient multiprocessor real-time simulations. Examples of such processors are the Texas Instruments (TI) DSPs TMS320C30/C40 [5,11,14]. The HIL simulation based on general-purpose microprocessors for applications of lower complexity levels have also been reported . The main objective of this paper is to report about the hardware and software structure of a HIL simulator designed and implemented in order to facilitate development, modi cation and testing of various prototype modules in semi-automaticcommand-to-line-of-sight (SACLOS) missile systems. In Section 2, a general mathematical model of the SACLOS system is described. The functional decomposition of the system is based on the logically connected physical subsystems. This allows easier multiprocessor model implementation of the various HIL simulation scenarios, as well as better insight in possibilities for the system modernisation. The hardware and the software structure of the HIL simulator is described in Section 3. The reasons for using a multiprocessor board, consisting of 4 TI TMS320C40 DSPs, are pointed out. The basic description of the special purpose A/D and D/A subsystem, signal interface and user interface is also given in this section. The details related to the implementation of the SACLOS system and the results of the several interesting simulation scenarios are discussed in Section 4. Conclusions are given in Section SACLOS system description SACLOS guidance is one approach to control anti-tank missiles in the short to medium range engagements. In SACLOS systems the operator's task is only to keep pointing tracking telescope to the target establishing a line-of-sight (LOS) between the launching unit and the target. In the LOS guidance scheme, shown in Fig. 1, the missile is automatically guided on a LOS course in an attempt to remain on a line joining the target and the point of control. The missile infrared (IR) goniometer is mounted alongside the operator's tracking telescope and is collimated to it. While operator tries to keep LOS pointing at the target, the goniometer generates pitch/yaw signals proportional to the missile's (IR missile tracker) displacement from the optical LOS, i.e. the guidance system error. In response to these signals, the automatic guidance system produces acceleration commands, which are sent to the missile via a wire link. In response to these, the missile then accelerates in such a way as to remain on the LOS, i.e. to keep guidance error e acceptably small. The acceleration commands sent to the missile are de ned in Cartesian (pitch and yaw) co-ordinate system. These commands have to be transformed to the `body- xed' co-ordinates for two pairs of n control. Missile roll attitude (/) is sensed
3 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107± Fig. 1. Semi-automatic CLOS guidance system. using a gyroscope with a lamellas transformer for distributing guidance signals to the pair of control ns Mathematical models SACLOS guidance typically includes an up-link to transmit guidance signals from a ground controller to the missile. A basic block diagram of the SACLOS guidance scheme for a rotating missile is shown on Fig. 2. Fig. 2. SACLOS guidance block diagram.
4 110 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107±123 The six degrees of freedom (6DOF) mathematical model of the missile's dynamics is a non-linear model of a ying `rigid body' object. The general translation and rotation vector di erential equations of the ying objects are as follows: m dv ~V dt ˆ ~F F a F~F t G; 1 I dh ~H dt ˆ M ~M a M~M t ; 2 where V ˆ uvwš T is the velocity vector, F a ˆ XYZŠ T the vector of the aerodynamic T force, F t ˆ F x F y F z the thrust vector, G the gravitational force, m the mass of the body, I the tensor of the inertia, H the angular momentum, M a ˆ LMNŠ T the vector of the aerodynamic moment and M t ˆ L F M F N F Š T the vector of the thrust moment. Eqs. (1) and (2) are de ned in the missile's axis system. For a complete mathematical model of the SACLOS guidance system it is necessary to add equations of the SACLOS guidance law and command forming units, rotating missile control and actuator dynamics as well as the kinematics relations. Thus, the controls of forces and moments have to be added to the right side of Eqs. (1) and (2), respectively. In order to establish the relations between the missile and the target, transformations from the missile's or dynamical (D) co-ordinate to the spherical command point co-ordinate system (C) L CD have to be used . 2 3 _R 4 R k _ M cosu 5 M ˆ L CD V ; 3 R _u M where R is distance from the command point to the centre of the missile mass, k M the missile angle in the horizontal plane and u M the missile angle in the vertical plane. Eq. (3) represents the geometric (kinematics) model. The matrix of transformation can be expressed as a function of the missile attitude angles (Euler's angles /; w; #) or alternatively by use of quaternion ± parameters (e 0, e 1, e 2, e 3 ). These quaternions can be computed directly from dynamics Eq. (2), bypassing the computation of transcendental functions needed for computing the Euler angles. In the case when the components of the angular velocities are known in the body co-ordinate system, parameters (e 0, e 1, e 2, e 3 ) T are de ned by di erential Eq. (4)  _e 0 e 1 e 2 e _e 1 7 _e 2 5 ˆ 1 e 0 e 3 e 2 p e 3 e 0 e 1 5 q 5 4 r _e 3 e 2 e 1 e 0 with, e 2 0 e2 1 e2 2 e2 3 ˆ 1 5 The four variables e 0 ; e 1 ; e 2 and e 3 coupled by means of Eq. (5), uniquely describe the orientation of the missile in space.
5 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107± A SACLOS guidance law can be described with a very simple model such as a proportional-integral-derivative regulator or with very complex description based on the non-linear inverse dynamics including di erent compensation forms which would o er potential modernisation of the existing guidance subsystem. The guidance controls expressed in the non-rotating co-ordinate system are transformed to the rotating co-ordinate system using Eq. (6). U 1 ˆ f 1 / U 0 H f 2 / U 0 V ; U 2 ˆ f 1 / U 0 V f 2 / U 0 H ; 6 U 1 ; U 2 and UV 0 ; U H 0 are non-rotating and rotating guidance signals for two orthogonal planes respectively. / is the missile rotating angle, f 1 / and f 2 / are modulation functions written as: f 1 / ˆ 1 sgn cos/ sgn sin/ Š 2 f 2 / ˆ 1 sgn cos/ sgn sin/ Š 7 2 Each pair of the n actuators has a nite bandwidth so that, for simplicity, action of the e ective de ection angles can be modelled by a rst-order system with surface position saturation and rate saturation Missile localisation system ± IR goniometer In a number of SACLOS systems the missile position is detected by using an IR source, placed in the tail of the missile, in combination with a special electro-optical system, an IR goniometer, that is based on a rotating reticle which is also called a modulating disk , Fig. 3. The role of the system, which is based on the rotating reticle and photodetector with appropriate spectral response, is to determine missile position by detecting infrared energy emanating from the missile IR source and to suppress unwanted signals from the background . The rotating reticle modulates incident optical ux and is located at the focal plane of an optical imaging system. A photodiode detects the modulated optical signal, where modulating function s r; u; t is a function of the polar co-ordinates Fig. 3. IR goniometer for missile localisation.
6 112 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107±123 of the projection of the IR source on the modulation disk area and also a function of the reticle type. Here r stands for the modulus and u stands for the angle. For a reticle with fan-bladed pattern [15,9,19] the modulating function has the form: s r; u; t ˆ cos x 0 t b sin X M t u Š 8 which is a canonical representation of the frequency modulated (FM) signal, . b, x 0 and X M are functions of the IR source co-ordinates and the optical modulator construction constants. It can be shown, [9,19], that deviation of the FM signal Eq. (8), b, is directly proportional with the polar co-ordinate r. The role of the FM discriminator, see Fig. 3, is to demodulate the FM signal Eq. (8). The amplitude of the demodulated signal will be directly proportional with the r coordinate while the phase will represent the u co-ordinate. By providing external phase reference, the demodulated signal is transformed at the synchronous detector from polar to Cartesian co-ordinates. In reference to Fig. 2, it must be observed that the FM signal Eq. (8) has a much wider spectral bandwidth than all the other signals in the guidance and control loop. Depending on the amount of maximal missile displacement r, the e ective signal bandwidth can be as large as 50 khz, which will in uence the design of the signal interface discussed in Section 3.2. The process of FM signal demodulation as well as synchronous detection can be carried out digitally. This is one important aspect of the SACLOS system modernisation. By application of the HIL simulation the new digital solution can be tested and veri ed with a real electro-optical system included in the closed guidance loop. Furthermore, since the described type of missile localisation system is sensitive to certain types of IR jamming , new advanced signal processing methods  can be applied and tested in order to increase the IR jamming margin. The research and development in this eld would be practically impossible to carry out without extensive use of the HIL simulation technology. 3. Hardware and software structure of the implemented HIL simulator The main part of the HIL simulator is an industry PC chassis containing a standard Pentium 200 MHz motherboard, a multiprocessor PC board for digital signal processing and two PC boards with I/O subsystem. The host processor (Pentium) is used for code developing and downloading to the target DSP board, and for both simulation control and output data analysis. This HIL simulator is primarily intended for laboratory testing and development purposes, thereby requiring some adaptation of the SACLOS system optics, designed for distances between 100 and 2000 m. With a small lens attached to the optics of the SACLOS launching unit real focus distance is corrected to a laboratory distance of 8 m between the launching unit and a plotter. A high-speed (compared to the missile dynamics) A3 plotter with a light emitting diode (LED) of appropriate
7 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107± Fig. 4. Hardware structure of the HIL simulator. spectrum is used as a low cost emulation of the moving missile's IR source. Information about actual co-ordinates of such an IR spot in relation to LOS is produced by a 6DOF missile model and sent to the plotter's analog inputs. A custom signal interface between the real hardware of the SACLOS system's launching unit and simulator's I/O subsystem also had to be designed. This hardware structure (Fig. 4) makes a closed guidance and control loop (IR spot ± launcher optics ± launcher hardware ± simulator models ± 6DOF missile model ± IR spot co-ordinates), and provides platform for a realistic and modular testing as well as for a partial development and modi cations of the SACLOS systems DSP board with four TMS320C40 The main processing unit of this simulator is a single PC board that carries four TIM 40 modules , each with one TMS320C40 digital signal processor  and three 32 kword RAM blocks (see Fig. 5). The C40 processor has six communication (COM) ports, each with assigned direct memory access (DMA) coprocessor. The COM ports, that are essential for modular structure and inter-processor communication are brought to the end-plate connectors. The communication with the PC host processor is handled via Link Interface Adapter, and development debugging via JTAG standard connector. All processors use the same clock generator, and their execution can be controlled through the userde ned interrupt status ags. The whole system has a performance of 1 GOPS operating on a 50 MHz clock.
8 114 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107±123 Fig. 5. QPC/C40B multiprocessor PC board with four TIM modules. The COM ports are connected in each-to-each-other mode that o ers maximum exibility for data-exchange and for implementation of the simulation models, which due to the di erent HIL simulation scenarios require modi cations of the simulation structure. This modularity and exibility of the multiprocessor platform makes the functional decomposition of a real system transparent to the simulation hardware, thereby reducing the complexity of implementation and context switching between di erent scenarios in a complex HIL simulation. One port from each processor is connected to LIA connector, thereby enabling direct communication between the host and each signal processor. This provides facility for code and data downloading, as well as for exchange of data and control parameters during or after simulation process. Inter-processor communication is carried out through DMA channels, enabling asynchronous high-speed data transfer. Each DMA channel is virtually divided in two channels (split mode) through which data exchange between simulation models, i.e. corresponding processors, is carried out (Fig. 6). All necessary data are exchanged between pre-assigned memory locations, concurrently with the execution of the main program (see Fig. 6). This construction provides a platform for a smooth communication between simulation models that are discretized with various periods, since high-speed data exchange is carried out by DMA completely independent from their execution. If, for example, model A with a shorter deadline sends data to a slower model B (longer deadline, i.e. discretization period), model B uses the newest data from the memory, i.e. the most recently received. On the other hand, if a model B is faster, prediction with data extrapolation can be done according to the memory record of the two-three or more previously received data. This provides updated data for
9 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107± Fig. 6. Asynchronous communication model. each step of the faster model execution, instead of using the same data from the slower model a number of times. This feature is of essential importance for e cient multi-rate real time simulation of complex dynamic systems  such as the SACLOS system described in Figs. 1 and 2 and by Eqs. (1)±(8), when deadlines of each implemented model are functions of the dynamics of the correspondent physical subsystem. Determinism of the whole simulation is maintained by using user-de ned status ags for synchronisation and simultaneous execution start of all models together using the distance counter start signal that comes from the SACLOS launching unit I/O card and signal interface From Fig. 4 it is clear that the design of a custom signal interface was necessary in order to connect the HIL simulator with various types of analog signals that exist at the appropriate connection points of the real SACLOS equipment. Depending on the chosen HIL simulation scenario di erent types of analog signals must be converted to the digital domain and vice versa. The main roles of the signal interface design are: to adjust voltage range of the selected signals to the voltage range of the A/D and D/A converters; to transform signals from di erential to single-ended formats and vice versa; to electronically isolate appropriate physical subsystems which are simulated or not used from the other physical subsystems that are included in the selected HIL simulation scenario. It is clear from the previous discussion that besides the signal interface, special care had to be paid to the I/O (i.e. A/D and D/A) subsystem. Since e ective signal spectra vary from several tens of Hz (guidance signal and missile position signals) to almost 50 khz (FM signal produced by the electro-optical subsystem) a very wide range of conversion speeds was necessary. When the FM signal is digitised, phase linearity of the antialiasing lter is required in order to synchronise the discriminated signal with the external phase reference signals. Therefore, a RD type of A/D converter had to be used with a digitally realised over-sampled FIR antialiasing lter. Since a half of a RD converter sampling frequency is 32
10 116 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107±123 khz, and maximum frequency of the sampled FM signal is around 29 khz, no analog antialiasing lter with maximally at group delay could meet such a narrow transition band requirements. The ratio between the required minimal and maximal conversion speeds was approximately 1 : Since, in a case of RDA/D converters, sampling frequency can vary with a typical ratio of 1 : 10 between minimal and maximal sampling frequency, it was possible to cover the conversion range between approximately 10k samples and 100k samples. Another type (successive approximation) of A/D converters was necessary for the low conversion speeds covering range from 100 samples to 20k samples. Consequently, the I/O card consists of two 12-bit successive approximation type of A/D converters, two 16-bit RDtype of A/D converters and four D/A converters with appropriate pre- and post- lters. Each pair of A/D and D/A converters is connected with its own TMS320C40 signal processor on the processor board. Consequently, two of the six communication channels on each processor are devoted to the communication with the analog world. Con guration of the A/D and D/A channels as well as the data format conversions is performed by programmable logic (ALTERA 128 cells EPLD chip). Since it was very di cult to nd such A/D and D/A card on the open market it also had to be designed to complete the HIL simulator User-interface and software support Software support includes Texas Instruments C40 Compiler, Assembler, and Linker  together with DB40 debugger and C40 API support . In order to facilitate the various phases present in a complex HIL simulation scenarios, a graphical user interface called `TMS320C40 integrated development environment' (IDE) has been built (Fig. 7). It integrates all the previously mentioned software packages with many additional options. This IDE is user-friendly windows environment, written in Microsoft Visual C/ C++, and enables writing, compiling, debugging and running of code. All settings for incorporated software can be made through windows box checks. The basic IDE appearance is very much alike the common C/C++ environment. Code is supposed to be written and tested for each processor independently, but it can be run on a single processor or as a package for all four processors. All of the six simulation modes, and one custom mode can be de ned in the `Multiple run' window shown on Fig. 7. In this window the user can specify which model to run on which processor (according to the desired simulation mode) and also to specify where to store the control data and the simulation parameters. The data format can be also speci ed (hexadecimal, integer, oating-point). After pressing the OK button, the code for all four processors will be downloaded, and prepared for synchronous start. Then synchronisation of code execution on all four processors is provided by START signal driven by the launching unit's trigger (start of the launching process), or from the button on I/O interface for testing purposes. This environment fully supports all features and modes of this HIL simulator, and also provides an easy-to use GUI for all users. Some features of the IDE itself
11 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107± Fig. 7. IDE graphical user interface outlook. were not previously implemented, even by the software support manufacturer. For example windows settings and execution with message boxes for the TI C40 Compiler, assembler and linker as well as windows support for using LSI's API libraries HIL simulation results As already pointed out in the second section, two main candidates for the possible modernisation of the described SACLOS system are the missile localisation subsystem (IR goniometer) and the guidance subsystem (see Fig. 2). Based on the layout shown in Fig. 2, complex mathematical models of the three subsystems had to be implemented on the DSP platform in order to perform the related HIL simulation. These are the 6DOF model of missile dynamics; the SACLOS guidance law with the command forming unit and the FM discriminator and synchronous detector. Details related to the TMS320C40 implementation of each of these models are given in Table 1. Deadline times are equal to the discretization periods of each model, determined by a model's dynamics, and must be met during simulation to maintain hard real-time constraints. Execution times are actual times required by the TMS320C40 processor to pass the longest execution path of each model code.
12 118 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107±123 Table 1 Model Deadline time Execution time 6DOF model of missile dynamics C language 2 ms 0.6 ms Guidance law and command forming unit C language 2 ms 38 ls Digital co-ordinator (FM demodulator and synchronous detector) Assembly language 16 ls 14.7 ls Fig. 8 shows the physical mapping of these models on the QPC/C40B multiprocessor platform needed to perform the HIL simulation and to verify a new digital solution of the IR goniometer and guidance as well as the control subsystem. The FM discriminator and synchronous detector are placed on one processor ± DSP C in Fig. 8 under the name `digital co-ordinator'. The 6DOF model of missile dynamics is placed on DSP A, while the SACLOS guidance law and command forming unit are placed on DSP D, under the name `digital guidance system'. The main feature of this simulation scenario is that processing of the FM signal produced by the spatial light modulator (IR goniometer) as well as the synthesis of the guidance and command law, are performed in a digital manner. The FM signal demodulation described with Eq. (8) is performed by the quadrature signal processing techniques. Fig. 8. Physical implementation of the second HIL simulation scenario.
13 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107± The digital FM demodulator, in combination with the digital implementation of the synchronous detector, extracts the Cartesian co-ordinates of the IR source projection on the plane spanned by the modulation disk. The co-ordinates are de ned in relation to the centre of the modulation disk. On the basis of these co-ordinates, which represent instantaneous guidance error, guidance law and command forming units synthesise the command in order to reduce that guidance error. In this simulation scenario, synthesis of the guidance and command law is performed by simple digitisation of the existing analog control law, whereas in the missile localisation subsystem new algorithms were applied. The main feature of this version of the HIL simulation is exibility. It permits future modernisation of the SACLOS system by developing new guidance and control laws as well as by enhanced signal processing methods related to an increasing IR anti-jamming capability . The instantaneous guidance error relative to LOS in both vertical and horizontal plane is reported as a nal performance measure in Fig. 9. Acceptable error for typical SACLOS system varies from 1.5 m in vertical plane and 1 m in horizontal plane in the beginning phase of the missile ight to 0.5 m in both planes in the active phase of the missile ight (i.e. with declared hit probability, 500±2000 m). As can be seen from Fig. 9, in our simulation the guidance error in vertical plane after fourth second of ight exceeds declared 1 m diameter tunnel. This is caused by the inherent error related to the present laboratory environment. As discussed in Section 3, a correction of the optical focus from the real world target distance (800±2000 m for the second optical channel that becomes active after 4 s of ight) to the laboratory distance (8 m) had to be made. Attached lens has signi cant in uence to the magnitude of guidance error after fourth second, when the narrow eld of view (second channel) is in use, while it can't be ideally mounted orthogonal to the optical channel line. Therefore, the point source image is not correctly focussed in the centre of the optical channel, and causes an additional constant small angle error in vertical plane (in our example). Since the absolute error (in meters) is computed by multiplying the angle error and the distance to the missile, in uence of this additional error is constantly increasing. This type of error can be avoided by using dynamic collimator for simulating moving missile IR source. However, in relation to the described plotter based solution this would be an extremely expensive solution. Furthermore, since the reference simulation scenario that includes the analog IR goniometer and guidance subsystem is conducted under the same conditions, this type of error has no essential in uence on the applicability of the HIL simulation concept in SCALOS system modernisation. In that sense (related to the referent scenario), the reported simulation results of this simulation scenario are considered to be of acceptable accuracy. To illustrate the in uence of the errors introduced by performing experiments with the real electro-optical system, the another HIL simulation was performed. The real IR goniometer is modelled as memory-less linear system. The missile co-ordinates, that are inputs to the guidance law and command forming unit, are obtained by a simple scaling of the missile position obtained from the 6-DOF model of missile dynamics. Synthesis of the guidance and command law is performed in the digital domain in the same manner as in the basic HIL simulation scenario. The guidance
14 120 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107±123 Fig. 9. Guidance error in horizontal and vertical plane. error in vertical and horizontal plane is shown in Fig. 10. It can be seen that the instantaneous guidance error is inside the speci ed range. Moreover, direct comparison of the Fig. 9 shows that dynamic behaviour of the guidance error in the rst
15 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107± Fig. 10. Guidance error in horizontal and vertical plane. 4 s is very similar in both cases. After the fourth second, however, the discussed optical problems cause guidance error in rst HIL simulation scenario to exceed the expected range.
16 122 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107± Conclusion The design and implementation of the hardware-in-the-loop simulator for typical SACLOS missile system has been described. The basic structure of the SACLOS missile system has been brie y discussed and possibilities for system modernisation are pointed out. Special attention has been given to the role of the state-of-the-art simulation platform based on cost-e ective multiprocessor PC board, consisting of 4 TMS320C40 digital signal processors, in the e cient multi-rate real time simulation of such a complex dynamic system. Details related to the implementation of the simulation scenario signi cant for the modernisation of the SACLOS missile system as well as the main simulation results are also reported. Consequently, the importance of the HIL simulation technology to the modernisation phase of the discussed system has been clearly illustrated. It has been demonstrated how a HIL simulation approach based on a cost-e ective computational platform can reduce development costs related to a design of quite complex weapon system such as the described SAC- LOS missile system. References  McDonnell Douglas Corporation, AD-LIB An ADI Customer Newsletter 4 (1988) 1.  Rocketdyne Gets a Boost from ADI Simulation Systems, AD-LIB Customer Newsletter 4 (1988) 2.  Hardware-in-the-Loop Experiments at Hughes/GM FAST Facility Help Automobiles of the Future Take-O Fast, AD-LIB An ADI Customer Newsletter 5 (1989) 1.  Development of a Four Wheel Steering Controller at Honda, dspace News 4 (1995) 2.  Hardware-in-the-Loop Simulation Breakthrough: 300 MFLOPS Subsystem for Signal Generation, dspace News 3 (1994) 1.  First HIL-Testbench for Wheel Slip Control Installed at Audi, dspace News 4 (1995) 2.  G.F. Aroyan, The Technique of Spatial Filtering, in: Proceedings of the IRE, 1959, pp. 1561±1568.  P.P.J. Van Den Bosch, W. Jongkind, A.C.M. Van Swieten, Adaptive attitude control for large-angle slew manoeuvres, Automatica 22 (2) (1986) 209±215.  T.B. Buttweiler, Optimum modulation characteristics for amplitude-modulated and frequencymodulated infrared systems, J. Opt. Soc. Am. 51 (9) (1961) 1011±1015.  K. Cosic, I. Kopriva, I. Miler, Workstation for integrated system design and development, Simulation 58 (3) (1992) 152±161.  K. Cosic, I. Kopriva, T. Sikic, A methodology for digital real time simulation of dynamic systems using modern DSPs, Journal Simulation Practice and Theory 5 (2) (1997) 137±151.  S.L. Dunbar, R.W. Webbert, Hardware-in-the-Loop emulation of the semi-active Stinger (Scorpion) missile, in: Proceedings of the Summer Computer Simulation Conference, San Diego, CA, 1994, pp. 329±334.  B. Etkin, L.. Reid, Dynamics of Flight - Stability and Control, Wiley, New York,  N. Huang et al., Real-time simulation and animation of suspension control system using TI TMS320C30 digital signal processors, Simulation 59 (12) (1993) 405±416.  R.D. Hudson, Jr., Infrared System Engineering, Wiley, New York,  I. Kopriva, Adaptive blind separation of convolved sources based on minimisation of the generalised instantaneous energy, in: Proceedings of the IX European Signal Processing Conference, vol. II, Island of Rhodes, Greece, 1998, pp. 761±764.  C4x network API support, Loughborough Sound Images,  QPC/C40B TIM40 carrier board technical reference manual, Loughborough Sound Images, 1996.
17 K. Cosic et al. / Simulation Practice and Theory 7 (1999) 107±  A.F. Nicholson, Error signals and discrimination in optical trackers that see several sources, Proc. of the IEEE 53 (1) (1965) 56±71.  H. Taub, D.L. Schilling, Principles of Communication Systems, McGraw-Hill, New York,  TMS320C4x User's guide, Texas Instruments,  TMS320C40 Code Generation Tools-Assembler, Compiler, Linker, Texas Instruments, 1997.
Non-Data Aided Carrier Offset Compensation for SDR Implementation Anders Riis Jensen 1, Niels Terp Kjeldgaard Jørgensen 1 Kim Laugesen 1, Yannick Le Moullec 1,2 1 Department of Electronic Systems, 2 Center
Department of Electrical and Computer Engineering Ben-Gurion University of the Negev LAB 1 - Introduction to USRP - 1-1 Introduction In this lab you will use software reconfigurable RF hardware from National
VECTOR NETWORK ANALYZER PLANAR TR1300/1 DATA SHEET Frequency range: 300 khz to 1.3 GHz Measured parameters: S11, S21 Dynamic range of transmission measurement magnitude: 130 db Measurement time per point:
dspace DSP DS-1104 based State Observer Design for Position Control of DC Servo Motor Jaswandi Sawant, Divyesh Ginoya Department of Instrumentation and control, College of Engineering, Pune. ABSTRACT This
Implementation of Digital Signal Processing: Some Background on GFSK Modulation Sabih H. Gerez University of Twente, Department of Electrical Engineering email@example.com Version 4 (February 7, 2013)
Instruction Manual Service Program ULTRA-PROG-IR Parameterizing Software for Ultrasonic Sensors with Infrared Interface Contents 1 Installation of the Software ULTRA-PROG-IR... 4 1.1 System Requirements...
An inertial haptic interface for robotic applications Students: Andrea Cirillo Pasquale Cirillo Advisor: Ing. Salvatore Pirozzi Altera Innovate Italy Design Contest 2012 Objective Build a Low Cost Interface
RF Network Analyzer Basics A tutorial, information and overview about the basics of the RF Network Analyzer. What is a Network Analyzer and how to use them, to include the Scalar Network Analyzer (SNA),
International Journal of Scientific & Engineering Research, Volume 4, Issue 4, April-2013 262 DSP based implementation of a Configurable Composite Digital Transmitter Soumik Kundu, Amiya Karmakar Abstract
Accurate Measurement of the Mains Electricity Frequency Dogan Ibrahim Near East University, Faculty of Engineering, Lefkosa, TRNC firstname.lastname@example.org Abstract The frequency of the mains electricity supply
AUTOMATYKA/ AUTOMATICS 03 Vol. 7 No. http://dx.doi.org/0.7494/automat.03.7..87 Grzegorz Karpiel*, Konrad Gac*, Maciej Petko* FPGA Based Hardware Accelerator for Parallel Robot Kinematic Calculations. Introduction
(DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de email@example.com NIOS II 1 1 What is Nios II? Altera s Second Generation
Three Channel Optical Incremental Encoder Modules Technical Data HEDS-9040 HEDS-9140 Features Two Channel Quadrature Output with Index Pulse Resolution Up to 2000 CPR Counts Per Revolution Low Cost Easy
Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28 How to handle complexity G The engineering
ugrid Testbed. Rein in microgrid complexity. With ease. Outsmart the microgrid. ugrid Testbed Ultimate test solution for microgrid control system verification What is a microgrid? Microgrid is a collection
INTRODUCTION TO SERIAL ARM A robot manipulator consists of links connected by joints. The links of the manipulator can be considered to form a kinematic chain. The business end of the kinematic chain of
Time Domain and Frequency Domain Techniques For Multi Shaker Time Waveform Replication Thomas Reilly Data Physics Corporation 1741 Technology Drive, Suite 260 San Jose, CA 95110 (408) 216-8440 This paper
DDX 7000 & 8003 Digital Partial Discharge Detectors The HAEFELY HIPOTRONICS DDX Digital Partial Discharge Detector offers the high accuracy and flexibility of digital technology, plus the real-time display
G.1 EE1.el3 (EEE1023): Electronics III Mechanics lecture 7 Moment of a force, torque, equilibrium of a body Dr Philip Jackson http://www.ee.surrey.ac.uk/teaching/courses/ee1.el3/ G.2 Moments, torque and
Robot Task-Level Programming Language and Simulation M. Samaka Abstract This paper presents the development of a software application for Off-line robot task programming and simulation. Such application
A Master-Slave DSP Board for Digital Control ROSA, F. E. 1 ; CARRARA, A. R. S. 2 ; SOUZA, A.H. 3 (1) M.Sc. candidate e-mail firstname.lastname@example.org (2) Professor, Ph.D. e-mail email@example.com
Force/position control of a robotic system for transcranial magnetic stimulation W.N. Wan Zakaria School of Mechanical and System Engineering Newcastle University Abstract To develop a force control scheme
Design-Simulation-Optimization Package for a Generic 6-DOF Manipulator with a Spherical Wrist MHER GRIGORIAN, TAREK SOBH Department of Computer Science and Engineering, U. of Bridgeport, USA ABSTRACT Robot
DS1104 R&D Controller Board Cost-effective system for controller development Highlights Single-board system with real-time hardware and comprehensive I/O Cost-effective PCI hardware for use in PCs Application
AARMS Vol. 5, No. 2 (2006) 237 243 TECHNOLOGY Onboard electronics of UAVs ANTAL TURÓCZI, IMRE MAKKAY Department of Electronic Warfare, Miklós Zrínyi National Defence University, Budapest, Hungary Recent
35'th Annual Precise Time and Time Interval (PTTI) Systems and Applications Meeting San Diego, December 2-4, 2003 A PC-BASED TIME INTERVAL COUNTER WITH 200 PS RESOLUTION Józef Kalisz and Ryszard Szplet
Quick Assembly Two and Three Channel Optical Encoders Technical Data HEDM-550x/560x HEDS-550x/554x HEDS-560x/564x Features Two Channel Quadrature Output with Optional Index Pulse Quick and Easy Assembly
LabVIEW Based Embedded Design Sadia Malik Ram Rajagopal Department of Electrical and Computer Engineering University of Texas at Austin Austin, TX 78712 firstname.lastname@example.org email@example.com Abstract
A System for Capturing High Resolution Images G.Voyatzis, G.Angelopoulos, A.Bors and I.Pitas Department of Informatics University of Thessaloniki BOX 451, 54006 Thessaloniki GREECE e-mail: firstname.lastname@example.org
DDX 7000 & 8003 Digital Partial Discharge Detectors The HAEFELY HIPOTRONICS DDX Digital Partial Discharge Detector offers the high accuracy and flexibility of digital technology, plus the real-time display
Best Practises for LabVIEW FPGA Design Flow 1 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and
Óbuda University e Bulletin Vol. 2, No. 1, 2011 LEGO NXT-based Robotic Arm Ákos Hámori, János Lengyel, Barna Reskó Óbuda University email@example.com, firstname.lastname@example.org, email@example.com
COMPUTER HARDWARE Input- Output and Communication Memory Systems Computer I/O I/O devices commonly found in Computer systems Keyboards Displays Printers Magnetic Drives Compact disk read only memory (CD-ROM)
Synthetic Sensing: Proximity / Distance Sensors MediaRobotics Lab, February 2010 Proximity detection is dependent on the object of interest. One size does not fit all For non-contact distance measurement,
Control, University of Bath, UK, September ID- IMPACT OF DEPENDENCY AND LOAD BALANCING IN MULTITHREADING REAL-TIME CONTROL ALGORITHMS M A Hossain and M O Tokhi Department of Computing, The University of
Technical Information Encoders for Linear Motors in the Electronics Industry The semiconductor industry and automation technology increasingly require more precise and faster machines in order to satisfy
Fondamenti su strumenti di sviluppo per microcontrollori PIC MPSIM ICE 2000 ICD 2 REAL ICE PICSTART Ad uso interno del corso Elettronica e Telecomunicazioni 1 2 MPLAB SIM /1 MPLAB SIM is a discrete-event
Qiang Lu Chapter 3. System Scanning Hardware Overview 79 Chapter 3 SYSTEM SCANNING HARDWARE OVERVIEW Since all the image data need in this research were collected from the highly modified AS&E 101ZZ system,
REAL TIME 3D FUSION OF IMAGERY AND MOBILE LIDAR Paul Mrstik, Vice President Technology Kresimir Kusevic, R&D Engineer Terrapoint Inc. 140-1 Antares Dr. Ottawa, Ontario K2E 8C4 Canada firstname.lastname@example.org
Product information Image Systems AB Main office: Ågatan 40, SE-582 22 Linköping Phone +46 13 200 100, fax +46 13 200 150 email@example.com, Introduction TrackEye is the world leading system for motion
Navigation simulators Propagation Channel Emulator ECP_V3 1 Product Description The ECP (Propagation Channel Emulator V3) synthesizes the principal phenomena of propagation occurring on RF signal links
Technical Teaching Equipment Computer Controlled Generating Stations Control and Regulation Simulator, with SCADA SCE EDIBON SCADA System Teaching Technique used 4 5 2 Data Acquisition Board Cables and
Synchronization of sampling in distributed signal processing systems Károly Molnár, László Sujbert, Gábor Péceli Department of Measurement and Information Systems, Budapest University of Technology and
Digital Signal Controller Based Automatic Transfer Switch by Venkat Anant Senior Staff Applications Engineer Freescale Semiconductor, Inc. Abstract: An automatic transfer switch (ATS) enables backup generators,
AUTOMATYKA/ AUTOMATICS 2013 Vol. 17 No. 1 http://dx.doi.org/10.7494/automat.2013.17.1.73 Mariusz Rudnicki*, Jan Schmidt*, Aleksander Schmidt*, Wojciech Leœniak* Acoustic Processor of the MCM Sonar 1. Introduction
HD Radio FM Transmission System Specifications Rev. E January 30, 2008 Doc. No. SY_SSS_1026s TRADEMARKS The ibiquity Digital logo and ibiquity Digital are registered trademarks of ibiquity Digital Corporation.
AN1200.04 Application Note: FCC Regulations for ISM Band Devices: Copyright Semtech 2006 1 of 15 www.semtech.com 1 Table of Contents 1 Table of Contents...2 1.1 Index of Figures...2 1.2 Index of Tables...2
CATIA V5 Tutorials Mechanism Design & Animation Release 18 Nader G. Zamani University of Windsor Jonathan M. Weaver University of Detroit Mercy SDC PUBLICATIONS Schroff Development Corporation www.schroff.com
1 of 10 1/25/2008 3:38 AM SIGNAL PROCESSING & SIMULATION NEWSLETTER Note: This is not a particularly interesting topic for anyone other than those who ar e involved in simulation. So if you have difficulty
1 Enhancing the SNR of the Fiber Optic Rotation Sensor using the LMS Algorithm Hani Mehrpouyan, Student Member, IEEE, Department of Electrical and Computer Engineering Queen s University, Kingston, Ontario,
Optimizing VCO PLL Evaluations & PLL Synthesizer Designs Today s mobile communications systems demand higher communication quality, higher data rates, higher operation, and more channels per unit bandwidth.
Universal Journal of Electrical and Electronic Engineering 3(1): 1-5, 2015 DOI: 10.13189/ujeee.2015.030101 http://www.hrpub.org Low Frequency Reader and Antenna Design Using RFID Waqas Malik Department
International Journal of Project Management Vol. 17, No. 3, pp. 181±188, 1999 # 1998 Elsevier Science Ltd and IPMA. All rights reserved Printed in Great Britain 0263-7863/98 $19.00 + 0.00 PII: S0263-7863(98)00026-X
HEDS-9000/9100 Two Channel Optical Incremental Encoder Modules Data Sheet Description The HEDS-9000 and the HEDS-9100 series are high performance, low cost, optical incremental encoder modules. When used
www.led-professional.com ISSN 1993-890X Trends & Technologies for Future Lighting Solutions ReviewJan/Feb 2015 Issue LpR 47 International Year of Light 2015 Tech-Talks BREGENZ: Mehmet Arik Well-Being in
INTRODUCTION Fibre optics behave quite different to metal cables. The concept of information transmission is the same though. We need to take a "carrier" signal, identify a signal parameter we can modulate,
Atmel 8-bit and 32-bit Microcontrollers AVR127: Understanding ADC Parameters APPLICATION NOTE Introduction This application note explains the basic concepts of analog-to-digital converter (ADC) and the
SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 6, No. 3, December 2009, 515-524 UDK: 004.738.2 Influence of Load Balancing on Quality of Real Time Data Transmission* Nataša Maksić 1,a, Petar Knežević 2,
International Conference on Product Lifecycle Management 1 Improving Interoperability in Mechatronic Product Developement Dr. Alain Biahmou, Dr. Arnulf Fröhlich, Dr. Josip Stjepandic PROSTEP AG Dolivostr.
DIGITAL INSTRUMENTATION PRINCIPLES WHY DIGITAL? - Transducers: analog output. - Analog to digital: - precision - values not changed during processing - signal processing using micro-processing. Digital
Disclaimer: This document was part of the First European DSP Education and Research Conference. It may have been written by someone whose native language is not English. TI assumes no liability for the
76 IEEE POWER ELECTRONICS LETTERS, VOL. 3, NO. 2, JUNE 2005 Constant and High Switching Frequency Torque Controller DTC Drives C. L. Toh, N. R. N. Idris, Senior Member, IEEE, and A. H. M. Yatim, Senior
Patient Monitoring Using Embedded Palaparthi.Jagadeesh Chand Associate Professor in ECE Department, Nimra Institute of Science & Technology, Vijayawada, A.P Abstract The aim of this project is to inform
Introduction White Paper Using Pre-Emphasis and Equalization with Stratix GX New high speed serial interfaces provide a major benefit to designers looking to provide greater data bandwidth across the backplanes
3x3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 s Introduction Convolution is one of the basic and most common operations in both analog and digital domain signal processing.
Agilent AEDB-9140 Series Three Channel Optical Incremental Encoder Modules with Codewheel, 100 CPR to 500 CPR Data Sheet Description The AEDB-9140 series are three channel optical incremental encoder modules
FREQUENCY RESPONSE ANALYZERS Dynamic Response Analyzers Servo analyzers When you need to stabilize feedback loops to measure hardware characteristics to measure system response BAFCO, INC. 717 Mearns Road
Precise Modelling of a Gantry Crane System Including Friction, 3D Angular Swing and Hoisting Cable Flexibility Renuka V. S. & Abraham T Mathew Electrical Engineering Department, NIT Calicut E-mail : firstname.lastname@example.org,
Clock Recovery in Serial-Data Systems Ransom Stephens, Ph.D. Abstract: The definition of a bit period, or unit interval, is much more complicated than it looks. If it were just the reciprocal of the data
HD Radio FM Transmission System Specifications Rev. F August 24, 2011 SY_SSS_1026s TRADEMARKS HD Radio and the HD, HD Radio, and Arc logos are proprietary trademarks of ibiquity Digital Corporation. ibiquity,
White Paper Better Digital Signal Performance; Lower Costs With Innovative IntervalZero RTX Real-time Platform I. Overview Digital Signal Processors (s) have specialized architectures that are optimized
Learning Outcomes Simple CPU Operation and Buses Dr Eddie Edwards email@example.com At the end of this lecture you will Understand how a CPU might be put together Be able to name the basic components
Journal of Electromagnetic Analysis and Applications, 2012, 4, 162-166 http://dx.doi.org/10.4236/jemaa.2012.44021 Published Online April 2012 (http://www.scirp.org/journal/jemaa) Design of Bidirectional
Operating Systems: Internals and Design Principles Chapter 1 Computer System Overview Eighth Edition By William Stallings Operating System Exploits the hardware resources of one or more processors Provides
Parameter identification of a linear single track vehicle model Edouard Davin D&C 2011.004 Traineeship report Coach: dr. Ir. I.J.M. Besselink Supervisors: prof. dr. H. Nijmeijer Eindhoven University of
RF Measurements Using a Modular Digitizer Modern modular digitizers, like the Spectrum M4i series PCIe digitizers, offer greater bandwidth and higher resolution at any given bandwidth than ever before.
Outline Modeling, simulation and optimization of Multi-Processor SoCs (MPSoCs) Università of Verona Dipartimento di Informatica MPSoCs: Multi-Processor Systems on Chip A simulation platform for a MPSoC
Evaluation Board for Universal Frequency-to- Digital Converters UFDC-1 and UFDC-1M-16 EVAL-UFDC-1/UFDC-1M-16 FEATURES Full-Featured Evaluation Board for the Universal Frequency-to-Digital Converters UFDC-1
Evolution from Voiceband to Broadband Internet Access Murtaza Ali DSPS R&D Center Texas Instruments Abstract With the growth of Internet, demand for high bit rate Internet access is growing. Even though
Braking/Traction Control Systems of a Scaled Railway Vehicle for the Active Steering Testbed Min-Soo Kim and Hyun-Moo Hur Vehicle Dynamics & Propulsion System Research Department Korea Railroad Research
Developing applications under CODE COMPOSER STUDIO 1. General Overview Code Composer Studio (CCS ) is a very efficient instrument for the fast development of applications that are written for the DSP families
Measuring Laser Power and Energy Output Introduction The most fundamental method of checking the performance of a laser is to measure its power or energy output. Laser output directly affects a laser s
Orbital Mechanics The objects that orbit earth have only a few forces acting on them, the largest being the gravitational pull from the earth. The trajectories that satellites or rockets follow are largely
Distributed Computing Solution for Hardware-In-LoopSimulation of Indian Satellites Rashmi Jagade, Sridevi.K.N, Jitendranath Mungara Abstract The purpose of Hardware-In-Loop-Simulation (HILS) is to verify
Page 1 Electronic Communications Committee (ECC) within the European Conference of Postal and Telecommunications Administrations (CEPT) ECC RECOMMENDATION (06)01 Bandwidth measurements using FFT techniques
Product brochure Version 02.00 Vector Signal Analyzer FSQ-K70 July 2004 Universal demodulation, analysis and documentation of digital radio signals For all major mobile radio communication standards: GSM