SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS

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1 1 GND GND GND V V V SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 SINGLE-SUPPL VOLTGE-LEVEL TRNSLTOR WITH NINE ONFIGURLE GTE LOGI FUNTIONS heck for Samples: SN74UP1T97 1FETURES 2 vailable in the Texas Instruments NanoStar (TOP VIEW) Packages Single-Supply Voltage Translator 1.8 V to 3.3 V (at V = 3.3 V) 2.5 V to 3.3 V (at V = 3.3 V) 1.8 V to 2.5 V (at V = 2.5 V) DV OR DK PKGE DR OR DSF PKGE 3.3 V to 2.5 V (at V = 2.5 V) (TOP VIEW) Nine onfigurable Gate Logic Functions Schmitt-Trigger Inputs Reject Input Noise and Provide etter Output Signal Integrity I off Supports Partial-Power-Down Mode With Low Leakage urrent (0.5 µ) Very Low Static and Dynamic Power FP OR ZP PKGE onsumption (TOP VIEW) Pb-Free Packages vailable: SON (DR or DSF), SOT-23 (DV), S-70 (DK), and NanoStar WSP Latch-Up Performance Exceeds 100 m Per JESD 78, lass II ESD Performance Tested Per JESD V Human-ody Model (114-, lass II) 1000-V harged-device Model (101) Related Devices: SN74UP1T98, SN74UP1T57, and SN74UP1T58 DESRIPTION/ORDERING INFORMTION UP technology is the industry's lowest-power logic technology designed for use in battery-operated or battery backed-up equipment. The SN74UP1T97 is designed for logic-level translation applications with input switching levels that accept 1.8-V LVMOS signals, while operating from either a single 3.3-V or 2.5-V V supply. The wide V range of 2.3 V to 3.6 V allows the possibility of battery voltage drop during system operation and ensures normal operation between this range. Schmitt-trigger inputs (ΔV T = 210 mv between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition. The SN74UP1T97 can be easily configured to perform a required gate function by connecting,, and inputs to V or ground (see Function Selection table). Up to nine commonly used logic gate functions can be performed. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2NanoStar is a trademark of Texas Instruments. PRODUTION DT information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright , Texas Instruments Incorporated

2 SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 I off is a feature that allows for powered-down conditions (V = 0 V) and is important in portable and mobile applications. When V = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions. The SN74UP1T97 is designed with optimized current-drive capability of 4 m to reduce line reflections, overshoot, and undershoot caused by high-drive outputs. NanoStar package technology is a major breakthrough in I packaging concepts, using the die as the package. ORDERING INFORMTION (1) T PKGE (2) ORDERLE PRT NUMER TOP-SIDE MRKING (3) NanoStar WSP (DSG) 0.23-mm Large ump ZP (Pb-free) Reel of 3000 SN74UP1T97ZPR _TH_ NanoStar WSP (DSG) 0.23-mm Large ump FP Reel of 3000 SN74UP1T97FPR _TH_ 40 to 85 QFN DR Reel of 5000 SN74UP1T97DRR TH uqfn DSF Reel of 5000 SN74UP1T97DSFR TH SOT (SOT-23) DV Reel of 3000 SN74UP1T97DVR HT4_ SOT (S-70) DK Reel of 3000 SN74UP1T97DKR TH_ (1) For the most current package and ordering information, see the Package Option ddendum at the end of this document, or see the TI web site at. (2) Package drawings, thermal data, and symbolization are available at /packaging. (3) DV/DK: The actual top-side marking has one additional character that designates the wafer fab/assembly site. ZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free). FUNTION SELETION TLE LOGI FUNTION FIGURE NO. 2-to-1 data selector 5 2-input ND gate 6 2-input OR gate with one inverted input 7 2-input NND gate with one inverted input 7 2-input ND gate with one inverted input 8 2-input NOR gate with one inverted input 8 2-input OR gate 9 Inverter 10 Noninverted buffer % 80% 60% 40% 20% 0% Static-Power onsumption (µ) 3.3-V Logic UP Single, dual, and triple gates 100% 80% 60% 40% 20% 0% Dynamic-Power onsumption (pf) 3.3-V LV Logic UP Figure 1. UP The Lowest-Power Family Voltage V Input Switching haracteristics at 25 MHz Output Time ns UP1G08 data at L = 15 pf Figure 2. Excellent Signal Integrity 2 Submit Documentation Feedback opyright , Texas Instruments Incorporated Product Folder Link(s): SN74UP1T97

3 SN74UP1T97 SES613I OTOER 2004 REVISED M V 3.3 V V IH = 1.19 V V IL = 0.5 V V IH = 1.19 V V IL = 0.5 V 1.8-V System 3.3-V System 2.5-V System 3.3-V System SN74UP1T97 SN74UP1T V 2.5 V V IH = 1.10 V V IL = 0.35 V V IH = 1.10 V V IL = 0.35 V 1.8-V System 2.5-V System 3.3-V System 2.5-V System SN74UP1T97 Figure 3. Possible Voltage-Translation ombinations SN74UP1T V 1.8-V System 3.3-V System SN74UP1T97 V OH min V T+ max = V IH min = 1.19 V V T min = V IL max = 0.5 V V OL max Input Switching Waveform Output Switching Waveform Figure 4. Switching Thresholds for 1.8-V to 3.3-V Translation opyright , Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): SN74UP1T97

4 SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 INPUTS FUNTION TLE OUTPUT L L L L L L H L L H L H L H H H H L L L H L H H H H L L H H H H LOGI DIGRM (POSITIVE LOGI) LOGI ONFIGURTIONS V GND Figure : 2-to-1 Data Selector/MUX When is L, = When is H, = V GND Figure 6. 08: 2-Input ND Gate 4 Submit Documentation Feedback opyright , Texas Instruments Incorporated Product Folder Link(s): SN74UP1T97

5 SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 V GND Figure /14+00: 2-Input OR/NND Gate With One Inverted Input V GND Figure /14+02: 2-Input ND/NOR Gate With One Inverted Input V GND Figure 9. 32: 2-Input OR Gate V GND Figure /14: Inverter opyright , Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): SN74UP1T97

6 SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 V GND Figure /34: Noninverted uffer 6 Submit Documentation Feedback opyright , Texas Instruments Incorporated Product Folder Link(s): SN74UP1T97

7 REOMMENDED OPERTING ONDITIONS (1) MIN MX UNIT SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 SOLUTE MXIMUM RTINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MX UNIT V Supply voltage range V V I Input voltage range (2) V V O Voltage range applied to any output in the high-impedance or power-off state (2) V V O Output voltage range in the high or low state (2) 0.5 V V I IK Input clamp current V I < 0 50 m I OK Output clamp current V O < 0 50 m I O ontinuous output current ±20 m ontinuous current through V or GND ±50 m DV package 165 DK package 259 DR package 340 q J Package thermal impedance (3) /W DSF package 300 FP package 123 ZP package 123 T stg Storage temperature range (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD V Supply voltage V V I Input voltage V V O Output voltage 0 V V V = 2.3 V 3.1 I OH High-level output current m V = 3 V 4 V = 2.3 V 3.1 I OL Low-level output current m V = 3 V 4 T Operating free-air temperature (1) ll unused inputs of the device must be held at V or GND to ensure proper device operation. See the TI application report Implications of Slow or Floating MOS Inputs, literature number S004. opyright , Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): SN74UP1T97

8 SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 ELETRIL HRTERISTIS over recommended operating free-air temperature range (unless otherwise noted) T = 40 T = 25 PRMETER TEST ONDITIONS V to 85 UNIT MIN TP MX MIN MX V T+ 2.3 V to 2.7 V Positive-going input threshold voltage 3 V to 3.6 V V T 2.3 V to 2.7 V Negative-going input threshold voltage 3 V to 3.6 V ΔV T 2.3 V to 2.7 V Hysteresis (V T+ V T ) 3 V to 3.6 V I OH = 20 µ 2.3 V to 3.6 V V 0.1 V 0.1 I OH = 2.3 m V V OH I OH = 3.1 m V I OH = 2.7 m V I OH = 4 m I OL = 20 µ 2.3 V to 3.6 V I OL = 2.3 m V V OL I OL = 3.1 m V I OL = 2.7 m V I OL = 4 m I I ll inputs V I = 3.6 V or GND 0 V to 3.6 V µ I off V I or V O = 0 V to 3.6 V 0 V µ ΔI off V I or V O = 3.6 V 0 V to 0.2 V µ I V I = 3.6 V or GND, I O = V to 3.6 V µ One input at 0.3 V or 1.1 V, 2.3 V to 2.7 V 4 Other inputs at 0 or V, I O = 0 ΔI µ One input at 0.45 V or 1.2 V, 3 V to 3.6 V 12 Other inputs at 0 or V, I O = 0 i V I = V or GND 3.3 V 1.5 pf o V O = V or GND 3.3 V 3 pf SWITHING HRTERISTIS over recommended operating free-air temperature range, V = 2.5 V ± 0.2 V, V I = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 12) T = 40 FROM TO T = 25 PRMETER L to 85 UNIT (INPUT) (OUTPUT) MIN TP MX MIN MX 5 pf pf t pd,, or ns 15 pf pf V V V 8 Submit Documentation Feedback opyright , Texas Instruments Incorporated Product Folder Link(s): SN74UP1T97

9 SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 SWITHING HRTERISTIS over recommended operating free-air temperature range, V = 2.5 V ± 0.2 V, V I = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 12) T = 40 FROM TO T = 25 PRMETER L to 85 UNIT (INPUT) (OUTPUT) MIN TP MX MIN MX 5 pf pf t pd,, or ns 15 pf pf SWITHING HRTERISTIS over recommended operating free-air temperature range, V = 2.5 V ± 0.2 V, V I = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 12) T = 40 FROM TO T = 25 PRMETER L to 85 UNIT (INPUT) (OUTPUT) MIN TP MX MIN MX 5 pf pf t pd,, or ns 15 pf pf SWITHING HRTERISTIS over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V, V I = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 12) T = 40 FROM TO T = 25 PRMETER L to 85 UNIT (INPUT) (OUTPUT) MIN TP MX MIN MX 5 pf pf t pd,, or ns 15 pf pf SWITHING HRTERISTIS over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V, V I = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 12) T = 40 FROM TO T = 25 PRMETER L to 85 UNIT (INPUT) (OUTPUT) MIN TP MX MIN MX 5 pf pf t pd,, or ns 15 pf pf opyright , Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): SN74UP1T97

10 SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 SWITHING HRTERISTIS over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V, V I = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 12) T = 40 FROM TO T = 25 PRMETER L to 85 UNIT (INPUT) (OUTPUT) MIN TP MX MIN MX 5 pf pf t pd,, or ns 15 pf pf OPERTING HRTERISTIS T = 25 V = 2.5 V V = 3.3 V PRMETER TEST ONDITIONS UNIT TP TP pd Power dissipation capacitance f = 10 MHz 4 5 pf 10 Submit Documentation Feedback opyright , Texas Instruments Incorporated Product Folder Link(s): SN74UP1T97

11 SN74UP1T97 SES613I OTOER 2004 REVISED M 2010 PRMETER MESUREMENT INFORMTION From Output Under Test L (see Note ) 1 MΩ L V MI V MO V = 2.5 V ± 0.2 V 5, 10, 15, 30 pf V I /2 V /2 V = 3.3 V ± 0.3 V 5, 10, 15, 30 pf V I /2 V /2 LOD IRUIT V I Input V MI V MI 0 V t PLH t PHL V OH Output V MO V Mo V OL t PHL t PLH Output V Mo V Mo VOLTGE WVEFORMS PROPGTION DEL TIMES INVERTING ND NONINVERTING OUTPUTS V OH V OL NOTES:. L includes probe and jig capacitance.. ll input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50 Ω, slew rate 1 V/ns.. The outputs are measured one at a time, with one transition per measurement. D. t PLH and t PHL are the same as t pd. Figure 12. Load ircuit and Voltage Waveforms opyright , Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): SN74UP1T97

12 PKGE OPTION DDENDUM 17-Mar-2017 PKGING INFORMTION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan SN74UP1T97DVR TIVE SOT-23 DV Green (RoHS & no Sb/r) SN74UP1T97DVT TIVE SOT-23 DV Green (RoHS & no Sb/r) SN74UP1T97DVTG4 TIVE SOT-23 DV Green (RoHS & no Sb/r) SN74UP1T97DKR TIVE S70 DK Green (RoHS & no Sb/r) SN74UP1T97DKRE4 TIVE S70 DK Green (RoHS & no Sb/r) SN74UP1T97DKRG4 TIVE S70 DK Green (RoHS & no Sb/r) SN74UP1T97DRR TIVE SON DR Green (RoHS & no Sb/r) SN74UP1T97DSFR TIVE SON DSF Green (RoHS & no Sb/r) SN74UP1T97FPR TIVE DSG FP Green (RoHS & no Sb/r) SN74UP1T97ZPR TIVE DSG ZP Green (RoHS & no Sb/r) (2) Lead/all Finish (6) MSL Peak Temp (3) Op Temp ( ) U NIPDU Level UNLIM -40 to 85 HT4R Device Marking U NIPDU Level UNLIM -40 to 85 (HT4F ~ HT4R) U NIPDU Level UNLIM -40 to 85 (HT4F ~ HT4R) U NIPDU Level UNLIM -40 to 85 (THF ~ THR) U NIPDU Level UNLIM -40 to 85 (THF ~ THR) U NIPDU Level UNLIM -40 to 85 (THF ~ THR) U NIPDU Level UNLIM -40 to 85 TH U NIPDU U NIPDUG Level UNLIM -40 to 85 TH SNGU Level UNLIM -40 to 85 (TH2 ~ THN) SNGU Level UNLIM -40 to 85 (TH2 ~ TH7 ~ THN) (4/5) Samples (1) The marketing status values are defined as follows: TIVE: Product device recommended for new designs. LIFEU: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/r) - please check for the latest availability information and additional product content details. TD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/r): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of romine (r) and ntimony (Sb) based flame retardants (r or Sb do not exceed 0.1% by weight in homogeneous material) ddendum-page 1

13 PKGE OPTION DDENDUM 17-Mar-2017 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDE industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/all Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/all Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus S numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to ustomer on an annual basis. ddendum-page 2

14 PKGE MTERILS INFORMTION 3-ug-2017 TPE ND REEL INFORMTION *ll dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) 0 (mm) 0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74UP1T97DVR SOT-23 DV Q3 SN74UP1T97DVT SOT-23 DV Q3 SN74UP1T97DKR S70 DK Q3 SN74UP1T97DRR SON DR Q1 SN74UP1T97DSFR SON DSF Q2 SN74UP1T97FPR DSG FP Q1 SN74UP1T97ZPR DSG ZP Q1 Pack Materials-Page 1

15 PKGE MTERILS INFORMTION 3-ug-2017 *ll dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74UP1T97DVR SOT-23 DV SN74UP1T97DVT SOT-23 DV SN74UP1T97DKR S70 DK SN74UP1T97DRR SON DR SN74UP1T97DSFR SON DSF SN74UP1T97FPR DSG FP SN74UP1T97ZPR DSG ZP Pack Materials-Page 2

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22 SLE FP0006 PKGE OUTLINE DSG mm max height DIE SIZE LL GRID RR E LL 1 ORNER D 0.5 MX LL TP SETING PLNE TP SMM 0.8 TP SMM D: Max = E: Max = 1.19 mm, Min = 1.13 mm 0.79 mm, Min = 0.73 mm 0.4 TP 6X / 11/2016 NOTES: 1. ll linear dimensions are in millimeters. ny dimensions in parenthesis are for reference only. Dimensioning and tolerancing per SME 14.5M. 2. This drawing is subject to change without notice.

23 FP0006 EXMPLE ORD LOUT DSG mm max height DIE SIZE LL GRID RR (0.4) TP 6X ( 0.23) 1 2 (0.4) TP SMM SMM LND PTTERN EXMPLE SLE:50X ( 0.23) METL 0.05 MX 0.05 MIN METL UNDER SOLDER MSK SOLDER MSK OPENING NON-SOLDER MSK DEFINED (PREFERRED) SOLDER MSK DEFINED ( 0.23) SOLDER MSK OPENING SOLDER MSK DETILS NOT TO SLE / 11/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNV009 (/lit/snva009).

24 FP0006 EXMPLE STENIL DESIGN DSG mm max height DIE SIZE LL GRID RR (0.4) TP 6X ( 0.25) (R0.05) TP 1 2 (0.4) TP SMM METL TP SMM SOLDER PSTE EXMPLE SED ON 0.1 mm THIK STENIL SLE:50X / 11/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

25 MEHNIL DT DSF (S-PX2SON-N6) PLSTI SMLL OUTLINE NO-LED PIN 1 INDEX RE MX SETING PLNE 0.05 SMM (0.11) TP 3 4 2X 0.7 4X (0.1) PIN 1 ID 6X SMM 6X /F 10/2014 NOTES: 1. ll linear dimensions are in millimeters. ny dimensions in parenthesis are for reference only. Dimensioning and tolerancing per SME 14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDE registration MO-287, variation X2F.

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27 SLE ZP0006 PKGE OUTLINE DSG mm max height DIE SIZE LL GRID RR E LL 1 ORNER D 0.5 MX LL TP SETING PLNE TP SMM 0.5 TP 1 TP D: Max = mm, Min = mm E: Max = mm, Min = mm X SMM / 06/2014 NOTES: NanoFree Is a trademark of Texas Instruments. 1. ll linear dimensions are in millimeters. ny dimensions in parenthesis are for reference only. Dimensioning and tolerancing per SME 14.5M. 2. This drawing is subject to change without notice. 3. NanoFree TM package configuration.

28 ZP0006 EXMPLE ORD LOUT DSG mm max height DIE SIZE LL GRID RR 6X ( 0.225) (0.5) TP 1 2 (0.5) TP SMM SMM LND PTTERN EXMPLE SLE:40X ( 0.225) 0.05 MX METL 0.05 MIN METL UNDER MSK SOLDER MSK OPENING NON-SOLDER MSK DEFINED (PREFERRED) SOLDER MSK DEFINED ( 0.225) SOLDER MSK OPENING SOLDER MSK DETILS NOT TO SLE / 06/2014 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SV017 (/lit/sbva017).

29 ZP0006 EXMPLE STENIL DESIGN DSG mm max height DIE SIZE LL GRID RR 6X ( 0.25) (0.5) TP 1 2 (R 0.05) TP (0.5) TP SMM METL TP SMM SOLDER PSTE EXMPLE SED ON 0.1 mm THIK STENIL SLE:40X / 06/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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