The Memory/Processor Performance Gap. Memory-Processor Performance Gap

Transcription

1 Memory

2 The Memory/Processor Performance Gap Memory-Processor Performance Gap

3 The memory hierarchy CPU Level 1 Increasing distance from the CPU in access time Levels in the memory hierarchy Level 2 Level n Size of the memory at each level

4 The memory hierarchy

5 Fundamentals of Memory Hierarchy Locality Temporal locality The currently required data are likely to need again in the near future Spatial locality There is high probability that the other data nearby will be need soon

6 Two Processor/Memory Architectures Princeton Fewer memory wires Harvard Simultaneous program and data memory access Program memory Processor Harvard Data memory Processor Memory (program and data) Princeton

7 Memory Access Process Virtual address hit Physical Address Tag miss CPU TLB Cache Main Memory miss hit Address Translation data TLB (Translation lookaside buffer): Translate a virtual address to a physical address

8 Memory management units Handles DRAM refresh, bus interface and arbitration Takes care of memory sharing among multiple processors Translates logic memory addresses from processor to physical memory addresses CPU logical address memory management unit physical address main memory

9 Memory Data Organization Endianness Big Endian/Little Endian Memory data alignment

10 Endianness The order of bytes (sometimes bit ) in memory to represent different data types Little/Big Endian Little Endian: put the least-significant byte first (at lower address) e.g. Intel Processor Big Endian: put the most-significant byte first e.g.some PowerPCs, Motorola, MIPS, SPARC

11 Big/Little Endian Example 32bit data 0xFABC0123 at address 0xFF20 0xFF20 0xFF21 0xFF22 0xFF23 Big Endian 0xFA 0xBC 0x01 0x23 Little Endian 0x23 0x01 0xBC 0xFA

12 Data Alignment Data alignment A datum with multiple bytes need to be allocated to an address that is a multiple of its size Examples 0bxxxxxxxxxx byte (8bit) aligned 0bxxxxxxxxx0 half word (16bit) aligned 0bxxxxxxxx00 word (32bit) aligned 0bxxxxxxx000 double word (64bit) aligned Why aligned? Misalignment causes implementation complications and reduces performance

13 m words Memory device: basic concepts Stores large number of bits m x n: m words of n bits each k = Log2(m) address input signals or m = 2^k words e.g., 4,096 x 8 memory: 32,768 bits Memory access 12 address input signals 8 input/output data signals r/w: selects read or write enable: read or write only when asserted multiport: multiple accesses to different locations simultaneously r/w enable A 0 A k-1 m n memory n bits per word memory external view 2 k n read and write memory Q n-1 Q 0

14 Memory Types

15 ROM: Read-Only Memory Nonvolatile memory Can be read from but not written to, by a processor in an embedded system Traditionally written to, programmed, before inserting to embedded system Uses Store software program for general-purpose processor program instructions can be one or more ROM words Store constant data needed by system Implement combinational circuit enable A 0 A k-1 External view 2 k n ROM Q n-1 Q 0

16 Example: 8 x 4 ROM Horizontal lines = words Vertical lines = data Lines connected only at circles Decoder sets word 2 s line to 1 if address input is 010 Data lines Q3 and Q1 are set to 1 because there is a programmed connection with word 2 s line Word 2 is not connected with data lines Q2 and enable A 0 A 1 A decoder programmable connection Internal view 8 4 ROM word 0 word 1 word 2 word line data line wired-or Q0 Q 3 Q 2 Q 1 Q 0 Output is 1010

17 Implementing combinational function Any combinational circuit of n functions of same k variables can be done with 2^k x n ROM Truth table Inputs (address) Outputs a b c y z enable c b a 8 2 ROM y z word 0 word 1 word 7

18 Types of ROM Written during manufacture Programmable (once) PROM Needs special equipment to program Read mostly Erasable Programmable (EPROM) Erased by UV can program and erase individual words Electrically Erasable (EEPROM) Takes much longer to write than read can program and erase individual words as well Flash memory Large blocks of memory read/write at once, rather than one word at a time Faster erase

19 RAM Random access memory Typically volatile memory bits are not held without power supply Read and written easily by processor during execution r/w enable A 0 A k-1 external view 2 k n read and write memory Internal structure more complex than ROM a word consists of several memory cells, each storing 1 bit each input and output data line connects to each cell in its column rd/wr connected to every cell when row is enabled by decoder, each cell has logic that stores input data bit when rd/wr indicates write or outputs stored bit when rd/wr indicates read enable A 0 A 1 rd/wr 4 4 RAM 2 4 decoder Q n-1 To every cell Q 0 internal view I 3 I 2 I 1 I 0 Memory cell Q 3 Q 2 Q 1 Q 0

20 Types of RAM SRAM: Static RAM Memory cell uses flip-flop to store bit Holds data as long as power supplied DRAM: Dynamic RAM Memory cell uses transistor and capacitor to store bit More compact than SRAM Refresh required due to capacitor leak Slower to access than SRAM

21 Device Schematic and Time Diagram 11-13, data<70> 11-13, data<70> 2,23,21,24, 25, addr<15...0> /OE 27,26,2,23,21, 24,25, addr<15...0> /OE 27 /WE 20 /CS 20 /CS1 26 CS2 HM6264 block diagrams 27C256 Device Access Time (ns) Standby Pwr. (mw) Active Pwr. (mw) Vcc Voltage (V) HM C device characteristics Read operation Write operation data addr OE /CS1 CS2 data addr WE /CS1 CS2 timing diagrams

22 Composing memory Memory size needed often differs from size of readily available memories When available memory is larger, simply ignore unneeded highorder address bits and higher data lines When available memory is smaller, compose several smaller memories into one larger memory Connect side-by-side to increase width of words Connect top to bottom to increase number of words added high-order address line selects smaller memory containing desired word using a decoder Combine techniques to increase number and width of words A 0 enable A m-1 A m 1 2 decoder Increase number of words 2 m+1 n ROM 2 m n ROM 2 m n ROM Q n-1 Q 0 Increase width of words enable A 0 A m 2 m n ROM 2 m 3n ROM 2 m n ROM 2 m n ROM Increase number and width of words A enable outputs Q 3n-1 Q 2n-1 Q 0

23 Summary Memory hierarchy Memory/processor architecture Memory access process Endianness Data alignment Memory data organization Memory devices Basics ROM/RAM