CPU includes ALU, control unit, registers, program counter. Alternates between instruction fetching and execution (more on this soon)

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1 Equivalence between hardware and software: Anything that can be done in software can be done in hardware, and vice-versa Breakthrough: Instead of programming the machines by changing the wiring, store a program in memory (but this had to wait until suitable storage means were available) omponents: PU includes, control, registers, program counter system I/O subsystem to connect external devices Fundamental properties: Sequential instruction processing Alternates between instruction fetching and execution (more on this soon)

2 (note: this was proposed earlier by John Mauchly and Presper Eckert creators of EIA) system bus I/O subsystem Data bus transfer information between the PU and the memory and peripherals PU Address bus provides the address information required to access specific memory locations or peripheral devices memory Subsystem bus provides control signals to memory and devices data address control

3 A block diagram of a simple PU A B (aka register file) : Arithmetic and Logic Unit: does all the number crunching and logic operations, computes addresses, executes instructions : Fastest memory in the system, they store data and results for the Special purpose registers: (program counter) keeps address of the next instruction to be executed, register contains flags that indicate special conditions resulting from the execution of instructions (eg overflow, divide by zero) : Takes care of instruction fetch and decoding, Interfacing with the memory system, and general sequencing of operations within the PU : Memory address register ontains the address of whatever memory location is being currently referenced : Memory buffer register ontains the data being read from, or written to memory Each PU will have their own special purpose registers, this is just a general model

4 A block diagram of a simple PU A B (aka register file) The registers are connected directly to the The can only operate on data that is stored in the registers, and can only store data into the registers The control determines control what operations are performed by the, and uses the program counter to determine what location in memory holds the next instruction that will be executed The control also connects to the and to provide address information and access data from the memory system or I/O subsystem To memory and I/O subsystems through system bus

5 A block diagram of a simple PU A B (aka register file) The width of the registers determines the maximum capacity of the for doing integer arithmetic, logic, and single step addressing (eg 8bit, 16bit, 32bit, 64bit, etc PUs) The PU can never directly perform operations on data stored in the main memory At least 1 of the operands, and often both, have to be brought into the PU s registers for manipulation The result is then written back to the desired location in main memory To memory and I/O subsystems through system bus

6 A B (aka register file) code ode and data now stored in main memory data

7 A B (aka register file) Processor has to alternate between reading code and accessing/manipulating data

8 A B (aka register file) 3 Stage ycle: Fetch Decode -Execute * Sometimes a 4 th stage is added Fetch Decode Execute -Write

9 A B (aka register file) Fetch The contents of the program counter are loaded onto the This selects the address of the next instruction () The instruction is read Into the

10 A B (aka register file) Decode The instruction is converted Into a sequence of simple register/ operations This sequence of operations is known as microcode Decode: (load the value of variable x into register A) converts to: - Move address of x to -Read x into - Store into register A

11 5 B (aka register file) Execute The sequence of microcode instructions is executed Decode: (load the value of variable x into register A) converts to: - Move address of x to -Read x into - Store into register A

12 5 B (aka register file) Execute The sequence of microcode instructions is executed Decode: (load the value of variable x into register A) converts to: - Move address of x to -Read x into - Store into register A

13 5 B (aka register file) Execute The program counter is incremented to point to the next instruction

14 5 B (aka register file) Repeat the cycle Fetch

15 5 B (aka register file) Repeat the cycle Decode Decode: (load the value of variable y into register B) converts to: - Move address of y to -Read y into - Store into register B

16 5 2 (aka register file) Repeat the cycle Execute microcode for Decode: (load the value of variable y into register B) converts to: - Move address of y to -Read y into - Store into register B

17 5 2 (aka register file) Repeat the cycle Increment

18 5 2 (aka register file) Repeat the cycle Fetch

19 5 2 (aka register file) Repeat the cycle Decode Decode: (add the contents of registers A and B) converts to: - : Sum reg A, reg B -Store result in A

20 7 2 (aka register file) Repeat the cycle Execute microcode for Decode: (add the contents of registers A and B) converts to: - : Sum reg A, reg B -Store result in A

21 7 2 (aka register file) Repeat the cycle Increment

22 7 2 (aka register file) Repeat the cycle Fetch

23 7 2 (aka register file) Repeat the cycle Decode Decode: (Store the content of register A at the location of variable result) converts to: - Move address of result to - Store the contents of register A in the - Write to memory

24 7 2 (aka register file) Repeat the cycle Execute microcode for result = 7 Decode: (Store the content of register A at the location of variable result) converts to: - Move address of result to - Store the contents of register A in the - Write to memory

25 7 2 (aka register file) Repeat the cycle Increment result = 7

26 Fetch-Decode-Execute This cycle is performed uninterruptedly by the PU as long as the system is on The computer is always doing *something* (ie unless sent to stand by, there is always some code being executed what code?-) We need to know how to program the PU (assembly language) Having done that, we will know how to control every aspect of the computer s operation

27 on Von eumann architectures Are becoming more common Parallel computation * Parallel computers * eural etworks * Genetic Algorithms * Quantum computers