AN2180. Power Management Switch Mode Pump in a Step-Down Converter Using PSoC. Application Note Abstract. Introduction

Transcription

1 Power Management Switch Mode Pump in a Step-Down Converter Using PSoC Application Note Abstract AN2180 Author: Andrey Magarita Associated Project: No Associated Part Family: CY87xxx, CY89x66, CY84x23A, CY84x23, CY81x34, CY81x23 Software Version: PSoC Designer 5.1 Associated Application Notes: AN2097 This Application Note demonstrates how to use the PSoC internal switch mode pump () to build a step-down regulator. This allows the PSoC voltage to be derived from higher-voltage sources and eliminates additional switching or linear regulators. Introduction PSoC devices have an internal Switch Mode Pump () that allows designers to build a boost regulator that powers the device with low-voltage sources such as single or double cell NiCd or NiMH batteries. PSoC s consists of a gated generator with a fixed duty cycle of 50% and a voltage comparator. The comparator compares the output voltage with a reference voltage, enables the generator when output voltage is less than the trip point, and disables the generator when the output voltage is higher than the trip point. Following figure shows the boost circuit implementation using : voltage for PSoC devices. This necessitates an additional linear or switching mode regulator. Alternatively, the internal can be used to build a regulated step-down converter. This application note provides details of step down converter implementation using the same feature. The PSoC device pin has an open-drain output with a maximum allowed drain voltage of roughly 6 V. The also requires an additional level translator to form the gate signal for the converter high-side switch. Note that another variant of PSoC device- Power PSoC (PPSoC- Power Controllers CY8CLED0x) has in-built switching regulator (along with PMOS). This provides a low cost solution to derive PSoC device voltage from a high voltage supply. For more details about this PSoC device, refer this link. The standard chopper topology is used in this step-down converter. A scheme is shown in the following figure. Figure 1. Step-Down Converter SW L + - Battery D C R For more details, refer Application Note AN2097 Power Management-Switch Mode Pump. In many practical applications involving PSoC,,it is possible to have DC supply source much higher than allowed DC supply Because the PSoC builds the step-up regulator, the step-down controlling sequence is inverted with respect to the step-up regulation sequence. To provide the device start-up, the control switch is turned on at the initial time to pre-charge the load capacitor to at least 1.1 V when the internal control circuit starts. This can be implemented by applying some design tricks described in this Application Note. Novmeber 15, 2010 Document No Rev. *A 1

2 To implement the step-down converter, it is important to remember that the PSoC internal generator has switching regulators with 1.3 MHz frequencies and duty cycles fixed roughly at 50%. Note that the end application requires the efficiency of the step-down switching regulator to be greater than the efficiency of the corresponding linear regulator. The step down converter implementation using feature is shown in the following figure. Figure 2. Step-Down Converter using Uin Q2 L1 Uout CY8C***** current flow through L1 is continuous, the voltage on L1 is inverted, turning on. As a result, the source of Q2 and the right pin of have a potential near ground and the current through and charges.the charge rate is limited by its capacitance and internal resistance to the diodes that are turned on. During this stage, the accumulated energy in inductor L1 is transferred to load. The path of current flow is shown in the following figure. + Uin - V1 C1 OFF Q2 L1 Uout CY8C ***** Load + - V1 C1 Load ON Transistor acts as the inverter for the control sequence. Transistor Q2 acts as the chopper switch. The bootstrap voltage is generated by the - circuit and is used to switch Q2 to on state with resistor. Here N channel MOSFET is used for Q2 as it is less expensive than the corresponding P-channel transistor. When power is supplied to the converter, switch and Q2 are in off state, Current slowly builds up through the path shown in Figure below: + U in - V1 C1 OFF OFF Q2 L1 Uout CY8C ***** Load When is low, enters off state and the capacitor voltage gets applied across gate-source of Q2 through. This turns ON Q2. As a result, and turn offand the voltage on L1 is inverted again. Q2 is kept in on state by the voltage on.note that voltage across slightly decreases due to Q2 gate-channel capacitance recharging and the leakage currents of, Q2, and. Energy is accumulated in the inductor at this stage. The path of current flow is shown in the following figure. + U in - V1 C1 OFF ON Q2 L1 Uout CY8C ***** Load Diode turns ON, begins charging and transistor Q2 starts entering linear mode through the negative feedback generated by resistor and diode. In linear mode, current flows through channel Q2, current value rises with time, and the slew rate is determined by the values of L1,, and R load. Part of this current charges capacitor and when voltage on is larger than the threshold level (1.1 V), the PSoC internal control logic starts and the regulator start-up stage finishes. When the PSoC internal control logic starts, the control pulses are routed to through pin. When is high, is turned ON. When is ON, Q2 is OFF because the gate-source voltage becomes negative. This stops energy accumulation in inductor L1. Because Novmeber 15, 2010 Document No Rev. *A 2

3 Implementation Limitations The proposed converter has limitations. These are described below. Minimum Input Voltage The input voltage should be at least twice the device s supply voltage. This is necessary because the maximum generator duty cycle is 50% and it is impossible to obtain a factor less than 2 at the minimum current drain. The output voltage, U out, depends on the input voltage, U in, and is given by: t U U U on out in on ton toff Equation 1 t on and t off represent the time Q2 is on and off, respectively. U on is the drop voltage on Q2 when turned on. A method to overcome this limitation is discussed in the Test Schematic section of this Application Note. Maximum Input Voltage The maximum input voltage is limited by the maximum allowable gate-source voltage for Q2 (usually near V). However, this limitation can be partly overcome by using Zener in the Q2 gate circuit. Value The value of should be small enough to rapidly saturate transistor Q2 and large enough to get better efficiency. When is on, all input voltage is applied to this resistor. The same requirements apply to, although the voltage applied to is determined by the controller supply level. The maximum value for can be calculated by: R 1 ln U C U C 2 U gd C gd Equation 2 is the minimum time Q2 is on. U gd is the Q2 threshold value. C gd is the capacitance gate-drain of Q2, and U is the minimum operational voltage. The minimum operational voltage for is given by: U Uin min Ud1 U d 2 Equation 3 U in min is the minimum supply level and U d1 and U d2 are voltage drops on diodes and, respectively. Adding a forcing transistor can accelerate the Q2 turn-on process but requires several discrete components and can be impractical. should be calculated to turn on in a reliable manner and, at the same time, prevent deep saturation. The following equation can be used: R 2 U U h l 2I be max 21min Equation 4 U be is the base-emitter voltage drop. h 2lmin is the minimum current transfer coefficient. I Rlmax is the maximum current when is turned on. Q2 Gate - Capacitance Because the switching frequency is high, transistor Q2 should have minimal gate - capacitance. Otherwise, it is necessary to decrease resistance, which then decreases the efficiency. This is only justified when large output currents are required, so be sure and choose Q2 according to the load current. Inductance Inductance should be set properly to prevent the circuit from going into discontinuous current operation. Although, it is not strictly necessary because the discontinuous current region is characterized by the increased level of output voltage ripples. The minimum inductance level can be calculated in two steps. The first step is to evaluate the minimum effective duty cycle D min : D min U U out in max Equation 5 U out is the required load voltage and U in max is the maximum supply voltage. Note that the maximum duty value is limited to 0.5 V by the generator s internal structure when it is working continuously. The second step is to estimate the minimum inductance: L min 1 D min 2I U l min f min Equation 6 I min is the minimum current consumption and f min is the minimum switching frequency defined as a gate comparator switching frequency. f min can be approximated. The base current is limited by to slow the turn-on of. This allows longer conduction time for Q2. The transformer loss calculation is not included in this analysis. There are static, P stat, and dynamic, P dyn, power losses. Pl Pstat P dyn Equation 7 Novmeber 15, 2010 Document No Rev. *A 3

4 Resistor, diode, and transistor Q2 are the main contributors to static losses. The Schottky diode has lower losses when compared to a more conventional silicon junction diode with the same current level and switching frequency. Q2 and selections are interrelated. A smaller value should be selected for a larger Q2 gate-drain capacitance. For low currents, the MOSFET with a low gate-drain capacitance value should be selected. This allows a greater value and reduces the power that dissipates on the resistor. To reduce loss for larger currents, a transistor with low ON state - resistance should be selected. Inductor resistance losses might be noticeable for larger currents. Thus, the inductor should be chosen according to the load current. Dynamic loses are primarily related to Q2 and can be reduced by adjusting the transistor switching time. For the proposed design, this is only possible by reducing the resistance values. Test Schematic In PSoC Designer Project, is enabled and trip voltage is set to 5.00 V in the global settings, (refer to the following figure). Figure 3. Global Resource Settings The following table lists the obtained characteristics. Table 1. Example Scheme Characteristics Parameter Input Voltage, Minimum Input Voltage, Maximum Output Voltage Output Current Maximum Output Current Minimum 10 V DC 16 V DC 5 V DC 125 ma 10 ma Value The schematic for the circuit with component values is shown in Figure 4. It is preferable to use a tantalum capacitor as С4 or increase capacitance to 1 uf when a conventional aluminum oxide capacitor is used for. Another design with the same topology is shown in Figure 5. A bipolar transistor is used in the role of the main current switch. Losses in the design shown in Figure 5 are less than those in the design shown in Figure 4 due to a larger value. However, the second design becomes less efficient as the load current increases. Note that increasing the resistance of leads to start-up problems when the voltage is less than 12 V. Figure 6 shows efficiency measurement results of the proposed regulator at various load currents and input voltages. The efficiency for an ideal linear regulator is provided for comparison. Novmeber 15, 2010 Document No Rev. *A 4

5 Figure 4. Regulator Test Schematic - Circuit 1 J N4148 C1 100uF 2.4k 0.22uF Q2 BS uH Mbm uF C4 20uF 10k CY8C***** V in 2N3904A Figure 5. Regulator Test Schematic - Circuit 2 J N4148 C1 100uF 3.3k 0.22uF Q2 2N uH Mbm uF C4 20uF 10k CY8C***** V in 2N3904A Novmeber 15, 2010 Document No Rev. *A 5

6 Figure 6. Switching and Ideal Linear Regulator Efficiency Curves for Different Load Currents Efficiency Iload=25mA Supply Voltage, V Cir1-25mA Lin Cir2-25mA Efficiency Iload=75mA Supply Voltage, V Cir1-75mA Lin Cir2-75mA Iload=125mA Efficiency Supply Voltage, V Cir1-125mA Lin It is appropriate to use the proposed switching regulator when load current is greater than 40 ma. Under these conditions, the switching regulator is more efficient than the linear regulator and is cheaper than using a buck regulator IC, although it is less efficient at energy conversion. Novmeber 15, 2010 Document No Rev. *A 6

7 Appendix: Converter Scope Images Several scope images for different load currents were collected. Figure 7. Signal Waveforms Source Q2 (Upper) and Base (Bottom) (a) Load Current: 25 ma As shown in Figure 7, the generator off-time is virtually the same for the different load currents, but on-time increases the load current. Figure 7(a) shows the discontinuous area for lower load currents. The off-time is primarily determined by the comparator signal propagation time. Figure 8 shows that the output voltage ripples slightly increased with the load current. (b) Load Current: 75 ma (c) Load Current: 125 ma Novmeber 15, 2010 Document No Rev. *A 7

8 Figure 8. Q2 Source Signal (Upper) Waveform and Output Voltage Ripples (Bottom) (a) Load Current: 25 ma (b) Load Current: 75 ma (c) Load Current: 125 ma Novmeber 15, 2010 Document No Rev. *A 8

9 About the Author Name: Andrey Magarita Title: Background: Contact: Sr. Application Engineer Andrey graduated from National University Lvivska Polytechnika (Lviv, Ukraine) in 1989 and presently works as Senior Application Engineer for a private company, Zuvs. He has more than 15 years experience in embedded systems design. makar@ltf.lviv.net Novmeber 15, 2010 Document No Rev. *A 9

10 Document History Document Title: Power Management Switch Mode Pump in a Step-Down Converter Using PSoC Document Number: Revision ECN Orig. of Change Submission Date Description of Change ** RJVB 09/24/07 New Application note. *A RJVB 11/15/10 1. Added more explanation with diagrams. 2. Removed unavailable references. 3. Added more PSoC devices in the associated Parts list. In March of 2007, Cypress recataloged all of its Application Notes using a new documentation number and revision code. This new documentation number and revision code (001-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all subsequent revisions. PSoC is a registered trademark of Cypress Semiconductor Corp. "Programmable System-on-Chip," PSoC Designer, and PSoC Express are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA Phone: Fax: Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Novmeber 15, 2010 Document No Rev. *A 10