150 μv Maximum Offset Voltage Op Amp OP07D

Transcription

1 5 μv Maximum Offset Voltage Op Amp OP7D FEATURES Low offset voltage: 5 µv max Input offset drift:.5 µv/ C max Low noise:.25 μv p-p High gain CMRR and PSRR: 5 db min Low supply current:. ma Wide supply voltage range: ±4 V to ±8 V operation PIN CONFIGURATIONS NULL 8 NULL IN 2 OP7D 7 V+ +IN 3 TOP VIEW (Not to Scale) 6 OUT V 4 5 NC NC = NO CONNECT Figure. 8-Lead SOIC_N (R-8), 8-Lead DIP (N-8) APPLICATIONS Medical and industrial instrumentation Sensors and controls Thermocouple RTDs Strain bridges Shunt current measurements Precision filters GENERAL DESCRIPTION The OP7D is a precision, ultralow offset amplifier. It integrates low power (. ma typical), low input bias current (± na maximum), and high CMRR/PSRR (3 db) in the small DIP package. Operation is fully specified from ±5 V to ±5 V supply. The OP7D provides higher accuracy than industry-standard OP7-type amplifiers due to Analog Devices ipolar process, which supports enhanced performance in a smaller footprint. These performance enhancements include wider output swing, lower power, and higher CMRR (common-mode rejection ratio) and PSRR (power supply rejection ratio). The OP7D maintains stability of offsets and gain virtually regardless of variations in time or temperature. Excellent linearity and gain accuracy can be maintained at high closed-loop gains. The OP7D is fully specified over the extended industrial temperature range of 4 C to +25 C. The OP7D amplifier is available in 8-lead DIP and the popular 8-lead, narrow SOIC lead-free packages. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 OP7D TABLE OF CONTENTS Features... Applications... General Description... Pin Configurations... Revision History... 2 Specifications... 3 Absolute Maximum Ratings...5 Thermal Resistance...5 ESD Caution...5 Typical Performance Characteristics...6 Outline Dimensions... 3 Ordering Guide... 4 REVISION HISTORY 2/ Rev. to Rev. A Changes to Output Voltage Swing Parameter... 4 Changes to Figure Updated Outline Dimensions... 3 Changes to Ordering Guide /5 Revision : Initial Version Rev. A Page 2 of 6

3 SPECIFICATIONS V S = ±5. V, T A = 25 C, unless otherwise specified. OP7D Table. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS 4 5 μv C T A 7 C 25 μv 4 C T A +25 C 35 μv Input Bias Current I B.2 na 4 C T A +25 C na Input Offset Current I OS. na 4 C T A +25 C na Input Voltage Range V Common-Mode Rejection Ratio CMRR V CM = ±3 V 2 27 db 4 C T A +25 C 2 db Open-Loop Gain A VO R L = 2 kω to ground, V O = ±3 V, V/mV 4 C T A +25 C V/mV Offset Voltage Drift V OS / T C T A 7 C.5.8 μv/ C 4 C T A +25 C.5.4 μv/ C OUTPUT CHARACTERISTICS Output Voltage Swing V OUT R L = kω to ground ±3.95 ±4. V 4 C T A +25 C ±3.95 V R L = 2 kω to ground ±3.9 ±4 V 4 C T A +25 C ±3.9 V Short-Circuit Current I SC 27 ma Output Current I O V O = 3.5 V 5 ma POWER SUPPLY Power Supply Rejection Ratio PSRR V S = ±4. V to ±8. V 5 3 db C T A 7 C 5 db 4 C T A +25 C db Supply Current/Amplifier I SY V O = V..25 ma C T A 7 C.45 ma 4 C T A +25 C.75 ma DYNAMIC PERFORMANCE Slew Rate SR R L = kω.2 V/μs Gain Bandwidth Product GBP.6 MHz Phase Margin 8 Degrees NOISE PERFORMANCE Voltage Noise e n p-p. Hz to Hz.28 μv p-p Voltage Noise Density e n f = khz nv/ Hz Current Noise Density i n f = khz.74 pa/ Hz Rev. A Page 3 of 6

4 OP7D V S = ±5 V, T A = 25 C, unless otherwise specified. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS 45 5 μv C T A 7 C 25 μv 4 C T A +25 C 35 μv Input Bias Current I B.2 na 4 C T A +25 C na Input Offset Current I OS.2 na 4 C T A +25 C na Input Voltage Range V Common-Mode Rejection Ratio CMRR V CM = ±3. V 2 4 db 4 C T A +25 C 2 db Open-Loop Gain A VO R L = 2 kω to ground, V O = ± V, V/mV 4 C T A +25 C V/mV Offset Voltage Drift V OS / T C T A 7 C μv/ C 4 C T A +25 C.5.5 μv/ C OUTPUT CHARACTERISTICS Output Voltage Swing V OUT R L = kω to ground ±3.95 ±4 V 4 C T A +25 C ±3.9 V R L = 2 kω to ground ±3.75 ±3.8 V 4 C T A +25 C ±3.7 V Short-Circuit Current I SC 3 ma Output Current I O V O = 3.5 V 5 ma POWER SUPPLY Power Supply Rejection Ratio PSRR V S = ±4. V to ±8. V 5 3 db C T A 7 C 5 db 4 C T A +25 C db Supply Current/Amplifier I SY V O = V..3 ma C T A 7 C.55 ma 4 C T A +25 C.85 ma DYNAMIC PERFORMANCE Slew Rate SR R L = kω.2 V/μs Gain Bandwidth Product GBP.6 MHz Phase Margin 8 Degrees NOISE PERFORMANCE Voltage Noise e n p-p. Hz to Hz.25 μv p-p Voltage Noise Density e n f = khz nv/ Hz Current Noise Density i n f = khz.74 pa/ Hz Rev. A Page 4 of 6

5 OP7D ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Input Voltage Differential Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, sec) Rating ±8 V ±V supply ±.7 V Indefinite 65 C to +5 C 4 C to +25 C 65 C to +5 C +3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θ JA is specified for worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Package Type θ JA θ JC Unit 8-Lead DIP (N-8) 3 43 C/W 8-Lead SOIC (R-8) C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A Page 5 of 6

6 OP7D TYPICAL PERFORMANCE CHARACTERISTICS NUMBER OF AMPLIFIERS V OS (µv) NUMBER OF AMPLIFIERS TCV OS (µv/ C) Figure 2. Number of Amplifiers vs. Offset Voltage Figure 5. Number of Amplifiers vs. TCV OS NUMBER OF AMPLIFIERS V OS (µv) V OS (µv) Figure 3. Number of Amplifiers vs. Offset Voltage Figure 6. Offset Voltage vs. Temperature NUMBER OF AMPLIFIERS 3 2 V OS (µv) TCV OS (µv/ C) Figure 4. Number of Amplifiers vs. TCV OS Figure 7. Offset Voltage vs. Temperature Rev. A Page 6 of 6

7 OP7D R L = kω I SY (ma). V OL (V) Figure 8. Supply Current vs. Temperature Figure. Negative Output Voltage Swing vs. Temperature R L = kω R L = kω V OH (V) 4.25 V OL (V) Figure 9. Positive Output Voltage Swing vs. Temperature Figure 2. Negative Output Voltage Swing vs. Temperature R L = kω V OH (V) I B (na) Figure. Positive Output Voltage Swing vs. Temperature Figure 3. Input Bias Current vs. Temperature Rev. A Page 7 of 6

8 OP7D.5 5 V S = ±4V TO ±8V..5 4 I B (na).2.25 PSRR (db) Figure 4. Input Bias Current vs. Temperature Figure 7. PSRR vs. Temperature CMRR (db) I SC (ma) Figure 5. CMRR vs. Temperature Figure 8. Short-Circuit Current vs. Temperature R L = 2kΩ A VO (V/mV) SUPPLY CURRENT (ma) Figure 6. Open-Loop Gain vs. Temperature SUPPLY VOLTAGE (V) Figure 9. Supply Current vs. Supply Voltage Rev. A Page 8 of 6

9 OP7D V OH = +V OUT 5 4 G = + V IN = 28mV R L = C L = 2pF V SY V OUT (V) V OL = V OUT CLOSED-LOOP GAIN (db) 3 2 G = + G = +... I LOAD (ma) Figure 2. Output Voltage Swing vs. Load Current k k k M Figure 23. Closed-Loop Gain vs. Frequency G = + V IN = 28mV R L = C L = 2pF V SY V OUT (V) V OL = V OUT V OH = +V OUT CLOSED-LOOP GAIN (db) 3 2 G = + G = +... I LOAD (ma) k k k M Figure 2. Output Voltage Swing vs. Load Current Figure 24. Closed-Loop Gain vs. Frequency GAIN GAIN 2 2 R L = C L = 2pF 4 ΦM = 8 k k k M M PHASE PHASE MARGIN (Degrees) OVERSHOOT (%) V IN = ±5mV G = + OS +OS C LOAD (nf) Figure 22. Open-Loop Gain and Phase vs. Frequency Figure 25. Overshoot vs. Capacitive Load Rev. A Page 9 of 6

10 OP7D OVERSHOOT (%) V IN = ±5mV G = + OS +OS R OUT (Ω) V IN = 28mV R L = C L = 2pF G = + G = + G = C LOAD (nf) Figure 26. Overshoot vs. Capacitive Load k k k M Figure 29. Output Impedance vs. Frequency V IN = 28mV R L = C L = 2pF CMRR (db) R OUT (Ω) G = + G = + G = k k k M Figure 27. CMRR vs. Frequency k k k M Figure 3. Output Impedance vs. Frequency PSRR PSRR (db) PSRR VOLTAGE NOISE DENSITY (nv/ Hz) k k k M Figure 28. PSRR vs. Frequency k Figure 3. Voltage Noise Density vs. Frequency Rev. A Page of 6

11 OP7D C L = nf G = + V IN = 4V p-p i n (pa/ Hz). OUTPUT VOLTAGE (V/DIV) 2.. k Figure 32. Current Noise Density vs. Frequency TIME (µs/div) Figure 35. Large-Signal Transient OUTPUT VOLTAGE (mv/div) 2 AND ±5V C L = nf G = + V IN = mv p-p 4mV 2mV V 2mV V 5V V V IN V OUT V IN = 2mV G = RECOVERY = µs 5V TIME (µs/div) V TIME (µs/div) Figure 33. Small-Signal Transient Figure 36. Positive Overload Recovery OUTPUT VOLTAGE (V/DIV) 2 C L = nf G = + V IN = 4V p-p 4mV 2mV V 2mV 5V V 5V V V IN V OUT V IN = 2mV G = RECOVERY = 5µs TIME (µs/div) V TIME (µs/div) Figure 34. Large-Signal Transient Figure 37. Negative Overload Recovery Rev. A Page of 6

12 OP7D 2mV 6mV V 6mV V 2V 4V V IN V OUT V IN = 6mV G = RECOVERY = 2.4µs VOLTAGE NOISE (.2µV/DIV) VN p-p =.24µV 6V 8V TIME (4µs/DIV) TIME (s/div) Figure 38. Positive Overload Recovery Figure 4. Voltage Noise (. Hz to Hz) 2mV 6mV V V IN V IN = 6mV G = RECOVERY = 5.6µs 6mV 4V 2V V V OUT INPUT 2 8 OP7D 2kΩ 7 6 V+ OUTPUT 2V V OS TRIM RANGE IS TYPICALLY ±3.5mV 4V TIME (4µs/DIV) V Figure 39. Negative Overload Recovery Figure 42. Optional Offset Nulling Circuit V IN = ±5.7V V IN V OUT 2 TIME (4µs/DIV) Figure 4. No Phase Reversal Rev. A Page 2 of 6

13 OP7D OUTLINE DIMENSIONS 5. (.968) 4.8 (.89) 4. (.574) 3.8 (.497) (.244) 5.8 (.2284).25 (.98). (.4) COPLANARITY. SEATING PLANE.27 (.5) BSC.75 (.688).35 (.532).5 (.2).3 (.22) 8.25 (.98).7 (.67).5 (.96).25 (.99).27 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 247-A.4 (.6).365 (9.27).355 (9.2).2 (5.33) MAX.5 (3.8).3 (3.3).5 (2.92).22 (.56).8 (.46).4 (.36) 8. (2.54) BSC 5.28 (7.).25 (6.35) 4.24 (6.).5 (.38) MIN SEATING PLANE.5 (.3) MIN.6 (.52) MAX.5 (.38) GAUGE PLANE.325 (8.26).3 (7.87).3 (7.62).43 (.92) MAX.95 (4.95).3 (3.3).5 (2.92).4 (.36). (.25).8 (.2).7 (.78).6 (.52).45 (.4) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 766-A Rev. A Page 3 of 6

14 OP7D ORDERING GUIDE Model Temperature Range Package Description Package Option OP7DNZ 4 C to +25 C 8-Lead PDIP N-8 OP7DRZ 4 C to +25 C 8-Lead SOIC_N R-8 OP7DRZ-REEL 4 C to +25 C 8-Lead SOIC_N R-8 OP7DRZ-REEL7 4 C to +25 C 8-Lead SOIC_N R-8 Z = RoHS Compliant Part. Rev. A Page 4 of 6

15 OP7D NOTES Rev. A Page 5 of 6

16 OP7D NOTES 25 2 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D5867 2/(A) Rev. A Page 6 of 6