Question 1: MOV AX, 3 MOV BX, [0300] ADD BX, AX (6 marks) Work out the time taken to execute: MOV AX, 2 MOV BX, 3 MUL BX ADD AX, BX

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1 Question 1: (a) (b) (c) Give a brief functional description of the Bus Interface Unit and of the Execution Unit in a CPU. Which of the following CPU internal registers would you expect to be assigned to the Bus Interface Unit and why: accumulator, instruction pointer, flag register, stack segment register. ( 5 marks) Using the DEBUG program you find that the content of two consecutive program memory locations starting at a location pointed by the IP register is FF and 61. List the possible interpretations of these two bytes which could be made by the CPU. Explain the fetch, decode and execute cycle with reference to the program fragment which uses registers AX and BX and a memory location with address 0300 : MOV AX, 3 MOV BX, [0300] ADD BX, AX (c) Work out the time taken to execute: MOV AX, 2 MOV BX, 3 MUL BX ADD AX, BX given that (i) when assembled into machine code, the first two instructions are 3 bytes long and the second two are 2 bytes long, (ii) the CPU clock is 12 MHz, (iii) four clock cycles are needed to fetch a word from a single memory location and (iv) and the MUL and ADD instructions each execute in 20 and 10 clock cycles, respectively. (8 marks) 1

2 Question 2: (a) (b) Having only access to the full list of machine instructions for a CPU, and no other information available, how would you tell whether that CPU has a memory or a port mapped I/O architecture? A micro computer system uses a CPU with a 8-bit wide program counter accessing a flat address space and having a memory mapped I/O architecture. What is the maximum number of I/O ports the system can have if the system memory consists of a 64 x 8 ROM and a 128 x 8 SRAM? (c) The 8086 microprocessor has two types of subroutine call instructions. What are they and how do they differ in terms of: (i) (ii) (iii) their functionality the machine code length the operating system s ability to relocate the code. (d) Explain the role of the memory stack in relation to the subroutine calls. What stack and program counter operations are performed by (i) the subroutine call instruction (ii) the return from subroutine instruction? (e) Most CPUs do not have an instruction that will load the current value of the program counter into the accumulator. Write a short subroutine which, on its return, will hold the current value of the program counter in the accumulator. (7 marks) 2

3 Question 3: (a) The 8088/86 microprocessor uses a segmented memory access. Explain why a flat memory access would violate the Intel s policy of backwards compatibility with the earlier16 bit address bus designs? What alternative to the segmented memory access could have been considered by Intel s designers without sacrificing the backward compatibility? (5 marks) (b) If the DS register contains 3AB5, which absolute location(s) in memory will be addressed by each of the following: (i) MOV BX, 2AB1 (ii) MOV BX, [1A9C] (iii) MOV CL, [BX] + 6 (iv) ADD AX, [BX] (8 marks) (c) Explain the following 8088/86 Addressing Modes and illustrate each by one possible application and giving an example of an instruction using each mode: (i) (ii) (iii) (iv) Question 4: register direct direct indexed base indexed (12 marks) (a) What is the maximum memory size that can be accessed with a 16-bit wide address bus? (b) Explain the terms Partial Address Memory Decoding and Full Address Memory decoding. What are their respective advantages and disadvantages? A memory map for a 16 bit address bus microcomputer system is shown below: Memory Range FF00h-FFFFh 0400h-FEFFh 0000h-03FFh Memory Type EPROM Not used SRAM Draw a possible circuit diagram, utilising suitable logic devices, that will enable : (c) Partial Address Memory Decode. (d) Full Address Memory Decode. (10 marks) 3

4 Question 5: (a) The 8086 microprocessor shares its sixteen data pins with the 16 lower address pins. Explain what is the role of the control pin ALE (Address Latch Enable) in providing the timing information enabling de-multiplexing of the shared data and address pins. (b) List the relevant control signals allowing the 8086 to perform a memory read bus cycle. Draw the timing diagram showing the state of address lines and data lines in relation to the clock cycles and the above identified control lines. (8 marks) (c) Explain the term wait state, what is it used for and how is it initiated? (d) Draw a simplified block diagram of the buffered system bus, assuming that the 8086 operates in the minimum mode. (7 marks) (e) In a microprocessor based computer system, explain the differences between the local bus and the system bus. Give an example of a standardised system bus used in a Personal Computer system and briefly describe its characteristics. (4 marks) Question 6: (a) Explain the difference between a polled I/O system and an Interrupt Driven I/O system. (4 marks) (b) List the sequence of events in a Vectored Interrupt system after a maskable interrupt has been received. Use an example of a 8086 based system. (4 marks) (c) Figure 6 shows an 8 digit common cathode LED display connected via the PPI 8255 to the Intel 8086 system bus. Write a short assembly code subroutine ( providing adequate comments) which will display a single bit of a byte held in the CPU s BL register. The order of the bit to be displayed, is held in the register DI. The bit shall be displayed as either 0 or 1 using the correct seven segment digit of the 8 digit LED. The relevant information on the PPI 8255 is provided below. (17 marks) Address Lines A 0 A Register Select 0 0 Port A 0 1 Port B 1 0 Port C 1 1 Control Register 4

5 8255 Control Word D4 D3 0 D1 D0 D0: Port C (lower) 1 = input 0 = output D1: Port B 1 = input 0 = output D3: Port C (upper) 1 = input 0 = output D4: Port A 1 = input 0 = output 5

6 Figure 6. End of Paper 6

7 Solutions: 1.a: BUI responsible for address and bus communications and memory addressing. EU decodes instructions and performs arithmetic and logic operations. EU has accumulator and flag register, BUI has Instruction Pointer and stack segment. (5 marks) 1b: The first byte has to be opcode or the first byte of opcode. The second byte is either opcode or an operand. 1.c: MOV AX, 3 - opcode is fetched from memory, decoded and 3 moved to AX MOV BX, [0300] - opcode and operand [300] is fetched and decoded, then the ADD BX, AX 1.d: 1 cycle = 1/(12x10 6 ) = 84 ns data in memory location 300 is fetched and moved to AX - opcode fetched from memory, addition executed in ALU instruction fetch time execution time Sub-total time MOV AX, 2 3x4x 84 ns ns MOV BX,3 3x4x84 ns ns MUL BX 2x4x84nS 20x84 ns 2352 ns ADD AX, Bx 2x4x84 ns 10x84 ns 1512 ns TOTAL : 5880 ns = 6 ms (8 marks) 2a: If instruction set includes IN port# and OUT port# instructions then the up is I/O port mapped. 2b: 8 bit PC with flat access can address 2 8 = 256 memory locations = Total address pace The address space available for I/O ports = Total address space implemented memory = = 64 ports possible 2c: The two subroutines are the Intra-segment CALL and the Inter-segment CALL Far. (i) CALL has a reach within the current segment max size 64k. CALL Far can reach the entire address space of 1M. (ii) CALL has a 2 byte operand which holds the current IP. CALL Far has four byte operand which holds the current IP and CS. (iii) CALL is relocatable whereas CALL far is not. 2d: (i) CALL pushes IP onto stack and updates it to point to the address of the subroutine (ii) RET pulls IP off the stack into the IP. 2 e: get_ip: PULL AX ; get the IP from the stack PUSH AX ; return the stack pointer to point to the IP ; otherwise the CPU will hang up RET (7 marks) 3a: Flat access to 1M memory requires 20 bit (2 20 = 1M) IP. The previous Intel CPUs had a 16 bit IP. Changing from 16 to 20 bit IP would make all previous software incompatible. With segmented access the IP reains 16 bit, so any program smaller than 64k runs as before. The alternative solution to segmented memory access is a paged memory access, whereby a 4-bit page register extends the IP addresses to 20 bits. (5 marks) 7

8 3b: (i) none: immediate mode (ii) 3AB50 + 1A9C = 3C1EC (iii) 3AB56 + [BX] (iv) 3AB50 + [BX] 3c: (8 marks) Addresing Mode Operand Format Example Register reg MOV AX, BX Direct disp MOV AX, Total Direct Indexed [SI]+ disp MOV AX, Total[SI] [DI]+ disp Base indexed [BX+ SI +disp] [BP + DI + disp] [BP + SI + disp] [BP + DI + disp] MOV AX, [BX+SI+3] 4a: 2 16 = bytes (12 marks) 4b: Partial Address Decoding does not use all the available memory address lines. Full Address Decoding involves decoding all the address lines: Advantages Disadvantages Partial Address Decode Easier to implement Creates ghost addresses in empty address space. These locations cannot be used for I/O port addresses. Full Address Decode Assigns unique addresses to the physical memory, so it allows utilisation of the unfilled address space for I/O port addresses. Requires more hardware to implement 4c: Because the address lines A 8 to A 15 are exclusive to EPROM the select EPROM/SRAM control can be derived by ANDing these lines. 4d: As before, the select EPROM will be obtained by ANDing the A 8 to A 15 lines. The address space for SRAM finishes at 03FF = so the SRAM select will be obtained by NORing the address lines A 10 to A 15. (10 marks) 8

9 5a: As the lower 16 address and data pins are shared ALE is a time multiplex strobe indicating that the A/D 0 to A/D 15 pins carry a valid address. 5 b: 9

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11 (8 marks) 5c: A wait state is one clock cycle inserted by the CPU to extend a machine bus cycle in order to allow more time for a device connected to the bus to read or write data. A wait state is initiated by the device deasserting the CPUs pin READY. 11

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14 (7 marks) 5e: Two buses explained: (i) ISA (Industry Standard Architecture) is the oldest of existing bus types, running at speeds of up to 8 MHz, providing 8-bit and 16-bit data transfers. (ii) PCI (Peripheral Component Interconnect) runs from 60MHz and offers 64-bit addressing and data transfers. (4 marks) 6a: With Poll driven I/O the CPU checks the state of the I/O at (hardware or software) predetermined intervals and if needed carries out the I/O operation. With Interrupt driven I/O the CPU carries on until it receives an I/O initiated interrupt and only then services that I/O. (4 marks) 6 b: Upon receipt of a NMI, the CPU completes the current instruction and then asserts the interrupt acknowledge pin to indicate that it expects the interrupting device to place a valid interrupt number. After getting the interrupt number, the 8086 consults the interrupt jump vector table in the memory to select the appropriate jump vector. The jump vectors point to the memory locations holding the starts of the service routines. Having serviced the interrupt, the CPU resumes the program execution with the instruction following the one at which it was interrupted. (4 marks) 6c: port_a EQU Ch ; binary address 1100 of Port A port_b EQU Dh ; binary address 1101 of Port B port_c EQU Eh ; binary address 1110 of Port C ctrl_r EQU Fh ; binary address 1111 of Control Register ctrl_w EQU 80h ; control word b, all ports configured outputs zero_dig EQU 3Eh ; zero digit: a=b=c=d=e=f=1 obtained from b one_dig EQU 30h ; one digit: b=c=1 obtained from b ; Table for logic masks to select the individual bits, starting from the lsb masks DB 01h ; mask to select the lsb DB 02h ; mask to select bit 1 DB 04h ; mask to select bit 2 DB 08h ; mask to select bit 3 DB 10h ; mask to select bit 4 DB 20h ; mask to select bit 5 DB 40h ; mask to select bit 6 DB 80h ; mask to select the msb ; Start of the subroutine display. The order of the bit to display held in BH, the byte to display in BL. display: MOV AX, ctrl_w ; configure ports OUT ctrl_r, AX MOV AX, BX AND AX, FFh MOV BX, masks[di] AND AX, BX ; Get the low byte holding the number ; into the AL ; Get the mask for the bit held in the DI ; Select the n-th bit in the AL 14

15 JZ zero ; If the n-th bit is not zero MOV AX, one_dig ; prepare the segment anodes OUT port_a, AX ; to display digit one JMP cathode ; Get ready to activate the cathode zero: MOV AX, zero_dig ; If the n-th bit is 0 prepare the segment anodes OUT port_a, AX ; to display digit zero cathode: MOV AX, DI ; Select the n-th digit cathode OUT port_c, AX ; and finally display the digit RET 15