Optimizing Power Consumption of Automotive Systems Requiring Periodic Wake Up

Transcription

1 June, 2007 Optimizing Power Consumption of Automotive Systems Requiring Periodic Wake Up AA303 Carl Culshaw, Automotive Systems Engineer Armin Winter, Automotive Field Applications Engineer

2 Agenda Introduction Low-Power Wake-up System Requirements Typical Application Timing Diagram Parameters Contributing to Current Consumption Typical Block Diagram Different Low Power Scenarios Low-Power Calculator Current Consumption Diagrams Low-Power Approaches Summary 1

3 Introduction Why is low-power management important? Car battery limitations: capacity, physical dimension, weight, cost, Number of Electronic Control Units (ECU s) in cars is constantly growing (E.g. BMW 7series -> ~70 ECU s) More and more ECU s need to be powered during the non-operational mode of the car (ignition off). OEMs specify an average standby current consumption of less than 300μA for each ECU, many of them going even further down to a requirement of less than 100 μa. To keep battery life at a maximum, smart concepts for power saving during standby mode are required! 2

4 Low-Power Wake-up System Requirements Cyclic wake-up ECU system requirements: Periodic wake-up to read analog inputs and/or refresh watchdog Wake-up on external event (switch detection) Very fast wake-up timings in order to save current or to operate an actuator very quickly (e.g. unlock door) BCM periodic LIN communication to trigger anti-theft unit Wake-up on CAN/LIN bus activity Blinking LED (e.g. VW door ) 3

5 Typical Application Timing Diagram I[mA] Tlin LIN Tsum (incl. Tosc) Tstop Trun Switches Switches Tosc Switches Osc start LIN HW (fix) t[ms] Tstop: Time while MCU is in low-power mode or switched off depending on low-power concept. Trun: Trun = MCU is in Run Mode, e.g. reading digital & analog Tosc: Oscillator start up time, plus time required to start SW execution (e.g. Clock quality check, RESET sequence). If MCU starts based on internal clock, Tosc = 0. Tlin: Duration of LIN communication. Tsum: Tstop + Tosc + Trun 4

6 The Power Problem 2 Elements to total power Dynamic Power Run Current Static Power Stop Current 5

7 The Power Problem - Dynamic Dynamic Power Basically caused by charging and discharging the gates of the millions of MOS transistors and their interconnects. 6

8 The Power Problem Dynamic cont d Current proportional to capacitance & switching speed Smaller technology = smaller transistors =smaller gates smaller capacitances = reduced power Increased frequencies = faster switching speeds larger currents = increased power Fortunately the reduced capacitance wins out over the faster switching speeds lower overall dynamic Power 7

9 The Power Problem - Static Static Power Static leakage is a result of leakage current due to the finite-resistance of the off transistors between power and ground that exist whenever power is applied to a CMOS circuit. Current highly dependent on the threshold voltage. As technology scales to ever smaller dimensions, supply voltage levels are likewise scaled. To improve circuit speed, the threshold voltages are also decreased. This decrease in threshold voltage results in an exponential increase in the sub threshold leakage current! Becoming a much larger part of the total power equation! 8

10 Static & Dynamic Power trends (Frequency fixed) The Power Problem - Trends Dynamic Power Static Technology shrinking 9

11 Parameters contributing to current consumption Current Consumption Dynamic Static Specified: System Architecture (Tsum, Trun, Tlin) Influenceable: ECU architecture On-chip auto wake-up timer & RC for fast wake-up Current consumption ma/mhz Clock gating / Clock distribution Avoiding glitches Self Timed Blocks Activity Reduction Bus frequency Algorithm Specified or fixed: Vdd Si technology Leakage Influenceable: Low leakage design Power gating RAM segmentation Multiple Supply Voltages (e.g. separate RAM Vreg) 10

12 Typical Block Diagram Vbat CAN LIN1 LIN2 System Basis Chip (SBC CAN/LIN) Vreg Wdog CAN P/L LIN P/L LIN P/L Keys Relay Drv. I/O Interface & Sensing SPI SPI MCU SPI Vbat Power Actuator Vbat Power Actuator Vbat Power Actuator Switch Detection IC (MSDI) 11

13 Scenario 1: SBC performs periodic wake-up Different Low-Power Scenarios pros: + SBC can manage different wake-up events, thus allowing the MCU to be unpowered in low-power modes + MCU does not contribute to low power consumption at all cons: - wake-up timing is longer (Vdd stabilization time, RESET timinig) have Vdd1=5V stable before releasing the reset - time needed for the oscillator of the MCU to start-up 12

14 Different Low Power Scenarios Cont d Scenario 2: MCU performs periodic wake-up pros: + faster recovery/start-up time + SBC in low-power mode can still manage wake-up events + SBC wake-up on current demand feature cons: - In idle state, two devices (SBC & MCU) contribute to power consumption 13

15 Different Low Power Scenarios Cont d Scenario 3: MSDI provides periodic wake-up pros: + faster recovery/start-up time. + SBC in low power mode can still manage wake-up events + SBC wake-up on current demand feature + Advantages compared to discrete solution: + Power Dissipation + Operating Voltage Range + Board Space Utilization + Number of Solder Joints + Ground Offset Protection + Quiescent Current with Wake up cons: - In idle state, three devices (SBC, MCU & MSDI) contribute to power consumption 14

16 Low-Power Calculator 15

17 Current Consumption Diagrams Current vs. Time Diagram I [ua] Tsum [ms] Scenario 1 Scenario 2 16

18 Current Consumption Diagrams Cont d Zoomed Current vs. Time Diagram 75 I[uA] Scenario 1 Scenario Tsum[ms] 17

19 Low-Power Approaches Technology Reduce Interconnect Capacitance Electro migration and Low - e Insulators SOI - Technologies ~ 25% total Capacitance Reduction DOS - Devices Combined Si - III/V-Semiconductors Speed Benefit allows Voltage Scaling Circuit Drive Parameterized Standard Cells Clock Distribution Buffer Insertion & Sizing Tolerable Skew Voltage Swing Reduction Energy Recovery CMOS Logic Avoiding Glitches Self Timed Blocks (asynchronous) Gate Resizing (parameterized std-cells) Gated Clock Activity Reduction Architecture (µc) Power Management Different operating modes Dynamic Voltage Scaling (Snug-ARM) To Cache or not to Cache Eliminate of Chip Communication Memory Partitioning/Cache Performance Oriented Clocking Dynamic Frequency Scaling (Snug-ARM) Algorithm Complexity Inherent Dissipation Implementation Overhead System Power Management Multiple Supply Voltages Clock Distribution Local Operation 18

20 Summary To keep battery life at a maximum, smart concepts for power saving during standby mode are required! In this presentation it is shown, which parameters have influence on power consumption, and how current consumption of an ECU requiring periodic wake-up can be optimized. The demonstrated xl-sheet calculator helps to compare different ECU architectures, taking application requirements as well as silicon capabilities into account. Freescale has the right technologies and device architectures in place to provide 1st class system solutions addressing today s and future low-power requirements! 19

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