UVM Based Verification of 10 Gigabit Ethernet Transmit

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1 IJIRST International Journal for Innovative Research in Science & Technology Volume 1 Issue 10 March 2015 ISSN (online): UVM Based Verification of 10 Gigabit Ethernet Transmit Bua Baker PG Student Department of Electronics & Communication Engineering Gujarat Technological University (GTU) Ahmedabad India Abstract The 10 Gigabit Ethernet Media Access Controller (MAC) typically transmits and receives data between a host workstation and an Ethernet network. The core purpose of the 10 Gigabit MAC is to guarantee that the Media Access regulations detailed in the IEEE802.3ae standard are met while transmitting a frame of data over Ethernet. While on the receive side, the Ethernet MAC will extract the different components of a frame and transfers them to higher applications through a FIFO interface [8]. The Universal Verification Methodology (UVM) offers the most excellent structure to attain coverage driven verification. The coverage driven verification combines automatic test generation, self-checking test benches and coverage metrics to significantly reduce the time spent verifying a Design Under Test (DUT) [2]. Keywords: Gigabit Ethernet MAC, UVM, Design under Test I. INTRODUCTION During the last decades, several verification methodologies have been developed to ease the process of ASIC verification designs. EDA tool vendors usually develop these methodologies which in most cases are not compatible with tools from different vendors [4]. With the introduction of the Open Verification Methodology (OVM) which supports the use of SystemVerilog testbenches, need for verification became more standardized and hence, OVM paved way for Universal Verification Methodology (UVM) which has become an official Accellera standard supported by all EDA tool vendors today[4]. This research presents UVM based Verification process and methodology using SystemVerilog, explains verification strategy and reuse of design environment with reference to verifying the 10 Gigabit Ethernet packets in an Ethernet Intellectual Property (IP) Core [4]. II. UNIVERSAL VERIFICATION METHODOLOGY (UVM) The Universal Verification Methodology (UVM) standard, developed by Accellera's Verification IP (VIP) Technical Subcommittee (TSC), is available as a Class Reference Manual accompanied by an open-source SystemVerilog base class library implementation and a User Guide. The UVM standard establishes a methodology to improve design and verification efficiency, verification data portability and tool, and VIP interoperability[2]. A. UVM Environment Overview: Fig. 1: UVM Environment Overview [1]. All rights reserved by 97

2 Fig. 2: Universal Verification Component (UVC) [1]. 1) Interface UVC: Generates stimulus for an interface (drive), observes interface activity (monitor) and is protocol specific (AXI, USB, etc). 2) Module UVC: It is key for verification and is module specific i.e. performs all device specific operation such as checking, coverage and is responsible for registers. 3) Virtual Sequencer/Sequence: In Interface UVC Sequencer, Sequences are protocol specific i.e. AXI, AHB, PCIe, etc while in Virtual Sequencer, Sequences are not protocol specific, does not deal with sequence items and Controls lower level sequences with virtual sequences i.e. often interface UVC Sequencers [1]. 4) Monitor: Gets transactions from collector or TLM interface, provides coverage, checking and makes transactions available for consumption. 5) Sequence Items: Is the basic building block for Stimulus generation and Coverage (can be data, address, delay, constraints, etc), provides lowest level transaction and can be combined into a sequence. 6) Sequence: Builds transaction from sequence items, builds higher level transaction from sequences and coordinates execution of its items/sub-items 7) Driver: Requests sequence items from sequencer and drives sequence items into interface. When operating on RTL model interface, Converts transactions level to signal level and has a virtual interface to connect to DUT interface 8) Sequencer: Sequencer (producer) creates the stimulus and sends sequence items to driver (consumer). It uses TLM port for connection (Sequencer Driver) and handshake (Sequencer Driver) during communication. 9) Agent: Configures and instantiates subcomponents (Driver, Sequencer, Monitor, Collector) and establishes port connections. Agent can be of types: - RX/TX (Point to Point) and master/slave (Arbitration). 10) Environment: This is the top level of a UVC (Container module/class which has all subcomponents). It is used to configure UVC for application i.e. # agent, agent type, monitor/collector, connections, etc. 11) Scoreboard: Receives transactions from interface UVCs and checks transactions for expected device behaviour. It is likely to include an abstract reference model and is located inside module UVC. 12) DUT Functional Coverage: These are mostly devices specific in terms of their dimensions and operation. 13) Test Bench: The testbench contains all sub-components in which their configuration is done according to a particular need. Connections are provided for exchange of information. 14) Test: The test contains Testbench, configures traffic which is its main purpose and may adjust testbench topology. It gets created in RTL top level and is selected at the simulator command line to provide flexibility [1]. B. The Basic Principles of UVM: 1) Functionality encapsulation: UVM promotes composition and reuse by encapsulating functionality in a basic block called ovm_component. This basic block contains a run task i.e. a functional block that can consume time that acts as an execution thread responsible for implementing functionality as simulation progress [2]. All rights reserved by 98

3 2) Transaction-Level Modeling (TLM): UVM uses TLM standard to describe communication between verification components in a UVM environment. One of the main advantages of using TLM is in abstracting the pin and timing details. A transaction, the unit of information exchange between TLM components, encapsulates the abstract view of stimulus that can be expanded by a lower-level component. 3) Using Sequences For Stimulus Generation: The transactions need to be generated by an entity in the verification environment. UVM allows for flexibility by introducing ovm_sequence, which is a wrapper object around a function called body(). uvm_sequence when started, registers itself with a uvm_sequencer which is a uvm_component that acts as the holder of different sequences and can connect to other uvm_components. The uvm_sequence and uvm_sequencer pair provides the flexibility of running different streams of transactions without having to change the component instantiation [2]. 4) Configurability: An enabler to productivity and reuse, is a key element in UVM. In UVM, user can change the behaviour of an already instantiated component by three means: configuration API, Factory overrides and callbacks. 5) Layering: Layering is a powerful concept in which every level takes care of the details at specific layers. UVM layering can be applied to components which can be called hierarchy and composition, and to configuration and to stimulus. Typically there is a correspondence between layering of components and objects. Layering stimulus, on the other hand, can reduce the complexity of stimulus generation [2]. 6) Emphasis On Reuse (Vertical And Horizontal): Extensibility, configurability and layering facilitate reuse. Horizontal reuse refers to reusing Verification IPs (VIPs) across projects and vertical reuse describes the ability to use block-level VIPs in cluster and chip level verification environments. III. IMPLEMENTATION OF TRANSMIT MAC DESIGN This research document explains the design of the transmit MAC used in the Opencores 10 Gigabit Ethernet project. 10 Gigabit Ethernet is part of the IEEE standard. It is essentially a faster version of the Ethernet where full duplex operation mode is supported. The MAC design is loosely based on the Xilinx LogiCORE 10-Gigabit Ethernet MAC, where the transmitter and the receiver incorporate the reconciliation layer. Therefore the transmit MAC will be specifically designed to interface the client and the physical layer [6]. A. Detailed Transmit module Design: The transmit MAC provides the interface between the client and physical layer. Figure 2 shows a block diagram of the transmit MAC with the interfaces to the client, physical, management and the flow control[3]. Fig. 3: Diagram of the Transmit Block All rights reserved by 99

4 B. Module Design: The transmit MAC contains the following blocks such as input and output FIFO/register, control logic and counters. The input and output FIFO/registers are used to receive data from the client and distribute the data to the physical. All data flow is all under controlled from the control logic. Fig. 4: IEEE 802.3x Frame The tx_ack signal is generated using a type of counter circuitry to compensate when paused frame transmission is invoked by the flow control block or the inter frame delay is set at the start. The assertion of the signal is achieve when the count equal to the delay value. The request from the pause or inter frame will be used to select the counter delay value. The minimum inter frame gap is 96 bits. For a normal transmission, the delay value will be 2 clock cycles [3]. C. Description of the State MachineL A basic block diagram for a normal transmission with FCS supplied. Fig. 5: Block diagram of the transmit process [3]. The control logic is essentially a state machine that controls how the data is output to the physical by selecting between the control bytes and the client data. 1) State Machine Description: IDLE: continue transmitting IDLEs until tx_ack is received. START: transmit the first 64 bit data. This includes start control byte, six preambles and Start Frame Delimiter. DATA: Load data from FIFO. Also check when tx_data_valid is equal to zero, load terminates and IDLE bytes at the appropriate section. PAUSE: Transmit PAUSE Frame. (Need to figure out how to do parallel CRC). D. Detailed Testbench Environment: Fig. 6: Detailed Testbench Architecture All rights reserved by 100

5 IV. RESULT A. Packet Transmit Interface: Fig. 7: Packet Transmit Interface Waveforms Figure 7 above shows a normal transmission from the client-side. FCS has to be generated if it is not included with the data from the client-side. If the data width is below 46 bytes, padding is needed to bring it in line with the minimum frame size. A parallel scheme has to be employed to generate the FCS. B. Packet Receive Interface: Fig. 8: Packet Receive Interface Waveforms V. CONCLUSION This research work presents an overview of the Universal Verification Methodology and its basic principles. Verification is the most essential component in the ASIC and FPDG VIPs designs. Universal Verification Methodology (UVM) is one of the most prominent Verification Methodology for verifying complex VIPs. 10 Gigabit Ethernet Transmit MAC is analyzed with its protocol verified based on the normal testing methods using the test benches. UVM is used to improve the test coverage and its verification environment can be reused for the projects. ACKNOWLEDGEMENT Gujarat Technology University (GTU), CDAC ACTS Pune and Mr. Ashish Prabhu for the support, expertise, resources and contribution towards this research work. REFERENCES [1] [2] Verification Methodology Manual - Janick Bergeron [3] [4] UVM User Guide manual [5] 10G Ethernet Mac System Design Issue 1.0 [6] Xilinx LogiCORE 10-Gigabit Ethernet MAC User Guide [7] IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation [8] [9] [10] All rights reserved by 101