Advanced-Packaging Memory Solutions Targeting High Performance Applications. ConFab 2015 SK hynix

Transcription

1 Advanced-Packaging Memory Solutions Targeting High Performance Applications ConFab 2015 SK hynix

2 Agenda Announcement Developments in Packaging Technology Memory ICs Challenges Addressed by TSV Memory Solutions Utilizing TSV Technology Page 1

3 Mass Production of the World 1 st HBM SK hynix completed the qualification for mass production in March 2015 SK hynix World-First HBM Products System Level Test Environment Worldwide first HBM provider Mass Production start from Apr 2015 HBM2 design wins in progress with major SoCs in multiple market segments SK hynix in-house test board for HBM HBM (Bottom View) (Top View) (Section View) Page 2

4 General Memory Requirements Each application has different memory requirement, but most common are high bandwidth and density based on real time random operation. HPC Density Power Latency Density Power Graphics Real time Based Random Operation Networking Latency Power Datacenter Power Latency Page 3

5 Increasing Demand for Packaging Technology Packaging Technology becomes a key enablement for high performance, small form factor and low cost solution 8G-P WIO2 Mono QDP 0.52T LGA 16DP 1.2T emmc ODP 1.2T 3DS Omega CSP LGA ODP 0.8T FOD Dual emmc ODP 1.2T WLCSP LGA 16DP 1.2T SDP F/C 3DS QDP(128GB) WIO2 2high Fan-out WLP SiP & TSV can support multi-functional solution HBM Gen1 4high HBM Gen2 8high LGA ODP 0.6T DDP 0.43T Page 4

6 History of SK Hynix Packaging Technology Development Reliable memory supplier with advanced packaging technologies Advanced Technology Embedded Package 0.235T (E/S, ) 20 nm HBM1 5mKGSD using TSV (C/S, ) Fan-out 3DS ( ) 2GB DDR2 Wafer level package Memory Module (2007.1) 4GB DDR2 Wafer level package Memory Module ( ) 2Stack Wafer level Package using TSV (E/S, ) 40 nm 2Gb DDR3 8stack using TSV (E/S, ) WIO1 4KGSD (E/S, ) WLCSP 0.37T (E/S, ) 128GB DDR4 Module using TSV (2014.3) WIO2 Mobile DRAM (4x Faster) using TSV (2014.9) Fan-out WLP ( ) Conventional Technology 24Stack 1.4T NAND (M/S, ) 8Stack NAND (C/S, ) 40 nm 2Gb LPDDR2 (2010.1) 30 nm 4Gb DDR3 ( ) The Highest density 8Gb LPDDR3 (2013.6) 20 nm 8Gb LPDDR4 ( ) 16Stack NAND (E/S, ) 32Stack NAND (E/S, ) *Developing Page 5

7 SK hynix TSV Technology TSV combines the benefits of LGA and Flip Chip technologies SK hynix TSV development experiences have resulted in mass production of HBM1 SK hynix TSV chronicle SK hynix s Plan on year 2015 Volume Production of HBM1 08 4Gb Flash 10 4Gb DRAM DDP-WLP 11 16Gb DRAM 9MCP HBM2 Universal Daisy Chain 9mKGSD HBM2 Development 11 16/32GB DIMM 11 4hi KGSD WIO 13 5mKGSD HBM 15 9mKGSD HBM2 D/C Page 6

8 HBM1 HBM2 Technology Challenges : HBM utilizes TSV technology to overcome DRAM bandwidth challenges Challenges High B/W with many I/O 10 (Gb/s) 8 LPSDR LPDDR LPDDR GDDRx LPDDRx DDRx GDDR6(?) (Gb/s) 8 Max (GB/s) B/W per Pin (Gbps) (GB/s) 300 LPDDR3 6 6 LPDDR4 DDR1 LPDDR5(?) DDR2 DDR3 DDR4 DDR5 (?) GDDR GDDR DDR3(x8) GDDR5(x32) 4Hi HBM1(x1024) 4Hi HBM2(x1024) 0 (Source : SK hynix) Page 7

9 HBM1 Normalized DDR256 = 100% Technology Challenges : Power Efficiency Optimized-Speed/pin and Cio of HBM reduces power consumption and increase power efficiency Power Efficiency Power Consumption@128GB/s 100% 80% DDR 256Mb -57% DDR DDR2 DDR3 DDR4 Gbps (Watt) GDDR5 DDR3 DDR4 HBM1 7.0Gbps(x32) 2.0Gbps(x16) 2.0Gbps(x16) 1.0Gbps(x1K) % % DDR2 1Gb -79% % DDR3 4Gb DDR4 4Gb 0% (Source : SK hynix) Page 8

10 Small Form Factor with TSV 1TBps Implementations. 40ea of DDR Module is needed Only 1ea of 50mmx50mm SiP is needed 160ea of DDR is needed Page 9

11 System & Memory Architecture Projection B/W B/W & Capacity HPC & Server (B/W & Capacity) Solution Solution Capacity Solution Network & Graphics (B/W) B/W HBM Solution B/W B/W & Cost Client-DT & NB (B/W & Cost) + + Post- DDR4 Solution Post- DDR4 Cost Solution Mobile & Wearable (LP, Small Form Factor, B/W & Cost) LP & B/W LP & Solution Page 10

12 HBM2 Product Configurations 8 Cores Base die 4 Cores 2 Cores 8Gb based 9mKGSD 5mKGSD 3mKGSD Density/Cube (GB) 8GB 4GB 2GB IO Speed/pin (Gbps) (GB/s) Usage HPC, Server HPC, Server, Graphics, Network Graphics, Cache Config. / system 8 / 6 / 4 Cube 4 / 2 / 1 Cube 2 / 1 Cube Page 11

13 DDR4 3DS for Server The highest memory density with high bandwidth requires 3D technology Interconnection paradigm shift; from W/B to TSV 100% Server Module Capacity Projection W/B TSV 80% 60% 40% 16GB (4Gb based) DDR3 (1,866Mbps) 32GB (8Gb based) DDR3 (1,866Mbps) DDR3 (1,066Mbps) 64GB (16Gb based) DDR4 (2,667Mbps) 128GB (32Gb based) DDR4 (2,667Mbps) 20% 0% E 2015E 2016E 2017E 2018E 2019E 2020E 2021E SDP RDL DDP RDL QDP 3DS QDP Mass Production 1Q 12 CS Release, 4Q 12 Mass Qual. Release 4Q 12~ Mass Production DDR3 4Gb based DDP 3Q 13 CS Release, 4Q 13 Mass Qual. Release Dec. 13~ Mass Production DDR3 4Gb based QDP CS available in 3Q 15 DDR4 4/8Gb based QDP *Source: SKH computing marketing *Speed: module based (RDIMM) Page 12

14 3DS (3-Dimensional Stacking) 3D stacked memory packaging is ready for C/S 2y nm 8Gb, SKH s 1 st 3DS tech-integrated mass product is available in September 15 as CS Status Long Term Roadmap y nm (3DS QDP) Q3 C/S, 32Gb(8GbX4, 1.2t) Q2 2z nm (Fan-out 3DS) C/S, 32Gb(8GbX4, 0.7t) SK hynix will release 128GB LRDIMM C/S in Apr znm 8Gb 4-hi stack 3DS is under package level reliability test. Q2 E/S, 64Gb(8GbX8, 1.0t) *C/S based Page 13

15 Further work for TSV Technology Advanced TSV Technology Fine pitch TSV design aligning with DRAM technology scale Significant Cost Reduction Productivity improvement, Advanced equipment, Test Time Reduction, etc. Improvement of stacking technology 14 Page 14

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