description/ordering information

Transcription

1 2-V to 6-V V CC Operation ( HC45) 4.5-V to 5.5-V V CC Operation (CD74HCT45) High- Sourcing Capability 7.5 ma at 4.5 V (CD74HCT45) 0 ma at 6 V ( HC45) Latches for BCD Code Storage Lamp Test and Blanking Capability Balanced Propagation Delays and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC45 High Noise Immunity, N IL or N IH = 30% of V CC at V CC = 5 V CD74HCT45 Direct LSTTL Logic Compatibility, V IL = 0.8 V Maximum, V IH = 2 V Minimum CMOS Compatibility, I I µa at V OL, V OH description/ordering information CD54HC45...F PACKAGE CD74HC45... E, M, OR PW PACKAGE CD74HCT45...E PACKAGE (TOP VIEW) BCD s BCD s D D 2 LT BL D 3 D 0 GND V CC f g a b c d e 7-Segment s a f g b e DISPLAY d c The CD54HC45, CD74HC45, and CD74HCT45 are BCD-to-7 segment latch/decoder/drivers with four address inputs (D 0 D 3 ), an active-low blanking (BL) input, lamp-test (LT) input, and a latch-enable () input that, when high, enables the latches to store the BCD inputs. When is low, the latches are disabled, making the outputs transparent to the BCD inputs. These devices have standard-size output transistors, but are capable of sourcing (at standard V OH levels) up to 7.5 ma at 4.5 V. The HC types can supply up to 0 ma at 6 V. TA 55 C to 25 C ORDERING INFORMATION PACKAGE PDIP E Tube of 25 Tube of 40 ORDERAB PART NUMBER CD74HC45E CD74HCT45E CD74HC45M TOP-SIDE MARKING CD74HC45E CD74HCT45E SOIC M Reel of 2500 CD74HC45M96 HC45M Reel of 250 CD74HC45MT TSSOP PW Reel of 250 CD74HC45PWT HJ45 Reel of 2000 CD74HC45PWR CDIP F Tube of 25 CD54HC45F3A CD54HC45F3A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated

2 function diagram FUNCTION TAB INPUTS OUTPUTS BL LT D3 D2 D D0 a b c d e f g DISPLAY X X L X X X X H H H H H H H 8 X L H X X X X L L L L L L L Blank L H H L L L L H H H H H H L 0 L H H L L L H L H H L L L L L H H L L H L H H L H H L H 2 L H H L L H H H H H H L L H 3 L H H L H L L L H H L L H H 4 L H H L H L H H L H H L H H 5 L H H L H H L L L H H H H H 6 L H H L H H H H H H L L L L 7 L H H H L L L H H H H H H H 8 L H H H L L H H H H L L H H 9 L H H H L H L L L L L L L L Blank L H H H L H H L L L L L L L Blank L H H H H L L L L L L L L L Blank L H H H H L H L L L L L L L Blank L H H H H H L L L L L L L L Blank L H H H H H H L L L L L L L Blank H H H X X X X X = Don t care Depends on BCD code previously applied when = L NOTE: Display is blank for all illegal input codes (BCD > HLLH). LT 3 BCD s D0 D D2 D3 BL Latch Decoder Driver a b c d e f g 7-Segment s VSS = 8 VDD = 6 2

3 logic diagram BL 4 3 a D3 6 D Latch 2 b D2 2 D c Latch 0 d D D Latch 9 e D0 7 D Latch 5 f 5 3 LT 4 g 3

4 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, V CC V to 7 V diode current, I IK (V I < 0.5 V or V I > V CC V) ) (see Note ) ±20 ma diode current, I OK (V O < 0.5 V or V O > V CC + 0.5V) (see Note ) ±20 ma Continuous output source or sink current per output, I O (V O = 0 to V CC ) ±25 ma Continuous current through V CC or GND ±50 ma Package thermal impedance, θ JA (see Note 2): E package C/W M package C/W PW package C/W Lead temperature (during soldering): At distance /6 ± /32 in (.59 ± 0.79 mm) from case for 0 s maximum C Unit inserted into a PC board (minimum thickness /6 in,.59 mm), with solder contacting lead tips only C Storage temperature, T stg to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 5-7. recommended operating conditions for HC45 (see Note 3) TO 25 C MIN MAX MIN MAX MIN MAX Supply voltage V = 2 V VIH High-level input voltage = 4.5 V V = 6 V = 2 V VIL Low-level input voltage = 4.5 V V = 6 V VI voltage V VO voltage V = 2 V tt transition (rise and fall) time = 4.5 V ns = 6 V NOTE 3: All unused inputs of the device must be held at or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS s, literature number SCBA004. 4

5 recommended operating conditions for CD74HCT45 (see Note 4) TO 25 C MIN MAX MIN MAX MIN MAX Supply voltage V VIH High-level input voltage V VIL Low-level input voltage V VI voltage V VO voltage V tt transition (rise and fall) time ns NOTE 4: All unused inputs of the device must be held at or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS s, literature number SCBA004. HC45 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL TO 25 C MIN MAX MIN MAX MIN MAX 2 V IOH = 20 µa 4.5 V V V IOH = 7.5 ma 4.5 V IOH = 0 ma 6 V V IOL = 20 µa 4.5 V V V IOL = 4 ma 4.5 V IOL = 5.2 ma 6 V II VI = or 0 6 V ±0. ± ± µa ICC VI = or 0, IO = 0 6 V µa Ci pf 5

6 CD74HCT45 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL IOH = 20 µa IOH = 4 ma IOL = 20 µa IOL = 4 ma 4.5 V 4.5 V TO 25 C MIN TYP MAX MIN MAX MIN MAX II VI = to GND 5.5 V ±0. ± ± µa ICC VI = or 0, IO = V µa ICC One input at 2. V, Other inputs at 0 or 4.5 V to 5.5 V µa Ci pf Additional quiescent supply current per input pin, TTL inputs high, unit load. For dual-supply systems, theoretical worst-case (VI = 2.4 V, = 5.5 V) specification is.8 ma. V V HCT INPUT LOADING TAB INPUT LOADS LT,.5 BL, Dn 0.3 Unit load is ICC limit specified in electrical characteristics table, e.g., 360 µa maximum at 25 C. HC45 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure ) TO 25 C MIN MAX MIN MAX MIN MAX 2 V tw Pulse duration, low 4.5 V ns 6 V V tsu Setup time, BCD inputs before 4.5 V ns 6 V V th Hold time, BCD inputs before 4.5 V ns 6 V

7 HC45 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure ) PARAMETER tpd FROM TO LOAD (INPUT) (OUTPUT) CAPACITANCE Dn BL LT TO 25 C MIN TYP MAX MIN MAX MIN MAX 2 V CL = 50 pf 4.5 V V CL = 5 pf 5 V 25 2 V CL = 50 pf 4.5 V V CL = 5 pf 5 V 23 2 V CL = 50 pf 4.5 V V CL = 5 pf 5 V 8 2 V CL = 50 pf 4.5 V V CL = 5 pf 5 V 3 2 V tt Any CL = 50 pf 4.5 V ns 6 V ns 7

8 CD74HCT45 timing requirements over recommended operating free-air temperature range V CC = 4.5 V (unless otherwise noted) (see Figure 2) TO 25 C MIN MAX MIN MAX MIN MAX tw Pulse duration, low ns tsu Setup time, BCD inputs before ns th Hold time, BCD inputs before ns CD74HCT45 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM TO LOAD (INPUT) (OUTPUT) CAPACITANCE Dn BL LT TO 25 C MIN TYP MAX MIN MAX MIN MAX CL = 50 pf 4.5 V CL = 5 pf 5 V 25 CL = 50 pf 4.5 V CL = 5 pf 5 V 23 CL = 50 pf 4.5 V CL = 5 pf 5 V 8 CL = 50 pf 4.5 V CL = 5 pf 5 V 3 tt Any CL = 50 pf 4.5 V ns ns operating characteristics, V CC = 5 V, T A = 25 C Cpd Power dissipation capacitance Cpd is used to determine the dynamic power consumption, per package. PD = Cpd 2 fi + CL 2 fo where: fi = input frequency fo = output frequency CL = output load capacitance = supply voltage PARAMETER TYP HC45 4 CD74HCT45 0 pf 8

9 PARAMETER MEASUREMENT INFORMATION HC45 PARAMETER S S2 From Under Test CL (see Note A) Test Point RL = kω S S2 tpzh ten tpzl tphz tdis tplz tpd or tt LOAD CIRCUIT tw PULSE DURATION CLR CLK trec Reference Data 50% tsu th 90% 90% tr tf RECOVERY TIME SETUP AND HOLD AND INPUT RISE AND FALL TIMES In-Phase Out-of-Phase tplh 50% tphl 90% 90% 90% tf PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr tphl 50% tf tplh 90% tr Control Waveform (see Note B) Waveform 2 (see Note B) NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tplz and tphz are the same as tdis. G. tpzl and tpzh are the same as ten. H. tplh and tphl are the same as tpd. tpzl tpzh Figure. Load Circuit and Voltage Waveforms 90% OUTPUT ENAB AND DISAB TIMES tplz tphz 9

10 PARAMETER MEASUREMENT INFORMATION CD74HCT45 PARAMETER S S2 From Under Test CL (see Note A) Test Point RL = kω S S2 tpzh ten tpzl tphz tdis tplz tpd or tt LOAD CIRCUIT tw PULSE DURATION CLR CLK trec Reference Data 50% tsu th 90% 90% tr tf RECOVERY TIME SETUP AND HOLD AND INPUT RISE AND FALL TIMES In-Phase Out-of-Phase tplh 50% tphl 90% 90% 90% tf PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr tphl 50% tf tplh 90% tr Control Waveform (see Note B) Waveform 2 (see Note B) NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tplz and tphz are the same as tdis. G. tpzl and tpzh are the same as ten. H. tplh and tphl are the same as tpd. tpzl tpzh Figure 2. Load Circuit and Voltage Waveforms 90% OUTPUT ENAB AND DISAB TIMES tplz tphz 0

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12 MPDI002C JANUARY 995 REVISED DECEMBER N (R-PDIP-T**) 6 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE DIM PINS ** A A MAX (9,69) (9,69) (23,37).060 (26,92) 6 9 A MIN (8,92) (8,92) (2,59) (23,88) (6,60) (6,0) C MS-00 VARIATION AA BB AC AD (,78) (,4) D (,4) (0,76) D (0,5) MIN (8,26) (7,62) 0.05 (0,38) (5,08) MAX Gauge Plane Seating Plane 0.25 (3,8) MIN 0.00 (0,25) NOM 0.02 (0,53) 0.05 (0,38) 0.00 (0,25) 0.00 (2,54) M (0,92) MAX 4/8 PIN ONLY 20 pin vendor option D /E 2/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00, except 8 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

13 MECHANICAL DATA MSOI002B JANUARY 995 REVISED SEPTEMBER 200 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN (,27) (0,5) 0.04 (0,35) 0.00 (0,25) (6,20) (5,80) (0,20) NOM 0.57 (4,00) 0.50 (3,8) Gage Plane 4 A (0,25) (,2) 0.06 (0,40) Seating Plane (,75) MAX 0.00 (0,25) (0,0) (0,0) DIM PINS ** A MAX 0.97 (5,00) (8,75) (0,00) A MIN (4,80) (8,55) (9,80) /E 09/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed (0,5). D. Falls within JEDEC MS-02

14 MECHANICAL DATA MTSS00C JANUARY 995 REVISED FEBRUARY 999 PW (R-PDSO-G**) 4 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,0 M 0, ,50 4,30 6,60 6,20 0,5 NOM Gage Plane A ,25 0,75 0,50,20 MAX 0,5 0,05 Seating Plane 0,0 DIM PINS ** A MAX 3,0 5,0 5,0 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 0/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53

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