LOW POWER DISSIPATION ADSL LINE DRIVER

Transcription

1 THS6 SLLS544E SEPTEMBER REVISED JULY 3 LOW POWER DISSIPATION ADSL LINE DRIVER FEATURES Low Power Dissipation Increases ADSL Line Card Density Low THD of dbc (-Ω, MHz) Low MTPR Driving + dbm on the Line 6 dbc With High Bias Setting 4 dbc With Setting Wide Output Swing of 44V PP Differential Into a Ω Differential Load (V CC = ± V) High Output Current of 6 ma (Typ) Wide Supply Voltage Range of ±5 V to ± V Pin Compatible With EL3C and ELC Multiple Package Options Multiple Power Control Modes ma/ch Mode.5 ma/ch Mode 4 ma/ch Mode.5 ma/ch Shutdown Mode I ADJ Pin for User Controlled Bias Current Stable Operation Down to ma/ch Low Noise for Increased Receiver Sensitivity 3. nv/ Hz Voltage Noise.5 pa/ Hz Noninverting Current Noise pa/ Hz Inverting Current Noise APPLICATIONS Ideal for Full Rate ADSL Applications DESCRIPTION The THS6 is a current feedback differential line driver ideal for full rate ADSL systems. Its extremely low power dissipation is ideal for ADSL systems that must achieve high densities in ADSL central office rack applications. The unique architecture of the THS6 allows the quiescent current to be much lower than existing line drivers while still achieving very high linearity without the need for excess open loop gain. Fixed multiple bias settings of the amplifiers allow for enhanced power savings for line lengths where the full performance of the amplifier is not required. To allow for even more flexibility and power savings, an I ADJ pin is available to further lower the bias currents while maintaining stable operation with as little as ma per channel. The wide output swing of 44 V pp differentially with ±V power supplies allows for more dynamic headroom, keeping distortion at a minimum. With a low 3. nv/ Hz voltage noise coupled with a low pa/ Hz inverting current noise, the THS6 increases the sensitivity of the receive signals, allowing for better margins and reach. Typical ADSL CO Line Driver Circuit Utilizing Active Impedance kω +V CODEC V IN+ + THS6a V.33 kω.6 Ω :. + dbm Line Power 53 Ω.33 kω Ω kω +V CODEC V IN + THS6b.6 Ω V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 3, Texas Instruments Incorporated

2 THS6 SLLS544E SEPTEMBER REVISED JULY 3 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage. ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE SYMBOL TA ORDER NUMBER TRANSPORT MEDIA THS6RHF Leadless 4-pin 4 mm x 5 mm PowerPAD RHF 4 6 THS6RHFR THS6RHFT Tape and reel (3 devices) Tape and reel (5 devices) THS6D SOIC D THS6 4 Cto5 C THS6D THS6DR Tube (4 devices) Tape and reel (5 devices) THS6DW SOIC DW THS6 THS6DW THS6DWR Tube (5 devices) Tape and reel ( devices) PACKAGE DISSIPATION RATINGS() PACKAGE PowerPAD SOLDERED() ΘJA PowerPAD NOT SOLDERED(3) ΘJA RHF-4 3 C/W 4 C/W. C/W D- 6. C/W 5. C/W DW C/W.4 C/W () ΘJA values shown are typical for standard test PCBs only. () For high power dissipation applications, use of the PowerPAD package and soldering the PowerPAD to the PCB is required. Failure to do so may result in reduced reliability and/or lifetime of the device. See TI technical brief SLMA for more information about utilizing the PowerPAD thermally enhanced package. (3) Use of packages without the PowerPAD or not soldering the PowerPAD to the PCB, should be limited to low-power dissipation applications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted() ELECTRICAL Supply voltage, VCC () Input voltage, VI Output current, IO () Differential input voltage, VIO THERMAL ΘJC THS6 ±.5 V ±VCC ma Maximum junction temperature, any condition(3), TJ C Maximum junction temperature, continuous operation, long term reliability(4), TJ 5 C Operating free air temperature, TA 4 C to 5 C Storage temperature, Tsgt 65 C to C Lead temperature,,6 mm (/ inch) from case for seconds 3 C () Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. () The THS6 may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature that could permanently damage the device. See TI Technical Brief SLMA for more information about utilizing the PowerPAD thermally enhanced package. (3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process. (4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. ± V

3 THS6 SLLS544E SEPTEMBER REVISED JULY 3 ABSOLUTE MAXIMUM RATINGS ESD HBM ESD ratings CDM V MM RECOMMENDED OPERATING CONDITIONS 5 V V MIN NOM MAX UNIT Dual supply ±5 ± ± Supply voltage, VCC+ to VCC V Single supply 4 3 Operating free-air temperature, TA 4 5 C Operating junction temperature, continuous operation TJ 4 5 C Normal storage temperature, Tstg 4 5 C ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, TA = 5 C,VCC = ± V, Ω, Gain = +5, IADJ = Bias = Bias = V, RL = 5 Ω (unless otherwise noted) NOISE/DISTORTION PERFORMANCE MTPR HD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Multitone power ratio Gain =+.5, 3 khz to. MHz DMT, + dbm Line Power, See Figure for circuit 6 dbc Receive band spillover Harmonic distortion, VO(PP) = V f = MHz Gain =+5, 5 khz to khz with MTPR signal applied, See Figure for circuit nd harmonic 3rd harmonic Differential load = Ω Differential load = 5 Ω Differential load = Ω Differential load = 5 Ω 4 5 dbc Vn Input voltage noise VCC = ±5 V, ± V, ± V, f = khz 3. nv/ Hz In Input current noise Crosstalk +Input Input OUTPUT CHARACTERISTICS V, ± V, ± V, f = khz.5 dbc dbc pa/ Hz f = MHz, VO(PP) = V, RL = Ω 65 dbc VCC = ±5 V, ± V, ± V 6 dbc V VO Single-ended ended output voltage swing VCC = ± V I Output () O current VCC = ± V RL = Ω ±3. ±4. ±3. ±3. RL = Ω ±. ±. ±. ±.6 RL = Ω ±.5 ±. ±. ±.4 RL = 5 Ω VCC = ±5 V ±35 ±4 RL =Ω Ω VCC = ± V ±45 ±6 ma VCC = ± V ±45 ±6 I(SC) Short-circuit current () RL = Ω VCC = ± V ma Output resistance Open-loop 6 Ω Output resistance terminate mode f = MHz, Gain = +.5 Ω Output resistance shutdown mode f = MHz, Open-loop.5 kω () A heatsink is rsequired to keep the junction temperature below absoulte maximum rating when an output is heavily loaded or shorted. See Absolute Maximum Ratings section for more information. V V V 3

4 THS6 SLLS544E SEPTEMBER REVISED JULY 3 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range, TA = 5 C,VCC = ± V, Ω, Gain = +5, IADJ = Bias = Bias = V, RL = 5 Ω (unless otherwise noted) POWER SUPPLY PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dual supply ±4 ± ±.5 VCC Operatingrange range V Single supply 4 33 TA = 5 C.. VCC = ± 5V ma TA = full range. Quiescent current (each driver)() Full-bias mode TA = 5 C (Bias =, Bias = ) VCC = ± V ma TA = full range.5 (Trimmed with VCC = ± V at 5 C) I CC TA = 5 C.5.5 VCC = ± V ma TA = full range PSRR Quiescent current t( (each hdriver) Variable bias modes, VCC = ± V Mid; Bias =, Bias =.5.5 Low; Bias =, Bias = 4 5 ma Shutdown; Bias =, Bias =.5. VCC = ± 5 V, TA = 5 C 5 56 Power supply rejection ratio VCC = ±.5 V TA = full range 4 ( VCC = ± V) VCC = ± V, ± V, TA = 5 C 56 6 VCC = ± V TA = full range 53 () Approximately.5 ma (total) flows from VCC+ to for internal logic control bias. DYNAMIC PERFORMANCE BW PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = Ω Gain = +, RF =. kω Gain = +, Ω Gain = +5, Ω 35 Single-ended ended small-signal signal bandwidth Gain = +, Ω ( 3 db), VO =. Vrms Gain = +, RF =.5k Ω 65 RL =5Ω Ω Gain = +, Ω 6 Gain = +5, Ω 4 Gain = +, Ω SR Single-ended slew-rate() VO = VPP, Gain =+5 45 V/µs () Slew-rate is defined from the 5% to the 5% output levels DC PERFORMANCE V OS I IB Input offset voltage PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential offset voltage TA = 5 C TA = full range 5 VCC = ± 5 V, ± V, ± V TA = 5 C.5 TA = full range Offset drift TA = full range 5 µv/ C Input bias current +Input bias current VCC = ± 5V V, ± V, ± V TA = 5 C TA = full range TA = 5 C TA = full range Z OL Open loop transimpedance RL = kω, VCC = ± V, ± V, kω db MHz MHz mv µa 4

5 THS6 ELECTRICAL CHARACTERISTICS (CONTINUED) SLLS544E SEPTEMBER REVISED JULY 3 over recommended operating free-air temperature range, TA = 5 C,VCC = ± V, Ω, Gain = +5, IADJ = Bias = Bias = V, RL = 5 Ω (unless otherwise noted) INPUT CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V TA = 5 C ±. ±3. TA = full range ±.6 V V ICR Input common mode mode voltage range VCC = ± V VCC = ± V TA = 5 C ±.5 ±. TA = full range ±.3 TA = 5 C ±.4 ±. TA = full range ±. moderejectionratio ±5V T A = 5 C 4 54 CMRR Common-mode ratio VCC = V, ± V, ± V T A = full range 44 R I Input resistance + Input kω Input 3 Ω C I Input capacitance. pf LOCIC CONTROL CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Bias pin voltage for logic Relative to pin voltage. V VIL Bias pin voltage for logic Relative to pin voltage. V IIH Bias pin current for logic VIH = 3.3 V, = V 4 3 µa IIL Bias pin current for logic VIL =.5 V, = V µa Transition time logic to logic () µs Transition time logic to logic () µs () Transition time is defined as the time from when the logic signal is applied to the time when the supply current has reached half its final value. LOGIC TABLE BIAS- BIAS- FUNCTION DESCRIPTION Full bias mode Amplifiers ON with lowest distortion possible (default state) Mid bias mode Amplifiers ON with power savings with a reduction in distortion performance Low bias mode Amplifiers ON with enhanced power savings and a reduction of distortion performance Shutdown mode Amplifiers OFF and output has high impedance NOTE: The default state for all logic pins is a logic zero (). V V db 5

6 THS6 SLLS544E SEPTEMBER REVISED JULY 3 5 Ω +V CODEC V IN+ + THS6a 4. Ω k Ω :.6 + dbm Line Power.33 k Ω k Ω Ω 5 Ω +V 4. Ω CODEC V IN + THS6b Figure. Single-Supply ADSL CO Line Driver Circuit Utilizing Active Impedance (SF = 4) 6

7 THS6 SLLS544E SEPTEMBER REVISED JULY 3 PIN ASSIGNMENTS THS6 SOIC (DW) PACKAGE (TOP VIEW) THS6 SOIC (D) PACKAGE (TOP VIEW) D IN D OUT V CC D IN+ BIAS BIAS D IN D OUT V CC + D IN+ I ADJ D IN D OUT V CC D IN+ BIAS BIAS D IN D OUT V CC + D IN+ I ADJ THS6 Leadless 4 pin PowerPAD 4 mm X 5 mm (RHF) PACKAGE (TOP VIEW) D OUT D IN D IN D OUT V CC Power PAD TM V CC + DIN+ BIAS BIAS I ADJ DIN+

8 THS6 SLLS544E SEPTEMBER REVISED JULY 3 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Output voltage headroom Output current Common-mode rejection ratio Frequency 3 Crosstalk Frequency 4 Total quiescent current 5 Large signal output amplitude Frequency 6 Voltage and current noise Frequency Overdrive recovery Power supply rejection ratio Frequency Output amplitude Frequency 3 Slew rate Output voltage 3 Closed-loop output impedance Frequency 3 Quiescent current Supply voltage 4 Quiescent current Temperature 4 Common-mode rejection ratio Common-mode voltage 4 Input bias current Temperature 43 Input offset voltage Temperature 44 nd Harmonic distribution Frequency rd Harmonic distribution Frequency 53 6 nd Harmonic distribution Output voltage rd Harmonic distribution Output voltage 65 6

9 THS6 SLLS544E SEPTEMBER REVISED JULY 3 TYPICAL CHARACTERISTICS Output Voltage Headroom (V CC V out) OUTPUT VOLTAGE HEADROOM OUTPUT CURRENT VCC= ±5 V VCC= ± V 4 6 Output Current ma Figure CMRR db COMMON-MODE REJECTION RATIO k Figure 3 VCC= ± V Gain = RL= 5 Ω Crosstalk db VCC= ± V RL= Ω CROSSTALK Gain = +5 Figure 4 Gain = + Total Quiescent Current (ma) TOTAL QUIESCENT CURRENT VCC= ± V Mode Mode Lo w B ias Mo d e.. Rset to kω Figure 5 Large Signal (V PP ) LARGE SIGNAL Vo =Vpp Vo =4Vpp Vo =Vpp Vo = Vpp Vo =.5Vpp Vo =.5Vpp VCC= ± V Ω RL= Ω G Figure 6 Large Signal (V PP ) LARGE SIGNAL Vo =Vpp Vo =Vpp Vo =4Vpp Vo =Vpp Vo =Vpp Vo =.5Vpp Vo =.5Vpp VCC= ± V Gain = Ω RL= Ω G f Figure Large Signal (V PP ) LARGE SIGNAL 6 6 Vo = 4 Vp p Vo =Vpp Vo = Vpp Vo =.5Vpp Vo =.5Vp p VCC= ± 5V RF = 5 Ω RL= 5 Ω G Figure Voltage Noise nv/ Hz V n VOLTAGE AND CURRENT NOISE In+ In Vn k k k Figure Current Noise pa/ Hz I n Input Voltage V 3 OVERDRIVE RECOVERY VCC= ±V RL= Ω Vin Vout Time ( µ S) Figure 5 5 Output Voltage V

10 THS6 SLLS544E SEPTEMBER REVISED JULY 3 POWER SUPPLY REJECTION RATIO PSSR Power Supply Rejection Ratio db k Vcc VCC = ±V Ω RL = Ω Vcc+ k k M M M f Frequency Hz Figure 3 4 VCC = ±V 5 Gain = 6 VO =. Vrms G Figure RF =. k VCC = ±V Gain = RL = Ω VO =. Vrms RF =. k G Figure RF = 5 RF = 5 VCC = ±V VO =. Vrms G Figure VCC = ±V RL = Ω VO =. Vrms Figure VCC = ±V Gain = VO =. Vrms Figure RF =. k RF =. k VCC = ±V Gain = RL = Ω VO =. Vrms Figure 3 4 VCC = ±V Gain = 5 6 VlO =. Vrms G Figure VCC = ±V Gain = RL = Ω VO=. Vrms G Figure

11 6 5 4 VCC = ±V 3 Gain = VO =. Vrms G Figure VCC = ±V Gain = RL = Ω VO =. Vrms G Figure RF = 5 THS6 SLLS544E SEPTEMBER REVISED JULY 3 RF = 5 VCC = ±V VO =. Vrms Figure RF = 5 RF = 5 RF = 5 VCC = ±V VO =. Vrms Figure 3 VCC = ±V VO =. Vrms Figure 4 VCC = ±V RL = Ω VO =. Vrms Figure 5 RF = 5 RF = 5 VCC = ±V RL = Ω VO =. Vrms Figure 6 VCC = ±V RL = Ω VO =. Vrms Figure VCC = ±V Gain = VO =. Vrms Figure

12 THS6 SLLS544E SEPTEMBER REVISED JULY 3 VCC = ±V Gain = RL = Ω VO =. Vrms Figure VCC= ±V Gain = 5 VO =. Vrms Figure 3 VCC = ±V Gain = 5 RL = Ω VO =. Vrms Figure 3 3 RF =. k 3 RF =. k RF = 5 3 Gain = 4 5 VO =. Vrms 6 G Figure Gain = RL = Ω 5 VO =. Vrms 6 G Figure 33 VO =. Vrms Figure 34 RF = 5 RL = Ω VO =. Vrms Figure 35 Gain = VO =. Vrms Figure 36 Gain = VlO =. Vrms Figure 3

13 THS6 SLLS544E SEPTEMBER REVISED JULY 3 Slew Raie (V/us) SLEW RATE OUTPUT VOLTAGE SR+ SR 5 Output Voltage Vp p Figure 3 Zo Closed Loop Output Impedance Ohms CLOSED LOOP OUTPUT IMPEDANCE. Shutdown VCC = ± V Gain = RL = 5 Ω. Figure 3 Total Quiescent Current ma 5 5 QUIESCENT CURRENT SUPPLY VOLTAGE Ta = 5 deg.c Icc+ (Low) Icc+ (Mid) Icc (Low) Icc+ (SD) Icc+ (Full) Icc (Full) Icc (Mid) 3 5 Supply Voltage +/ Vcc Figure 4 A Icc (SD) Total Quiescent Current ma 5 5 QUIESCENT CURRENT TEMPERATURE Vcc = +/ V Icc+ (Low) Icc+ (Mid) Icc (Low) Icc+ (Full) Icc (Full) Icc (Mid) Icc (SD) Common Mode Rejection Ratio db COMMON-MODE REJECTION RATIO COMMON-MODE VOLTAGE Vcc = +/ V Deg C 4 Deg C 5 Deg C Input Bias Current ua INPUT BIAS CURRENT TEMPERATURE Iib Iib+ Icc+ (SD) Temperature Deg.C Figure Common Mode Voltage V Figure Temperature Deg C Figure 43 Input Offset Voltage mv INPUT OFFSET VOLTAGE TEMPERATURE Vio Channel A Vio Channel B Temperature Deg C Figure VCC = ±V Gain = RL = Ω Ω VO= VPP Figure Gain = RL = Ω Ω Figure 46

14 THS6 SLLS544E SEPTEMBER REVISED JULY VCC = ±V Gain = RL = 5 Ω 5 Ω Figure Gain = RL = 5 Ω 5 Ω Figure 4 6 VCC = ±V RL = Ω Ω Figure RL = Ω Ω Figure VCC = ±V 5 RL = 5 Ω Ω 5 Figure RL = 5 Ω Ω 5 Figure 5 3 VCC = ±V 4 Gain = RL = Ω 5 Ω 6 Figure Gain = RL = Ω Ω Figure Gain = RL = 5 Ω Ω Figure 55

15 VCC = ±V Gain = RL = 5 Ω Ω Figure VCC = ±V RL = Ω Ω Figure 5 THS6 SLLS544E SEPTEMBER REVISED JULY RL = Ω 5 Ω 6 Figure VCC = ±V 5 RL = 5 Ω Ω 6 Figure RL 5 Ω Ω Figure 6 OUTPUT VOLTAGE 5 5 VCC = ±V 5 RL = Ω Ω f = MHz Output Voltage Vpp Figure 6 OUTPUT VOLTAGE 5 OUTPUT VOLTAGE 65 OUTPUT VOLTAGE RL = Ω Ω f = MHz 5 Output Voltage Vpp Figure 6 5 VCC = ±V RL = 5 Ω Ω f = MHz Output Voltage Vpp Figure 63 5 RL = 5 Ω Ω f = MHz 4 6 Output Voltage Vpp Figure 64

16 THS6 SLLS544E SEPTEMBER REVISED JULY OUTPUT VOLTAGE 5 RL = Ω Ω f = MHz 4 6 Output Voltage Vpp Figure 65 OUTPUT VOLTAGE 5 5 VCC = ±V 5 RL = Ω Ω f = MHz Output Voltage Vpp Figure OUTPUT VOLTAGE VCC = ± V RL = 5 Ω Ω f = MHz Output Voltage Vpp Figure 6 OUTPUT VOLTAGE RL = 5 Ω 5 Ω f = MHz 4 6 Output Voltage Vpp Figure 6

17

18 MECHANICAL DATA MSOIB JANUARY 5 REVISED SEPTEMBER D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE PINS SHOWN.5 (,). (,5). (,35). (,5) 5.44 (6,). (5,). (,) NOM. (4,). (3,) Gage Plane 4 A. (,5).44 (,). (,4) Seating Plane.6 (,5) MAX. (,5).4 (,).4 (,) DIM PINS ** A MAX. (5,).344 (,5).34 (,) A MIN..33 (4,) (,55).36 (,) 444/E / NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed.6 (,). D. Falls within JEDEC MS- POST OFFICE BOX DALLAS, TEXAS 565

19 MECHANICAL DATA MSOI3E JANUARY 5 REVISED SEPTEMBER DW (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE.5 (,). (,5). (,35). (,5).4 (,65).4 (,). (,5). (,3). (,5) NOM Gage Plane. (,5) A.5 (,). (,4).4 (,65) MAX. (,3).4 (,) Seating Plane.4 (,) DIM PINS ** 4 A MAX.4.46 (,4) (,3).5 (,5).6 (,4). (,3) A MIN.4 (,).453 (,5).5 (,).6 (,4). (,) 44/E / NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed.6 (,). D. Falls within JEDEC MS- POST OFFICE BOX DALLAS, TEXAS 565

20 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio /audio Data Converters dataconverter.ti.com Automotive /automotive DSP dsp.ti.com Broadband /broadband Interface interface.ti.com Digital Control /digitalcontrol Logic logic.ti.com Military /military Power Mgmt power.ti.com Optical Networking /opticalnetwork Microcontrollers microcontroller.ti.com Security /security Telephony /telephony Video & Imaging /video Wireless /wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas 565 Copyright 4, Texas Instruments Incorporated