System Design, Verification and Optimization of Modern Memory Interfaces (DDR3) Greg Pitner

Transcription

1 System Design, Verification and Optimization of Modern Memory Interfaces (DDR3) Greg Pitner 1 ANSYS, Inc. September 14,

2 Agenda DDR3 Requirements Xilinx PCB translation DC and AC model extraction Building a system model User-defined outputs 2 ANSYS, Inc. September 14,

3 DDR2/3 Overview DDR3 speed is MBps which is 2x DDR2 Tighter noise margins Lower voltage (1.5V vs 1.8V) 4 ANSYS, Inc. September 14, Information source: JEDEC 2007 DDR Workshop and HP DDR3 Application Note

4 DDR2/3 Timing Specifications Setup Margin & Hold Margin DQ Jitter DQS V REF V IH(AC) Setup Time Hold Time V IH(DC) V IL(AC) V IL(DC) Setup Margin Hold Margin 5 ANSYS, Inc. September 14,

5 Also DDR2/3 Timing Specifications 6 ANSYS, Inc. September 14, Information source: JEDEC specification JESD79-3

6 ANSYS Solution Electrical DesignerSI, SIwave, HFSS Mechanical Fluid Dynamic 7 ANSYS, Inc. September 14, Images and models courtesy of the Xilinx, Micron Technology, TE Connectivity.

7 Xilinx ML605 Board 10 ANSYS, Inc. September 14, Courtesy of:

8 Layout Translation from Cadence Allegro 11 ANSYS, Inc. September 14, Courtesy of:

9 Complex Multiple PCB Power Domains Power Sources and Sinks 1.5V Memory and FPGA 1V8 2V5 2V5 FPGA 3V3 5V 12_P 12_P_IN 14 ANSYS, Inc. September 14, Courtesy of:

10 Bidirectional Thermal Link SIwave DC IR solver SIwave has the ability to examine the full current path as well as each individual segment. Hot spots/bottlenecks that may cause reliability and excessive heating can be detected via current density and DC simulation results can be coupled to a thermal / airflow simulation using ANSYS IcePak TM. SIwave Bi-directional Coupling Power and Thermal Mapping Icepak 15 ANSYS, Inc. September 14,

11 SIwave DC Simulation Adaptive meshing of PCB geometry 16 ANSYS, Inc. September 14,

12 SIwave Icepak Link SIwave Icepak Although most temperature increase is driven by IC s, IR loss in high-current nets can be a non-trivial source of heating SIwave can export spatiallydependent ohmic loss data to Icepak Icepak Siwave Metal conductivity is significantly affected by temperature SIwave can read temperature data from Icepak and alter DC conductivity accordingly 17 ANSYS, Inc. September 14,

13 SYZ Parameter extraction Main board and SODIMM modeled with SIwave Power Rail and Signal Nets, DC and AC DDR3 204PIN SODIMM Connector modeled with HFSS 19 ANSYS, Inc. September 14,

14 Designer Models Main board with connector Main board with connector and SODIMM board Main board only 20 ANSYS, Inc. September 14,

15 VRM(PTD08A010W) model from TI Fusion Digital Power designer from TI Generate real VRM model 22 ANSYS, Inc. September 14, Information source:

16 VRM DDR3 PDN model DDR3 1.5V Power Delivery Network with real VRM model Multiple probing points displayed Top and bottom DDR3 package, FPGA and VRM U8 U18 23 ANSYS, Inc. September 14, Courtesy of:

17 VRM Current Signature Profile Probe Point : VRM Output(Blue), FPGA Power(Brown) and DDR3 (Red). 1. VRM Output 2. DDR3 package 24 ANSYS, Inc. September 14,

18 Automatic Schematic Creation: SIWizard Step 1: Select Signal Nets Step 2: Assign IBIS TX/RX Buffers Step 3: Identify Component Pwr/Gnd Nets Step 4: Set VRM Parameters Step 5: Set Transient Simulation 28 ANSYS, Inc. September 14,

19 SSN analysis Full Schematic and Analysis DQS Zero Crossing and Eye Margins 29 ANSYS, Inc. September 14,

20 DDR3 Channel Eye Diagrams Connector Effects on DQS line Zero Crossing Without Connector With Connector 30 ANSYS, Inc. September 14,

21 DDR3 SSN and Channel Eye Diagrams 31 ANSYS, Inc. September 14,

22 User-Defined Outputs UDO s are a way of calling Python scripts from within the Designer GUI Python is an intuitive and powerful scripting language with a large scientific and engineering user base Perform custom analyses on simulation waveforms A Python script can be written to arbitrarily postprocess waveforms 32 ANSYS, Inc. September 14,

23 Setting Up a UDO Point Designer to a Python script and map variables to waveform trace names 33 ANSYS, Inc. September 14,

24 Creating a UDO-based Report Once a UDO is set up, its results can be accessed like an ordinary output 34 ANSYS, Inc. September 14,

25 DDR3 Calculations With UDO Voltage and timing margins can be printed in Data Table format within the Designer GUI 35 ANSYS, Inc. September 14,

26 DDR3 Channel Derating tables, slew rate 36 ANSYS, Inc. September 14,

27 SODIMM board, Connector and Main Board HFSS SIwave, DesignerSI SIwave, DesignerSI and HFSS 37 ANSYS, Inc. September 14,

28 ANSYS Tools Overview DDR3 Solution for Electrical Simulations ECAD Geometry Translation ECAD Translators and AnsoftLinks SI/PI DDR3 Channel Extraction HFSS, SIwave Design Automation and Schematic Creation DesignerSI and SIwave DDR3 Transient Simulation Results DesignerSI, UDO s 38 ANSYS, Inc. September 14,

29 Thank You 39 ANSYS, Inc. September 14,