Computer Structure. Topic 2. Contents

Transcription

1 31 Topi 2 Computer Struture Contents 2.1 Introdution Computer Organisation Calulating mahines - from Babbage to integrated iruits Computer organisation The stored program onept Feth-exeute yle Two-state mahine Reviewquestions Struture of a small omputer system Computer omponents and their funtion Memory Random aess memory Read only memory Review questions Cahe memory Memorymaps External memory Central proessing unit The arhiteture of the miroproessor Aessing memory Control unit Arithmeti logi unit Registers Review questions Buses Address bus Data bus Review questions Summary End of topi test

2 u u u u u u u u u u u 32 TOPIC 2. COMPUTER STRUCTURE Prerequisite knowledge Before studying this topi you should be able to: Desribe the purpose of a proessor and list its parts; Represent the data flow between the omponent devies of a omputer system; Distinguish between main memory and baking storage; Desribe the features and uses of Random Aess Memory (RAM) and Read Only Memory (ROM). Learning Objetives By the end of this topi, you will be able to: Desribe the purpose and funtion of the ALU and the Control Unit within a proessor; Desribe the purpose and funtion of registers; Desribe the purpose and funtion of the data bus and address bus; Identify ontrol lines within a omputer inluding reset and interrupt; Desribe the purpose of read, write and timing funtions of ontrol lines; Outline the steps of the feth-exeute yle; Desribe and make distintions between registers, ahe memory, main memory and baking store in terms of funtion and speed of aess. v

3 2.1. INTRODUCTION 33 Revision The following exerise tests the prerequisites for this topi. Ensure that you are happy with your responses before progressing. Q1: What type of memory stores programs that must not be lost when the power to the system is removed? Q2: A proessor will frequently transfer data. Where is the data transferred to and from a) Output devies b) Input devies ) Clok d) Memory 2.1 Introdution This unit on Computer Struture desribes in detail the funtion of the omponent parts of a proessor in the manipulation of data. This is extended to the methods of transferring data within a proessor and between a proessor and memory. The onept of a stored program is onsidered and the steps in the feth-exeute yle to aess and run programs. Memory types are onsidered, from registers to baking storage and how memory is defined and addressed. 2.2 Computer Organisation Computers play a signifiant role in meeting our everyday requirements. You an now browse the Internet for a new home, order from a supermarket on-line and have the goods delivered to your door. You an import a new ar from abroad at the touh of a button, order lothes from a atalogue ompany and ommuniate with friends overseas. The ways in whih you learn are also hanging. You an omplete a shool or ollege assignment using a general purpose pakage, or solve programming problems at home on your own PC, ing your results to your instrutor for feedbak. You an use omputer based learning tools to assist you in understanding new onepts. You are using one suh tool right now! If omputers have made suh a signifiant impat, then it makes sense to find out a little more about how they work and how you an make use of them. For instane, how are w

4 x y z { 34 TOPIC 2. COMPUTER STRUCTURE they strutured? How do they operate internally? How is data represented? Why are some omputers faster and more powerful than others? What devies an you attah to them and how an you get them to ommuniate? These are some of the questions we will be looking at in this topi. There are others. First let us take a loser look at the basi struture of a small omputer system and at how it operates internally Calulating mahines - from Babbage to integrated iruits Learning Objetive At the end of this topi you will know: the ontribution of Charles Babbage to modern omputer design; major tehnologial advanes leading to the development of the Personal Computer. Nowadays you use alulators to perform numerial alulations. This was not always the ase, and for some soieties, is still not. Sine early times humans have tried to find ways to make alulations easier. For instane the abaus was developed by the Chinese around 1300 AD, although similar devies had been used by the Babylonians, sine about 500 BC. Logarithms were developed as a method of alulation by John Napier, who also invented a devie known as Napier s Bones. The slide rule is a further example of an analogue devie for multipliation that is based upon logarithms. Simple, manually operated mehanial alulators were developed by many famous mathematiians, inluding Pasal and Leibniz. The first steps towards automating the mehanial alulator were taken by Charles Babbage ( ) with the design of the speial purpose Differene Engine and the subsequent design of the more general purpose Analytial Engine. The Analytial Engine was ontrolled by a set of instrutions entered as punh holes on a set of metal ards. This idea was first introdued by Jaquard ( ) who designed weaving looms. The pattern woven depended upon the position of holes punhed in metal ards. Unfortunately the tehnology of the time was not advaned enough to allow Babbage to onstrut a working mahine. However his ideas laid the foundations of modern omputer design. These ideas inluded: a memory that ould store 1000 numbers; }

5 ~ ~ ~ 2.2. COMPUTER ORGANISATION 35 a mahine ontrolled by a program entered into it; entering a different program to perform a new task - general purpose; the program was a set of instrutions that, if followed, would aomplish a task - an algorithm. These ideas were not developed further until eletro-mehanial relay tehnology produed omputers in the 1930s. By today s standards these mahines were large and slow. Vauum tube tehnology in the 1940s inreased the speed of the omputers and by the 1960s transistor tehnology redued the size and power requirements. From about 1965 to the present, the iruits for many operations have been inorporated into a single hip as Integrated Ciruits (ICs). Chip fabriation tehniques also improved, allowing further integration to the extent that we now have Very Large Sale Integration (VLSI) and a omplete proessor on a hip. This made possible the Personal Computer. Review Questions Q3: Desribe the Analytial Engine designed by Charles Babbage. Q4: How does the Analytial Engine relate to modern omputers? Q5: What tehnial development in the 1940s and 1950s helped redue the size and power requirements of omputers? Q6: What affet did the development of the integrated iruit have on omputers? Computer organisation Computers are digital mahines that exeute mahine ode programs and operate on data in binary form. By binary form we mean a representation of information as 0s and 1s. Binary representation of information was onsidered earlier in this unit. Here we examine the internal organisation of the omputer to understand how mahine ode programs are run.

6 36 TOPIC 2. COMPUTER STRUCTURE The Organisation of a Simple Computer Until now we have been looking at how we an use simple logi gates to produe devies suh as adders, deoders and flip-flops. Although we have looked at simplified versions of these logi devies, it is devies suh as this that are ombined together to reate a omputer. We will now step bak a level and look at the basi arhiteture of a simple omputer. A simple omputer onsists of the following omponents (see Figure 2.1): Proessor; Memory; Input/output devie; Communiation hannels (shown between the aforementioned omponents in Figure 2.1); Figure 2.1: A Simple Computer Input devies inlude the keyboard and mouse and an be used to supply input to the proessor. Output devies inlude the sreen and printers and these an be used to supply output from the proessor. Input and output devies are often known as peripheral devies. Some omputers have more than one proessor; however we will onentrate on single proessor mahines in this topi. Where there is only one proessor it is known as the Central Proessing Unit, orcpu. This is where instrutions are proessed and omputations are arried out. This is the ontrol entre of the omputer. The ommuniation hannels allow data and ontrol signals to be ommuniated between the main omponents of the omputer via the system bus or external bus. A bus is a olletion of parallel wires eah of whih an arry a digital signal. Thus a 16- bit wide bus ould transmit 16 bits simultaneously. The CPU has its own internal bus allowing the ommuniation of data and ontrol signals between its omponent parts. It is worth noting here that the system bus ontains lines to transmit data, lines to transmit memory addresses and various ontrol lines. Frequently it is thought of as if it were separate buses: a data bus, an address bus and ontrol lines. Sometimes the data and address lines are not separate at all and the same lines are used for different

7 2.2. COMPUTER ORGANISATION 37 purposes at different times. For example, one moment sending an address to memory and the next transmitting data from the addressed memory loation to the CPU. A more detailed diagram of the main omponents of a simple omputer are shown in Figure 2.2. Figure 2.2: The Organisation of a Simple Computer The omputer illustrated in Figure 2.2 is a typial example of a Von Neumann arhiteture. Virtually all omputers follow this arhiteture model that has its origins in the stored program onept proposed by John Von Neumann in The basi idea behind the Stored Program Conept is that the sequene of instrutions (or program) to solve a problem should be stored in the same memory as the data. This ensured that the omputer beame a general-purpose, problem-solving tool, sine to make it solve a different problem required only that a different program be plaed in memory. The omponent parts of the omputer are: Central Proessing Unit (CPU). Carries out omputation and has overall ontrol of the omputer. Main memory. Stores programs and data while the omputer is running. Has fast aess, is diretly aessible by the CPU, is limited in size and non-permanent. External memory. Holds substantial quantities of information too large for storage in main memory. Slower aess than main memory, not aessible diretly by the CPU but an be used to keep a permanent opy of programs and data. Peripheral devies (input/output devies). ommuniate with the outside world. These allow the omputer to ƒ

8 38 TOPIC 2. COMPUTER STRUCTURE External system bus. This allows ommuniation of information between the omponent parts of the omputer. Some possible transfers of information via the system bus are: data transmitted from main memory to the the CPU input data from an external devie (e.g. the keyboard) travelling from the devie to main memory information from external memory transmitted to main memory The speed of the system bus is very important sine, if it is too slow, the speed of the CPU is restrited by having to wait for data. The CPU typially onsists of A Control Unit (CU) whih exerts overall ontrol over the operation of the CPU; An Arithmeti and Logi Unit (ALU) whih arries out omputation; A set of registers whih an hold intermediate results during a omputation. Two of these registers are of partiular importane, namely, The Program Counter (PC) whih holds the address in memory of the next instrution in the program; The Instrution Register (IR) whih holds the instrution urrently being exeuted. These omponents are linked by an internal bus. In pratie, the arhiteture of a modern digital omputer will be more omplex than the desription given here, with eah omponent itself being an assembly of parts onneted by various different buses. However, for the moment, this will suffie as a model for how the major parts of a digital omputer are organised Review Questions Q7: What are the main omponents of a omputer? Q8: What is the purpose of the system bus? What type of information is it likely to transmit? Q9: With what important onept was John Von Neumann assoiated? What large advantage did this onept onfer upon omputers? Q10: What is held in the main memory of the omputer? Why is external memory also required? Q11: How would an item of data that was entered at the keyboard finally find its way into a CPU register for proessing?

9 2.2. COMPUTER ORGANISATION 39 Q12: All CPUs ontain two partiular registers. What are these registers and for what are they used? The stored program onept All omputers are based upon the same basi design, known as the Von Neumann Arhiteture. Computers arry out tasks by exeuting mahine instrutions. instrutions is alled a mahine ode program. A series of these A mahine ode program is held in main memory as a stored program, a onept first proposed by John Von Neumann in A unit, known as the Central Proessing Unit (CPU) fethes, deodes and exeutes the mahine instrutions. By altering the stored program it is possible to have the omputer arry out a different task. As a user of a desktop omputer you will already know this. You may have loaded a word proessing program to enter and edit text. Using the same omputer you may have opened a spreadsheet or drawing program to enter numerial values or reate graphi images. Being able to load and exeute different programs allows the omputer to beome a general purpose problem solving mahine Feth-exeute yle To exeute a mahine ode program it must first be loaded, together with any data that it needs, into main memory (RAM). One loaded, it is aessible to the CPU whih fethes one instrution at a time, deodes and exeutes it at eletroni speed. Feth, deode and exeute are repeated until a program instrution to HALT is enountered. This is known as the feth-exeute yle.

10 40 TOPIC 2. COMPUTER STRUCTURE Feth exeute yle in greater detail Earlier we introdued the feth-exeute yle and desribed the stored program onept where mahine ode instrutions are repeatedly transferred from main memory to the CPU for exeution. We would now like to show you how the address bus, data bus, ontrol bus and internal registers take part in reading a program instrution from main memory - essentially the feth phase of the feth-exeute yle. Figure 2.3 below illustrates in more detail the feth-exeute yle. Simulation of an instrution feth Figure 2.3: Feth-exeute yle On the web is a simulation whih shows you how the buses and the internal registers of the CPU take part in reading an instrution from main memory. You should now look at this simulation.

11 2.2. COMPUTER ORGANISATION Registers used by the proessor in the feth-exeute yle Memory address register To aomplish the tasks, a proessor has a olletion of dediated registers. These are used to hold information speifi to this task. Note that these registers are in addition to the general purpose registers provided by the proessor. Unlike the general purpose registers, these registers are not usually visible to the assembly level programmer. The first register that we will disuss is the memory address register (MAR). This is used to hold a value representing the address in memory that the proessor needs to aess. Usually the MAR will hold a bit pattern orresponding to the state (0 or 1) of the address bus. When the proessor needs to aess memory, the value of the loation in memory is plaed in the MAR and the proessor iruitry will ensure that the address bus lines are set to the orret values. Memory data register The memory data register (MDR) is used to hold bit patterns that represent data values. For example, when reading from memory, the MAR will be used to set up the address lines to selet a loation. After a short delay, the memory devie will set the lines on the data bus to appropriate values. When the values on the data bus have settled, the iruitry of the proessor will set the value of the MDR to the value that appeared on the data bus. Instrution register The instrution register is a dediated storage spae used by the ontrol unit when it is deoding instrutions. General purpose registers involved in the feth-exeute yle The program ounter (PC) is the general purpose register most involved in the fethexeute yle. Remember that this register is used to keep trak of where in the program exeution has reahed. Other general purpose registers are only usually affeted as part of the exeution of the program and as suh, are not fundamental to the operation of the yle The feth phase The first of the two main phases of the feth-exeute yle is the feth phase, and onsists of the following steps: 1. The ontents of the PC are opied into the MAR; 2. The ontents of memory at the loation designated by the MAR are opied into the MDR; ˆ

12 42 TOPIC 2. COMPUTER STRUCTURE 3. The PC is inremented; 4. The ontents of the MDR are opied into the IR. Remember that the PC is used to keep trak of where exeution has reahed. Thus the first step is onerned with establishing the loation of the next instrution to exeute. The seond step is to get the value into the MDR. The third step is to ensure that the PC points to the next instrution to be exeuted: if we did not inrement the PC at some point, we would ontinually exeute the same instrution over and over again!. The fourth step ensures that there is a opy of the instrution in the IR ready for exeution to begin. Sequening the steps in an instrution feth On the web is an assessment that requires you to plae the steps of an instrution feth in the orret order. You should now arry out this assessment The exeute phase The exeute phase onsists of the following steps: 1. Deode the instrution in the IR; 2. Exeute the instrution in the IR. One the exeute phase has ompleted, the feth phase will be arried out again. Animation of the feth-exeute yle On the web is an animation of the feth, deode and exeution of the instrution LOAD[16]. You should now look at this animation. Pseudoode representation of the feth-exeute yle For onveniene we an write this series of steps as a pseudoode representation: >Š>Š Œ ŠYŽ4 Y 4 YŽ, >š >š,œ Y ž>š, >Ÿ,,ž,š Y š ž 4 YŠ š «ª4, š Y,,Š>ŠY Note that «means is opied to and that pointed to by, >š. >š œ ± means the ontents of the loation

13 ³ µ 2.2. COMPUTER ORGANISATION Two-state mahine The eletroni omponents of a omputer are designed to be in only one of two states. For example, a magneti storage devie reords data magnetised in one diretion or another, transistors ondut or do not ondut. The binary digits 0 and 1 are used to represent these two states and hene the omputer is termed a two-state mahine Review questions Q13: Whih of the following is true? a) mahine ode is represented in binary b) data is represented in deimal or hexadeimal ) a stored program is exeuted from disk Q14: What is meant by the term stored program? Q15: The CPU: a) was invented by John Von Neumann b) holds a stored program ) fethes, deodes and exeutes mahine instrutions Q16: What is meant by the term feth-exeute yle? Q17: Whih of the following is false? a) magneti storage devies are two-state devies b) a two-state devie an only be in one of two states ) binary annot be used to represent a two-state devie Struture of a small omputer system ² Learning Objetive At the end of this sub-topi you will know: The main funtions of the omponents of a small omputer system; Organisation of Main Memory and types of main memory;. The purpose of the Address Bus, the Data Bus and the Control Bus; Internal registers of the CPU and their purpose; The steps involved in a memory read operation. We want to look at the internal organisation of the omputer at a level of abstration that desribes the system as interating, high-level omponents. For now, we are not that interested in the lower level detail of shunting bits around the mahine. To get a feel for this omponent level, imagine you are a ar driver. When you step into the ar, what is visible to you are interfaes to the omponents that allow you to drive it.

14 44 TOPIC 2. COMPUTER STRUCTURE The ignition omponent allows you to start the ar and to swith it off. You do not need to know how the ignition system works, this is hidden from sight. Aelerator pedals, brake pedals and a gear mehanism eah interfae to omponents whih alter the speed of the ar. To manouvre the ar you operate a steering wheel whih interfaes to a steering omponent. From this desription, you ould produe a diagram of these interating omponents. It would not be very detailed and ertainly would not have enough information for a ar mehani to work with, but it would, at a higher level, desribe how the driver interats with the ar. This is the omponent level we will introdue. Identifying system omponents used in a task 5min You should find a partner to work with. Imagine that you have a PC or a Ma running a windows interfae and that you have powered it up. Now think about the sequene of events that our when you reate a new word proessing doument. Try to identify the omponents of your PC that are involved in this task. For instane, there will need to be a transfer of the word proessing appliation (program) from the hard disk omponent to the main memory omponent in order to run the program. What happens next and what omponents do you think are involved? Computer omponents and their funtion The omponents of the CPU and the onnetions to devies that are external to it are showninfigure2.4

15 2.3. MEMORY 45 Figure 2.4: Components of a Small Computer System 2.3 Memory Main memory (RAM and ROM) stores programs and data while the omputer is operating. Memory used to be soldered onto the system board of the proessor (motherboard). The need to provide more readily upgradable omputers led to the development of Single In-Line Memory Modules (SIMMs). These plug into a SIMM soket on the motherboard. Eah SIMM ontains a number of DRAM hips and varies depending on the type of omputer and the amount of RAM required. Later, we will take a loser look at the harateristis of RAM and ROM hips and the differenes between DRAM and SRAM. Main memory onsists of a large sequene of bytes (typially 64 Mbytes in a PC) eah of whih may be diretly aessed using its memory address. In a bytewide memory, the first byte in memory has address 0 and subsequent bytes have addresses 1,2,3, et. as shown in a simplified representation of RAM in Figure 2.5 ¹

16 º º º º 46 TOPIC 2. COMPUTER STRUCTURE Figure 2.5: A simplified representation of RAM Any loation in memory an be read from or written to by referring to its address. Memory an be organised as: 8- bit wide (PC-8088) 16-bit wide (XT-8086, AT-80286) 32-bit wide (386DX, 486SX, 486DX) 64-bit wide (Pentium) Random aess memory Random Aess Memory (RAM) is a volatile memory. This means that the ontents of RAM are lost when power is no longer supplied to the hip. RAM an be written to and read from. There are two types of RAM, namely stati and dynami (SRAM and DRAM) SRAM hips are very fast but are not suited for very large amounts of memory. They are more suited to ahe memory, where only small amounts are required. You will learn more about ahe memory when we look at fators that affet system performane. DRAM hips are more widely used. They are muh heaper to produe, an hold larger amounts of data in a smaller physial area and require less power. They are dynami, requiring a ontinuous signal to refresh the ontents of the hip Read only memory Read Only Memory (ROM) is a non-volatile store whih means that the ontents are held permanently. The software and data stored on the ROM are fixed at the time of manufature. One programs and data have been entered into the ROM they annot be subsequently altered.»

17 2.3. MEMORY 47 ROMs are used to store programs and data that do not hange during the operation of the system. These are known as mask programmed ROM. Where different software and/or data is needed on a ROM hip, manufaturers produed a hip that allows existing data to be erased and new data written. These are known as eletrially programmable read-only memory hips (EPROMs). Data is erased by shining ultraviolet light onto the hip. EPROMs have the disadvantage that all the hip ontents are removed during erasure. The entire hip has to be reprogrammed, even if only a single memory word needs to be hanged. Another type of ROM tehnology where the ontents of the hip an be altered is the eletrially erasable programmable read-only memory (EEPROM). By applying suitable eletrial pulses, this hip an be seletively reprogrammed whih means that the entire ontents need not be erased Review questions Q18: Whih of the following is true? a) RAM is volatile b) ROM is volatile ) Neither RAM nor ROM is volatile Q19: Explain what is meant by the term non-volatile? Q20: Whih of the following memory hips an be seletively reprogrammed? a) PROM b) EEPROM ) EPROM Q21: Explain how EPROM hips an be reprogrammed and give one disadvantage of EPROM. Q22: Whih of the following statements is false? a) RAM annot be written to b) ROM an only be read from and not written to ) EEPROM is erased using eletrial pulses ROM tehnologies On the web is an ativity that asks you to math ROM tehnologies to their desriptions. You should now arry out this ativity Cahe memory Program instrutions are usually read sequentially. From one instrution it would be reasonable to assume that the next instrution required will be in the next memory loation. This assumption is used to inrease proessor effiieny. Although the movement of data within the proessor is getting faster and faster, the system buses are not keeping up. This leads to wasted time while the proessor waits for data to be fethed from memory. ¼

18 48 TOPIC 2. COMPUTER STRUCTURE To redue this problem most mahines now have a seond, smaller, area of memory known as ahe memory. This is usually SRAM whih is faster than DRAM, and although this is muh smaller than RAM there is a benefit from the fat that it is always faster to aess a small memory segment. When data or an instrution is read from memory, the memory loations following are opied into the ahe memory. At the next read instrution the ahe memory is read first. If the data is in ahe the aess time will be muh lower than going to main memory. If the data is not in ahe then main memory will be aessed, and although there is a slight loss of time from reading twie, the overall time saving in this method is quite signifiant. Observing ahe memory On the web is a simplified simulation of the operations of ahe memory. You should now look at this simulation. The ontents of ahe are simultaneously held in RAM. When data is to be written bak to memory it must be written to ahe so that the ahe is kept urrent. At some stage it will also have to be written bak to RAM. Cahe that has not been updated doesn t have to be opied bak to memory it is just removed from ahe when it is to be replaed by something the proessor has a greater need for. There are 2 different ways to update ahe memory. Write through ahe. When ahe is updated memory is updated at the same time. Write bak ahe. Cahe is updated, but RAM is not updated until the ontent of ahe is being leared. Write bak requires fewer write operations but there is an overhead in managing the seleted updates. Write bak ahe is generally about 10% faster than write through ahe Memory maps Main memory is made up of a matrix of ells. However when studying the ontent of memory it is helpful to use a logial view of a set of ells, arranged in numerial order in whih the lowest memory position is loation 0 and the highest is loation ½. Different proessors have different ways of organising information in RAM, the BIOS and part of the operating system will always be in the same proteted areas. Certain areas are alloated for user appliations. Memory addresses are often written in hexadeimal as they would otherwise be awkwardly long binary strings. Example : Memory addresses Problem: A proessor has a 16 line address bus. If a partiular memory holds an operating ¾

19 Æ 2.3. MEMORY 49 system from position 0 16 to , and a 32 Kb program starts at position ,is there enough free memory spae for a 1 Kb blok of data starting at position C000 16? Solution: O/S Program Data 02K 8K 40K 48K 64K Step 1 There are 16 address lines. The maximum number of address loations = 2 16 = =64K. Mark 64K on the memory map. Step 2 O/S from 0 16 to Æ «ÀÀ Á.Â0ÃÅÄ Kb ÀÀ Á.Â0Ã Ç Kb Operating system from 0 to 2 Kb Mark this blok on the memory map. Step 3 Program from for 32 Kb «ÀÀÀ Á.ÂÃ Kb ÆÊÉÌË Ç«ÍÎÃ «À so the program runs from 8 Kb to È Mark this blok on the memory map. Step 4 The starting position for the data blok is C This is at 48 Kb and needs 1 Kb of spae. Mark this on the memory map. The data will fit. Kb. Desribing memory maps Q23: A proessor has 16 lines. The memory has 4 KB s of BIOS data starting at position 0. Ï

20 Ð Ð Ð Ð Ð Ð 50 TOPIC 2. COMPUTER STRUCTURE There are devie drivers positioned from for 8 Kb A program runs from 32 K to the top of memory. Identify where, in memory, there is free spae and how muh there is. Q24: A proessor has 32 address lines. There is BIOS data from 0 to 8 Kb The DOS kernel lies between and There is a program from F using 24 Kb There is a data blok from F using32k. Draw the memory map learly identifying the start and end of eah used memory area External memory External memory, suh as the hard disk, holds quantities of data too large to store in main memory. It is also used to keep a permanent opy of programs and data. Examples of external memory devies are: hard disk; floppy disk; zip disk; CD-R; magneti tape; flash drive. Ñ

21 Ò Ò Ò 2.4. CENTRAL PROCESSING UNIT Central proessing unit Central Proessing Unit. The CPU oordinates and ontrols the ativities of all other units in the omputer system. It exeutes program instrutions and manipulates data in aordane with the instrutions. The CPU is the most important omponent of a omputer and it is essential to have a good knowledge of its internal organisation, i.e. its arhiteture. Just as the arhiteture of a building refers to a struture of rooms, failities and aess whih links all parts of the building, proessor arhiteture refers to its internal organisation of subsystems and how they interat. CPUs are fairly omplex and at this level of study we will onentrate on a simplified funtional desription of its struture using a standard arhiteture omposed of the following three omponents: Arithmeti and logi unit (ALU); Control unit; Registers. All three omponents work together to form the proessor The arhiteture of the miroproessor We will now study the internal arhiteture of the miroproessor (CPU) itself. Beause of the stored program onept, any onsideration of this arhiteture must onsider the relationship between the CPU and memory. Figure 2.6 is a shemati diagram of a fairly typial miroproessor design, showing the internal struture of the CPU and its relationship to the memory of the omputer. Ó

22 Ô Ô Ô Ô 52 TOPIC 2. COMPUTER STRUCTURE Figure 2.6: Typial Miroproessor Design We will now look at the role that these omponents play in the operation of the proessor Aessing memory The CPU has to aess memory both for instrutions and to reeive and transmit data from or to memory. For this purpose it typially has two internal registers, namely: Memory Address Register (MAR) - speifies the address in memory for the next read or write operation from or to memory; The Memory Data Register (MDR) or Memory Buffer Register (MBR) - ontains the data to be written to memory or reeives the data read from memory. The MAR register is onneted to the address portion of the system bus and the MDR register is onneted to the data portion of the system bus. To read data from memory, the CPU plaes the address of the required memory loation into the MAR and ativates the memory-read ontrol line of the system bus. This will ause the required data to be transmitted from memory via the data bus to the MDR; To write from the CPU to memory, the CPU plaes the data to be written in the MDR; the address of the memory loation where they are to be written is plaed in the MAR; and the memory-write ontrol line is ativated. The MAR and MDR registers have a large part to play in the feth-exeute yle. When fething an instrution from memory during the feth-exeute yle, the address ontained in the PC will be opied to the MAR using the proessor s internal bus. When the memory-read ontrol line is ativated, the instrution will be sent to the MDR using the data bus. From the MDR it will be opied to the IR using the proessor s internal bus. When exeuting an add to aumulator instrution, the address part of the instrution will be sent to the MAR so that the operand an be obtained from memory. The operand Õ

23 2.4. CENTRAL PROCESSING UNIT 53 is then plaed in the MDR from where it an be sent to the ALU, viathecpu internal bus, for adding to the ontents of the aumulator Control unit The mahine ode programs stored in main memory tell the omputer what steps must be arried out to solve a problem. They also tell it the sequene in whih it must arry out the steps. The ontrol unit inludes timing/ ontrol logi and the instrution deoder. It sends signals to other parts of the omputer to diret the feth and exeution of mahine instrutions. Using timing and ontrol signals, it tells other parts of the system what to do and when to do it, i.e. it synhronises the whole system. Signals are sent out and reeived on the ontrol bus. For example, if data is to be read from main memory, the ontrol unit will initiate a read signal on the ontrol bus. Some signals, suh as interrupts, originate from external devies, ating as inputs to the CPU. The ontrol bus is not really a bus at all. Unlike the address and data buses where bits are simultaneously transmitted along a set of parallel wires, the ontrol bus is made up of disrete wires, eah having a speifi funtion. These funtions are desribed in the table below: Control Line lok reset interrupt NMI Funtion generates a onstant pulse at a frequeny measured in Hertz (Hz). Eah pulse auses a mahine operation to be arried out. Mahine operations inlude reading data from main memory or adding numbers together. auses the proessor to halt the exeution of the stored program. All internal registers are leared and the mahine reboots. tells the proessor that an external event has ourred, suh as the transfer of data from an external devie. The proessor may ignore this type of interrupt. a non-maskable interrupt that annot be ignored by the proessor. For example, low power failure. When data is to be read from a memory loation then the ontrol unit will initiate a read signal on the ontrol bus and when data is to be written to a memory loation then the ontrol unit will initiate a write signal. These operations are desribed later in greater detail when we take a loser look how an instrution is fethed from main memory. Ö

24 54 TOPIC 2. COMPUTER STRUCTURE Identifying funtions of the ontrol bus On the web is an ativity that asks you to orretly identify 4 funtions of the ontrol bus. You should now arry out this ativity Getting the proessor s attention A omputer reeives signals from a number of different soures. Charaters keyed in on the keyboard, the lik of a mouse, data from a sanner. The arrival of this type of signal is not neessarily expeted at any partiular time and the omputer has to have a way of deteting them. There are two ways that this an happen, known as polling and interrupts Polling The first is known as polling. This is what ertain types of door to door salespeople do. They ensure that all their ustomers have a opy of the ompany atalogue and then they visit every house on a rota basis to ask if the ustomer would like to plae an order. This means that the salesperson will visit every house, say, every month. They may know that the average time between orders is about 3 months but they an t take the risk of leaving the ustomer unattended when they might want to plae a big order. This means that the salesperson may be wasting a lot of time making unneessary alls. From the ustomer s point of view this is not ideal either, beause they might realise a week after the last visit that they have forgotten something important and there is no way to shorten the waiting time until next month. For a omputer system this would work quite satisfatorily if the proessor was running a mirowave oven beause the proessor would be dediated to that one task and effiieny would be a meaningless onept. The life of the door to door salesperson would be simpler and they would be able to handle far more ustomers, if the ustomer was given a phone number or address and asked to initiate ontat when they wanted to order. This would provide the ustomer with a muh better servie and also allow the salesperson more time to do other things Interrupts In omputer terms, the signal from a peripheral devie or program that the attention of the proessor is needed is known as an interrupt. Every time a keyboard key is pressed an interrupt is generated. When the mahine is designed, the handling of interrupts is planned for. In an IBM type PC there is an allowane for 256 different types of interrupt. When one of these ours the system is able to identify its type. With this information the proessor then looks at an area in memory in whih an address for eah of the 256 interrupts is stored. At this address there is a program known as an Interrupt Servie Routine. The

25 Ø Ø Ø Ø Ø 2.4. CENTRAL PROCESSING UNIT 55 address table is used to furnish addresses indiretly beause this makes it possible for a programmer to ontrol. Many of the ISRs are stored in ROM. When an interrupt is reeived, the proessor will: store the ontents of its internal registers in an area of memory alled the stak; find the address for the ISR; jump to the servie routine and proess it; reload the internal registers from the stak; ontinue proessing from where it stopped. There are different priority levels assigned to interrupts. If an interrupt arrives while the proessor is already dealing with one, it an do one of two things. If the seond interrupt is of a lower priority the proessor will arry on until the urrent interrupt has been servied then it will servie the seond. If the new interrupt is of a high priority the proessor will store it s urrent state on the stak and start to proess the newer interrupt. When that one is finished it will omplete the proessing of the first interrupt and then revert to the original proess. This is known as nesting interrupts. Interrupts an be generated by hardware or software. Any signal oming from a peripheral devie will prompt an interrupt. Eah I/O onnetion has a physial link alled an IRQ line. This serves to arry the interrupt signal and in turn to identify the soure of the interrupt. Internal devies onneted via the motherboard also use IRQ lines. There is a limited number of IRQ lines and this an be a limiting fator in adding hardware to a omputer system. However the newer systems using USB (Universal Serial Bus) or Firewire an aept a number of hardware devies sharing IRQ lines. A software interrupt is one generated from within a program. This inludes routine ativities like sending a harater to the keyboard or the sreen. A software fault like trying to divide by zero, or trying to write into a proteted area of memory, will also all an interrupt. Generally the proessor an mask or delay the serviing of interrupts until it is ready. There is, however, a group of interrupts that annot be ignored. These are known nonmaskable interrupts (NMIs). Typially this interrupt would indiate a problem suh as loss of power, requiring the omputer to shut down immediately Arithmeti logi unit Ù The arithmeti logi unit (ALU) is where data is proessed and manipulated and an be onsidered the "brain" of the omputer. Proessing an involve either arithmeti operations and the ALU must ontain iruitry to perform additions. Note that multipliation an be ahieved through a series of additions, while division an be ahieved through a series of subtrations.

26 Ú Ú Ú Ú Ú Ú Ú Ú 56 TOPIC 2. COMPUTER STRUCTURE The ALU may also perform logial operations suh as a logial OR operation. This requires in-built logi elements. The ALU uses arithmeti registers whih are storage loations used to hold data and temporary results of alulations. One speial storage register used by the ALU is the aumulator whih it uses to hold the results of additions. Typial operations performed by the ALU inlude: addition; subtration; shift left; shift right; logial OR; logial AND; inrement; derement Registers A register is a storage loation used to hold instrutions, memory addresses, data or the temporary results of alulations. Beause registers are internal to the proessor, they an be aessed at high speed. The CPU has a set of general and speial purpose registers and the number and type of registers in any one CPU will be different from those in another CPU. Speial purpose registers typially found within a proessor are listed below: memory address register (MAR) is used to hold the address of a loation in main memory. memory buffer register (MBR) is used to hold data that has just been read from main memory or is to be written to main memory. instrution register (IR) is used to hold the urrent instrution that is being exeuted. program ounter (PC) holds the address of the next instrution to be fethed from memory. The proessor also has a set of general purpose registers. They are alled general purpose beause their role is not defined at manufature and an be used by programmers as appropriate Review questions Q25: What is the funtion of the CPU? Q26: Whih of the following is NOT a omponent of the CPU? Û

27 2.5. BUSES 57 a) ALU b) RAM ) Speial purpose registers Q27: How does the ontrol unit synhronise operations within the omputer? Q28: Whih of the following desribes how the ALU performs multipliation? a) using a logial OR operation b) suessive addition ) using an inrement operation Q29: Why are general purpose registers provided within the CPU? Mathing CPU registers to their purpose On the web is an ativity that asks you to math some CPU registers to their purpose. You should now arry out this ativity. Mathing CPU omponents to their desriptions On the web is an ativity that asks you to math CPU omponents to their desriptions. You should now arry out this ativity. 2.5 Buses The system bus is a group of parallel wires, eah arrying a single bit of data. In a single bus system, input/output devies (I/O) and memory use the same ommuniations hannel. A two bus system has a separate I/O hannel and memory transfer hannel. Larger systems make use of several I/O buses for more effetive operation. A single bus system is typial of small omputer systems. The system bus must provide omponents with the use of a Data Bus, Address Bus and Control Bus. Ü

28 58 TOPIC 2. COMPUTER STRUCTURE Address bus The address bus is a uni-diretional bus, transferring information in one diretion only. In a single bus system, input/output devies (I/O) and memory use the same ommuniations hannel. When the CPU needs to put data into memory or send it to a disk then it does so in the same way, only using different addresses. Devies are memory mapped and are treated by the system as if they were memory. The address bus is made up of parallel wires, eah apable of arrying 1 bit. The size of the address bus will determine how many memory loations an be diretly addressed. To understand this, onsider first an address bus width of 1-bit. There are 2 distint values that a single bit an represent (0 or 1). Thus a bus width of 1-bit an identify 2 unique addresses. Now add another address line. There are now 2 lines, eah of whih an represent 2 distint values. This results in 4 possible unique addresses shown below. Now add another address line. There are now 3 lines, eah of whih an represent 2 distint values, resulting in 8 unique addresses. Can you think of a general formula to relate the number of diretly addressable memory loations to the width of the address bus? If not, try answering the questions below and then think through the problem again. Q30: How many memory loations an be diretly addressed using 5 bits? a) 10 b) 7 ) 32 Q31: How many memory loations an be diretly addressed using 8 bits? a) 8 b) 256 ) 16 Ý

29 2.5. BUSES 59 Generally then, The number of memory loations = 2width of address bus Thus, a 24-bit address bus will be able to distinguish between: 2 24 = 16,777,216 memory loations Addressability When the proessor has to send or reeive data or instrutions from memory, ahe or external devies, the medium along whih the signal is arried is known as a bus. This is a set of wires or lines that an eah transmit 1 bit at a time. Thus when an instrution is read from memory the bits are plaed on the data bus and moved in parallel to the proessor. Typially the data bus will be the same size as one memory loation. While the data bus moves data and instrutions, a seond bus, the address bus arries the address of the memory loation to be aessed. The size of the address bus affets the amount of main memory offered. If there were 8 address lines able to transmit 8 bits the maximum number of different addresses would be Þ«ßÊàÞáâ A 32 bit address bus addressing up to 4 Gb of memory is a more typial urrent size. When an address is being speified there has to be a way to determine whether it refers to a main memory address or to one of the I/O interfaes that ontrol ommuniation with other peripheral devies. This an be done in two ways. Memory mapped I/O If the interfae is memory mapped, a blok of main memory addresses is mapped to the I/O interfae. In this way the addressing proess is exatly the same for main memory or I/O. If there is no memory mapping the destination is defined by a signal on one of the ontrol lines. This means that the same address values an be used for I/O and memory without onfusion. The address bus is effetively one way (uni-diretional) while the data bus an transfer data in both diretions (bi-diretional), outwards for a write operation and inwards for a read operation. A third bus, the ontrol bus has the signal that identifies the type of operation, read or ã

30 ä ä ä ä 60 TOPIC 2. COMPUTER STRUCTURE write. This an take 4 signals: read from memory; write to memory; read from I/O; write to I/O. Therefore to feth an instrution or data item from memory all 3 buses are used. Address bus Data bus Control bus This is illustrated in Figure 2.7 address in memory or I/O devie data to be written to or data being read from memory operation read / write memory or read/write I/O Data bus CPU Control bus Address bus I/O interfae Cahe I/O interfae Memory Figure 2.7: Data bus The data bus is used to transfer data to and from the CPU. The data bus is a bi-diretional bus whih transfers data in both diretions. In a single bus system, the data bus is shared by main memory and external devies suh as sreens, printers and disk drives. You an appreiate why this bus needs to be bi-diretional if you onsider some typial operations that are arried out. For instane, the CPU must feth instrutions from main memory whih requires transfer in the diretion from main memory to the CPU. If å

31 æ æ æ æ æ æ æ æ 2.6. SUMMARY 61 the stored program has instrutions to alulate values and update variables, then the results of the alulations need to be stored in main memory. This requires a transfer of data from the CPU registers to main memory. In the ase of ommuniating with an external devie, suh as a hard disk, data must be loaded from the devie and also saved to the devie. This requires bi-diretional data transfer Review questions Q32: The purpose of the address bus is to: a) initiate a read from memory operation b) arry a memory address from whih data an be read or to whih data an be written ) store results of alulations Q33: Why is the address bus desribed as uni-diretional? Q34: The data bus is used: a) to store the results of alulations b) to signal a read event ) to arry data/instrutions from main memory to CPU or to arry data from CPU to main memory 2.6 Summary The following summary points are related to the learning objetives in the topi introdution: Organisation of the omponent parts of a omputer system; Desription and struture of the omponents parts of a proessor; The stored program onept and the feth-exeute yle; The funtion of the proessor omponents; Control lines funtions and timings; The use of buses; The storage of data using registers, ahe, memory and baking storage; Aessing memory. 2.7 End of topi test An online assessment is provided to help you review this topi. ç

32 62 TOPIC 2. COMPUTER STRUCTURE è